Daniel Vetter | 7dc0001 | 2014-03-22 15:31:15 +0100 | [diff] [blame] | 1 | #include <stdlib.h> |
| 2 | #include <sys/ioctl.h> |
| 3 | #include <stdio.h> |
| 4 | #include <string.h> |
| 5 | #include <assert.h> |
| 6 | #include <fcntl.h> |
| 7 | #include <inttypes.h> |
| 8 | #include <errno.h> |
| 9 | #include <sys/stat.h> |
| 10 | #include <sys/time.h> |
Daniel Vetter | 7dc0001 | 2014-03-22 15:31:15 +0100 | [diff] [blame] | 11 | #include "drm.h" |
| 12 | #include "i915_drm.h" |
| 13 | #include "drmtest.h" |
| 14 | #include "intel_bufmgr.h" |
| 15 | #include "intel_batchbuffer.h" |
Daniel Vetter | c03c6ce | 2014-03-22 21:34:29 +0100 | [diff] [blame] | 16 | #include "intel_io.h" |
Daniel Vetter | 7dc0001 | 2014-03-22 15:31:15 +0100 | [diff] [blame] | 17 | |
Daniel Vetter | a6751ba | 2011-03-31 23:29:25 +0200 | [diff] [blame] | 18 | #include "i915_reg.h" |
| 19 | #include "i915_3d.h" |
Daniel Vetter | 1357427 | 2012-01-18 17:53:12 +0100 | [diff] [blame] | 20 | #include "rendercopy.h" |
Daniel Vetter | a6751ba | 2011-03-31 23:29:25 +0200 | [diff] [blame] | 21 | |
Daniel Vetter | f1de285 | 2012-01-18 00:55:49 +0100 | [diff] [blame] | 22 | void gen3_render_copyfunc(struct intel_batchbuffer *batch, |
Ville Syrjälä | 725da6e | 2013-11-21 19:05:17 +0200 | [diff] [blame] | 23 | drm_intel_context *context, |
Daniel Vetter | 83a4c7d | 2014-03-22 15:44:48 +0100 | [diff] [blame] | 24 | struct igt_buf *src, unsigned src_x, unsigned src_y, |
Daniel Vetter | 9f20ecc | 2012-01-18 17:46:00 +0100 | [diff] [blame] | 25 | unsigned width, unsigned height, |
Daniel Vetter | 83a4c7d | 2014-03-22 15:44:48 +0100 | [diff] [blame] | 26 | struct igt_buf *dst, unsigned dst_x, unsigned dst_y) |
Daniel Vetter | a6751ba | 2011-03-31 23:29:25 +0200 | [diff] [blame] | 27 | { |
Daniel Vetter | a6751ba | 2011-03-31 23:29:25 +0200 | [diff] [blame] | 28 | /* invariant state */ |
| 29 | { |
| 30 | OUT_BATCH(_3DSTATE_AA_CMD | |
| 31 | AA_LINE_ECAAR_WIDTH_ENABLE | |
| 32 | AA_LINE_ECAAR_WIDTH_1_0 | |
| 33 | AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0); |
| 34 | OUT_BATCH(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD | |
| 35 | IAB_MODIFY_ENABLE | |
| 36 | IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) | |
| 37 | IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE << |
| 38 | IAB_SRC_FACTOR_SHIFT) | |
| 39 | IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO << |
| 40 | IAB_DST_FACTOR_SHIFT)); |
| 41 | OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); |
| 42 | OUT_BATCH(0); |
| 43 | OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); |
| 44 | OUT_BATCH(0); |
| 45 | OUT_BATCH(_3DSTATE_DFLT_Z_CMD); |
| 46 | OUT_BATCH(0); |
| 47 | OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS | |
| 48 | CSB_TCB(0, 0) | |
| 49 | CSB_TCB(1, 1) | |
| 50 | CSB_TCB(2, 2) | |
| 51 | CSB_TCB(3, 3) | |
| 52 | CSB_TCB(4, 4) | |
| 53 | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7)); |
| 54 | OUT_BATCH(_3DSTATE_RASTER_RULES_CMD | |
| 55 | ENABLE_POINT_RASTER_RULE | |
| 56 | OGL_POINT_RASTER_RULE | |
| 57 | ENABLE_LINE_STRIP_PROVOKE_VRTX | |
| 58 | ENABLE_TRI_FAN_PROVOKE_VRTX | |
| 59 | LINE_STRIP_PROVOKE_VRTX(1) | |
| 60 | TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D); |
| 61 | OUT_BATCH(_3DSTATE_MODES_4_CMD | |
| 62 | ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) | |
| 63 | ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) | |
| 64 | ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff)); |
| 65 | OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | I1_LOAD_S(4) | I1_LOAD_S(5) | 2); |
| 66 | OUT_BATCH(0x00000000); /* Disable texture coordinate wrap-shortest */ |
| 67 | OUT_BATCH((1 << S4_POINT_WIDTH_SHIFT) | |
| 68 | S4_LINE_WIDTH_ONE | |
| 69 | S4_CULLMODE_NONE | |
| 70 | S4_VFMT_XY); |
| 71 | OUT_BATCH(0x00000000); /* Stencil. */ |
| 72 | OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); |
| 73 | OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD); |
| 74 | OUT_BATCH(0); |
| 75 | OUT_BATCH(0); |
| 76 | OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE); |
| 77 | OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */ |
| 78 | OUT_BATCH(0); |
| 79 | OUT_BATCH(_3DSTATE_STIPPLE); |
| 80 | OUT_BATCH(0x00000000); |
| 81 | OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0); |
| 82 | } |
| 83 | |
| 84 | /* samler state */ |
| 85 | { |
| 86 | #define TEX_COUNT 1 |
| 87 | uint32_t tiling_bits = 0; |
| 88 | if (src->tiling != I915_TILING_NONE) |
| 89 | tiling_bits = MS3_TILED_SURFACE; |
| 90 | if (src->tiling == I915_TILING_Y) |
| 91 | tiling_bits |= MS3_TILE_WALK; |
| 92 | |
| 93 | OUT_BATCH(_3DSTATE_MAP_STATE | (3 * TEX_COUNT)); |
| 94 | OUT_BATCH((1 << TEX_COUNT) - 1); |
| 95 | OUT_RELOC(src->bo, I915_GEM_DOMAIN_SAMPLER, 0, 0); |
| 96 | OUT_BATCH(MAPSURF_32BIT | MT_32BIT_ARGB8888 | |
| 97 | tiling_bits | |
Daniel Vetter | 83a4c7d | 2014-03-22 15:44:48 +0100 | [diff] [blame] | 98 | (igt_buf_height(src) - 1) << MS3_HEIGHT_SHIFT | |
| 99 | (igt_buf_width(src) - 1) << MS3_WIDTH_SHIFT); |
Daniel Vetter | a6751ba | 2011-03-31 23:29:25 +0200 | [diff] [blame] | 100 | OUT_BATCH((src->stride/4-1) << MS4_PITCH_SHIFT); |
| 101 | |
| 102 | OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * TEX_COUNT)); |
| 103 | OUT_BATCH((1 << TEX_COUNT) - 1); |
| 104 | OUT_BATCH(MIPFILTER_NONE << SS2_MIP_FILTER_SHIFT | |
| 105 | FILTER_NEAREST << SS2_MAG_FILTER_SHIFT | |
| 106 | FILTER_NEAREST << SS2_MIN_FILTER_SHIFT); |
Chris Wilson | f5e63b1 | 2011-06-05 17:23:09 +0100 | [diff] [blame] | 107 | OUT_BATCH(TEXCOORDMODE_WRAP << SS3_TCX_ADDR_MODE_SHIFT | |
Daniel Vetter | a6751ba | 2011-03-31 23:29:25 +0200 | [diff] [blame] | 108 | TEXCOORDMODE_WRAP << SS3_TCY_ADDR_MODE_SHIFT | |
| 109 | 0 << SS3_TEXTUREMAP_INDEX_SHIFT); |
| 110 | OUT_BATCH(0x00000000); |
| 111 | } |
| 112 | |
| 113 | /* render target state */ |
| 114 | { |
| 115 | uint32_t tiling_bits = 0; |
| 116 | if (dst->tiling != I915_TILING_NONE) |
| 117 | tiling_bits = BUF_3D_TILED_SURFACE; |
| 118 | if (dst->tiling == I915_TILING_Y) |
| 119 | tiling_bits |= BUF_3D_TILE_WALK_Y; |
| 120 | |
| 121 | OUT_BATCH(_3DSTATE_BUF_INFO_CMD); |
| 122 | OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits | |
| 123 | BUF_3D_PITCH(dst->stride)); |
| 124 | OUT_RELOC(dst->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); |
| 125 | |
| 126 | OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD); |
| 127 | OUT_BATCH(COLR_BUF_ARGB8888 | |
| 128 | DSTORG_HORT_BIAS(0x8) | |
| 129 | DSTORG_VERT_BIAS(0x8)); |
| 130 | |
| 131 | /* draw rect is unconditional */ |
| 132 | OUT_BATCH(_3DSTATE_DRAW_RECT_CMD); |
| 133 | OUT_BATCH(0x00000000); |
| 134 | OUT_BATCH(0x00000000); /* ymin, xmin */ |
Daniel Vetter | 83a4c7d | 2014-03-22 15:44:48 +0100 | [diff] [blame] | 135 | OUT_BATCH(DRAW_YMAX(igt_buf_height(dst) - 1) | |
| 136 | DRAW_XMAX(igt_buf_width(dst) - 1)); |
Daniel Vetter | a6751ba | 2011-03-31 23:29:25 +0200 | [diff] [blame] | 137 | /* yorig, xorig (relate to color buffer?) */ |
| 138 | OUT_BATCH(0x00000000); |
| 139 | } |
| 140 | |
| 141 | /* texfmt */ |
| 142 | { |
Chris Wilson | f5e63b1 | 2011-06-05 17:23:09 +0100 | [diff] [blame] | 143 | OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | |
| 144 | I1_LOAD_S(1) | I1_LOAD_S(2) | I1_LOAD_S(6) | 2); |
| 145 | OUT_BATCH((4 << S1_VERTEX_WIDTH_SHIFT) | |
| 146 | (4 << S1_VERTEX_PITCH_SHIFT)); |
| 147 | OUT_BATCH(~S2_TEXCOORD_FMT(0, TEXCOORDFMT_NOT_PRESENT) | S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D)); |
Daniel Vetter | a6751ba | 2011-03-31 23:29:25 +0200 | [diff] [blame] | 148 | OUT_BATCH(S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE | |
| 149 | BLENDFUNC_ADD << S6_CBUF_BLEND_FUNC_SHIFT | |
| 150 | BLENDFACT_ONE << S6_CBUF_SRC_BLEND_FACT_SHIFT | |
| 151 | BLENDFACT_ZERO << S6_CBUF_DST_BLEND_FACT_SHIFT); |
Daniel Vetter | a6751ba | 2011-03-31 23:29:25 +0200 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | /* frage shader */ |
| 155 | { |
| 156 | OUT_BATCH(_3DSTATE_PIXEL_SHADER_PROGRAM | (1 + 3*3 - 2)); |
| 157 | /* decl FS_T0 */ |
| 158 | OUT_BATCH(D0_DCL | |
| 159 | REG_TYPE(FS_T0) << D0_TYPE_SHIFT | |
| 160 | REG_NR(FS_T0) << D0_NR_SHIFT | |
| 161 | ((REG_TYPE(FS_T0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0)); |
| 162 | OUT_BATCH(0); |
| 163 | OUT_BATCH(0); |
| 164 | /* decl FS_S0 */ |
| 165 | OUT_BATCH(D0_DCL | |
| 166 | (REG_TYPE(FS_S0) << D0_TYPE_SHIFT) | |
| 167 | (REG_NR(FS_S0) << D0_NR_SHIFT) | |
| 168 | ((REG_TYPE(FS_S0) != REG_TYPE_S) ? D0_CHANNEL_ALL : 0)); |
| 169 | OUT_BATCH(0); |
| 170 | OUT_BATCH(0); |
| 171 | /* texld(FS_OC, FS_S0, FS_T0 */ |
| 172 | OUT_BATCH(T0_TEXLD | |
| 173 | (REG_TYPE(FS_OC) << T0_DEST_TYPE_SHIFT) | |
| 174 | (REG_NR(FS_OC) << T0_DEST_NR_SHIFT) | |
| 175 | (REG_NR(FS_S0) << T0_SAMPLER_NR_SHIFT)); |
| 176 | OUT_BATCH((REG_TYPE(FS_T0) << T1_ADDRESS_REG_TYPE_SHIFT) | |
| 177 | (REG_NR(FS_T0) << T1_ADDRESS_REG_NR_SHIFT)); |
| 178 | OUT_BATCH(0); |
| 179 | } |
| 180 | |
| 181 | OUT_BATCH(PRIM3D_RECTLIST | (3*4 - 1)); |
Daniel Vetter | 9f20ecc | 2012-01-18 17:46:00 +0100 | [diff] [blame] | 182 | emit_vertex(batch, dst_x + width); |
| 183 | emit_vertex(batch, dst_y + height); |
| 184 | emit_vertex(batch, src_x + width); |
| 185 | emit_vertex(batch, src_y + height); |
Daniel Vetter | a6751ba | 2011-03-31 23:29:25 +0200 | [diff] [blame] | 186 | |
Daniel Vetter | f1de285 | 2012-01-18 00:55:49 +0100 | [diff] [blame] | 187 | emit_vertex(batch, dst_x); |
Daniel Vetter | 9f20ecc | 2012-01-18 17:46:00 +0100 | [diff] [blame] | 188 | emit_vertex(batch, dst_y + height); |
Daniel Vetter | f1de285 | 2012-01-18 00:55:49 +0100 | [diff] [blame] | 189 | emit_vertex(batch, src_x); |
Daniel Vetter | 9f20ecc | 2012-01-18 17:46:00 +0100 | [diff] [blame] | 190 | emit_vertex(batch, src_y + height); |
Daniel Vetter | a6751ba | 2011-03-31 23:29:25 +0200 | [diff] [blame] | 191 | |
Daniel Vetter | f1de285 | 2012-01-18 00:55:49 +0100 | [diff] [blame] | 192 | emit_vertex(batch, dst_x); |
| 193 | emit_vertex(batch, dst_y); |
| 194 | emit_vertex(batch, src_x); |
| 195 | emit_vertex(batch, src_y); |
Daniel Vetter | a6751ba | 2011-03-31 23:29:25 +0200 | [diff] [blame] | 196 | |
Daniel Vetter | a6751ba | 2011-03-31 23:29:25 +0200 | [diff] [blame] | 197 | intel_batchbuffer_flush(batch); |
| 198 | } |