Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
| 2 | * |
| 3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. |
| 4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. |
| 5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the "Software"), |
| 10 | * to deal in the Software without restriction, including without limitation |
| 11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 12 | * and/or sell copies of the Software, and to permit persons to whom the |
| 13 | * Software is furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice shall be included in |
| 16 | * all copies or substantial portions of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 24 | * OTHER DEALINGS IN THE SOFTWARE. |
| 25 | * |
| 26 | * Authors: |
| 27 | * Kevin E. Martin <martin@valinux.com> |
| 28 | * Gareth Hughes <gareth@valinux.com> |
| 29 | * Keith Whitwell <keith@tungstengraphics.com> |
| 30 | */ |
| 31 | |
| 32 | #ifndef __AMDGPU_DRM_H__ |
| 33 | #define __AMDGPU_DRM_H__ |
| 34 | |
| 35 | #include "drm.h" |
| 36 | |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 37 | #if defined(__cplusplus) |
| 38 | extern "C" { |
| 39 | #endif |
| 40 | |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 41 | #define DRM_AMDGPU_GEM_CREATE 0x00 |
| 42 | #define DRM_AMDGPU_GEM_MMAP 0x01 |
| 43 | #define DRM_AMDGPU_CTX 0x02 |
| 44 | #define DRM_AMDGPU_BO_LIST 0x03 |
| 45 | #define DRM_AMDGPU_CS 0x04 |
| 46 | #define DRM_AMDGPU_INFO 0x05 |
| 47 | #define DRM_AMDGPU_GEM_METADATA 0x06 |
| 48 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 |
| 49 | #define DRM_AMDGPU_GEM_VA 0x08 |
| 50 | #define DRM_AMDGPU_WAIT_CS 0x09 |
| 51 | #define DRM_AMDGPU_GEM_OP 0x10 |
| 52 | #define DRM_AMDGPU_GEM_USERPTR 0x11 |
Christopher Ferris | 2fd4b3c | 2017-02-21 12:32:08 -0800 | [diff] [blame] | 53 | #define DRM_AMDGPU_WAIT_FENCES 0x12 |
Christopher Ferris | 2598113 | 2017-11-14 16:53:49 -0800 | [diff] [blame] | 54 | #define DRM_AMDGPU_VM 0x13 |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 55 | |
| 56 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) |
| 57 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) |
| 58 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) |
| 59 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) |
| 60 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) |
| 61 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) |
| 62 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) |
| 63 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) |
| 64 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
| 65 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
| 66 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) |
| 67 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) |
Christopher Ferris | 2fd4b3c | 2017-02-21 12:32:08 -0800 | [diff] [blame] | 68 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) |
Christopher Ferris | 2598113 | 2017-11-14 16:53:49 -0800 | [diff] [blame] | 69 | #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 70 | |
| 71 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 |
| 72 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 |
| 73 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 |
| 74 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 |
| 75 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 |
| 76 | #define AMDGPU_GEM_DOMAIN_OA 0x20 |
| 77 | |
| 78 | /* Flag that CPU access will be required for the case of VRAM domain */ |
| 79 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) |
| 80 | /* Flag that CPU access will not work, this VRAM domain is invisible */ |
| 81 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) |
| 82 | /* Flag that USWC attributes should be used for GTT */ |
| 83 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
Christopher Ferris | 3318540 | 2017-01-13 13:28:52 -0800 | [diff] [blame] | 84 | /* Flag that the memory should be in VRAM and cleared */ |
| 85 | #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) |
| 86 | /* Flag that create shadow bo(GTT) while allocating vram bo */ |
| 87 | #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) |
Christopher Ferris | 2fd4b3c | 2017-02-21 12:32:08 -0800 | [diff] [blame] | 88 | /* Flag that allocating the BO should use linear VRAM */ |
| 89 | #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 90 | |
| 91 | struct drm_amdgpu_gem_create_in { |
| 92 | /** the requested memory size */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 93 | __u64 bo_size; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 94 | /** physical start_addr alignment in bytes for some HW requirements */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 95 | __u64 alignment; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 96 | /** the requested memory domains */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 97 | __u64 domains; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 98 | /** allocation flags */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 99 | __u64 domain_flags; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 100 | }; |
| 101 | |
| 102 | struct drm_amdgpu_gem_create_out { |
| 103 | /** returned GEM object handle */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 104 | __u32 handle; |
| 105 | __u32 _pad; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 106 | }; |
| 107 | |
| 108 | union drm_amdgpu_gem_create { |
| 109 | struct drm_amdgpu_gem_create_in in; |
| 110 | struct drm_amdgpu_gem_create_out out; |
| 111 | }; |
| 112 | |
| 113 | /** Opcode to create new residency list. */ |
| 114 | #define AMDGPU_BO_LIST_OP_CREATE 0 |
| 115 | /** Opcode to destroy previously created residency list */ |
| 116 | #define AMDGPU_BO_LIST_OP_DESTROY 1 |
| 117 | /** Opcode to update resource information in the list */ |
| 118 | #define AMDGPU_BO_LIST_OP_UPDATE 2 |
| 119 | |
| 120 | struct drm_amdgpu_bo_list_in { |
| 121 | /** Type of operation */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 122 | __u32 operation; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 123 | /** Handle of list or 0 if we want to create one */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 124 | __u32 list_handle; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 125 | /** Number of BOs in list */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 126 | __u32 bo_number; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 127 | /** Size of each element describing BO */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 128 | __u32 bo_info_size; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 129 | /** Pointer to array describing BOs */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 130 | __u64 bo_info_ptr; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 131 | }; |
| 132 | |
| 133 | struct drm_amdgpu_bo_list_entry { |
| 134 | /** Handle of BO */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 135 | __u32 bo_handle; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 136 | /** New (if specified) BO priority to be used during migration */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 137 | __u32 bo_priority; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 138 | }; |
| 139 | |
| 140 | struct drm_amdgpu_bo_list_out { |
| 141 | /** Handle of resource list */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 142 | __u32 list_handle; |
| 143 | __u32 _pad; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 144 | }; |
| 145 | |
| 146 | union drm_amdgpu_bo_list { |
| 147 | struct drm_amdgpu_bo_list_in in; |
| 148 | struct drm_amdgpu_bo_list_out out; |
| 149 | }; |
| 150 | |
| 151 | /* context related */ |
| 152 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 |
| 153 | #define AMDGPU_CTX_OP_FREE_CTX 2 |
| 154 | #define AMDGPU_CTX_OP_QUERY_STATE 3 |
| 155 | |
| 156 | /* GPU reset status */ |
| 157 | #define AMDGPU_CTX_NO_RESET 0 |
| 158 | /* this the context caused it */ |
| 159 | #define AMDGPU_CTX_GUILTY_RESET 1 |
| 160 | /* some other context caused it */ |
| 161 | #define AMDGPU_CTX_INNOCENT_RESET 2 |
| 162 | /* unknown cause */ |
| 163 | #define AMDGPU_CTX_UNKNOWN_RESET 3 |
| 164 | |
| 165 | struct drm_amdgpu_ctx_in { |
| 166 | /** AMDGPU_CTX_OP_* */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 167 | __u32 op; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 168 | /** For future use, no flags defined so far */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 169 | __u32 flags; |
| 170 | __u32 ctx_id; |
| 171 | __u32 _pad; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 172 | }; |
| 173 | |
| 174 | union drm_amdgpu_ctx_out { |
| 175 | struct { |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 176 | __u32 ctx_id; |
| 177 | __u32 _pad; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 178 | } alloc; |
| 179 | |
| 180 | struct { |
| 181 | /** For future use, no flags defined so far */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 182 | __u64 flags; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 183 | /** Number of resets caused by this context so far. */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 184 | __u32 hangs; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 185 | /** Reset status since the last call of the ioctl. */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 186 | __u32 reset_status; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 187 | } state; |
| 188 | }; |
| 189 | |
| 190 | union drm_amdgpu_ctx { |
| 191 | struct drm_amdgpu_ctx_in in; |
| 192 | union drm_amdgpu_ctx_out out; |
| 193 | }; |
| 194 | |
Christopher Ferris | 2598113 | 2017-11-14 16:53:49 -0800 | [diff] [blame] | 195 | /* vm ioctl */ |
| 196 | #define AMDGPU_VM_OP_RESERVE_VMID 1 |
| 197 | #define AMDGPU_VM_OP_UNRESERVE_VMID 2 |
| 198 | |
| 199 | struct drm_amdgpu_vm_in { |
| 200 | /** AMDGPU_VM_OP_* */ |
| 201 | __u32 op; |
| 202 | __u32 flags; |
| 203 | }; |
| 204 | |
| 205 | struct drm_amdgpu_vm_out { |
| 206 | /** For future use, no flags defined so far */ |
| 207 | __u64 flags; |
| 208 | }; |
| 209 | |
| 210 | union drm_amdgpu_vm { |
| 211 | struct drm_amdgpu_vm_in in; |
| 212 | struct drm_amdgpu_vm_out out; |
| 213 | }; |
| 214 | |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 215 | /* |
| 216 | * This is not a reliable API and you should expect it to fail for any |
| 217 | * number of reasons and have fallback path that do not use userptr to |
| 218 | * perform any operation. |
| 219 | */ |
| 220 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) |
| 221 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) |
| 222 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) |
| 223 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) |
| 224 | |
| 225 | struct drm_amdgpu_gem_userptr { |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 226 | __u64 addr; |
| 227 | __u64 size; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 228 | /* AMDGPU_GEM_USERPTR_* */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 229 | __u32 flags; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 230 | /* Resulting GEM handle */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 231 | __u32 handle; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 232 | }; |
| 233 | |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 234 | /* SI-CI-VI: */ |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 235 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
| 236 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 |
| 237 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf |
| 238 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 |
| 239 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f |
| 240 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 |
| 241 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 |
| 242 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 |
| 243 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 |
| 244 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 |
| 245 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 |
| 246 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 |
| 247 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 |
| 248 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 |
| 249 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 |
| 250 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 |
| 251 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 |
| 252 | |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 253 | /* GFX9 and later: */ |
| 254 | #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 |
| 255 | #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f |
| 256 | |
| 257 | /* Set/Get helpers for tiling flags. */ |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 258 | #define AMDGPU_TILING_SET(field, value) \ |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 259 | (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 260 | #define AMDGPU_TILING_GET(value, field) \ |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 261 | (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 262 | |
| 263 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 |
| 264 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 |
| 265 | |
| 266 | /** The same structure is shared for input/output */ |
| 267 | struct drm_amdgpu_gem_metadata { |
| 268 | /** GEM Object handle */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 269 | __u32 handle; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 270 | /** Do we want get or set metadata */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 271 | __u32 op; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 272 | struct { |
| 273 | /** For future use, no flags defined so far */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 274 | __u64 flags; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 275 | /** family specific tiling info */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 276 | __u64 tiling_info; |
| 277 | __u32 data_size_bytes; |
| 278 | __u32 data[64]; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 279 | } data; |
| 280 | }; |
| 281 | |
| 282 | struct drm_amdgpu_gem_mmap_in { |
| 283 | /** the GEM object handle */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 284 | __u32 handle; |
| 285 | __u32 _pad; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 286 | }; |
| 287 | |
| 288 | struct drm_amdgpu_gem_mmap_out { |
| 289 | /** mmap offset from the vma offset manager */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 290 | __u64 addr_ptr; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 291 | }; |
| 292 | |
| 293 | union drm_amdgpu_gem_mmap { |
| 294 | struct drm_amdgpu_gem_mmap_in in; |
| 295 | struct drm_amdgpu_gem_mmap_out out; |
| 296 | }; |
| 297 | |
| 298 | struct drm_amdgpu_gem_wait_idle_in { |
| 299 | /** GEM object handle */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 300 | __u32 handle; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 301 | /** For future use, no flags defined so far */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 302 | __u32 flags; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 303 | /** Absolute timeout to wait */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 304 | __u64 timeout; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 305 | }; |
| 306 | |
| 307 | struct drm_amdgpu_gem_wait_idle_out { |
| 308 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 309 | __u32 status; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 310 | /** Returned current memory domain */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 311 | __u32 domain; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 312 | }; |
| 313 | |
| 314 | union drm_amdgpu_gem_wait_idle { |
| 315 | struct drm_amdgpu_gem_wait_idle_in in; |
| 316 | struct drm_amdgpu_gem_wait_idle_out out; |
| 317 | }; |
| 318 | |
| 319 | struct drm_amdgpu_wait_cs_in { |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 320 | /* Command submission handle |
| 321 | * handle equals 0 means none to wait for |
| 322 | * handle equals ~0ull means wait for the latest sequence number |
| 323 | */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 324 | __u64 handle; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 325 | /** Absolute timeout to wait */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 326 | __u64 timeout; |
| 327 | __u32 ip_type; |
| 328 | __u32 ip_instance; |
| 329 | __u32 ring; |
| 330 | __u32 ctx_id; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 331 | }; |
| 332 | |
| 333 | struct drm_amdgpu_wait_cs_out { |
| 334 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 335 | __u64 status; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 336 | }; |
| 337 | |
| 338 | union drm_amdgpu_wait_cs { |
| 339 | struct drm_amdgpu_wait_cs_in in; |
| 340 | struct drm_amdgpu_wait_cs_out out; |
| 341 | }; |
| 342 | |
Christopher Ferris | 2fd4b3c | 2017-02-21 12:32:08 -0800 | [diff] [blame] | 343 | struct drm_amdgpu_fence { |
| 344 | __u32 ctx_id; |
| 345 | __u32 ip_type; |
| 346 | __u32 ip_instance; |
| 347 | __u32 ring; |
| 348 | __u64 seq_no; |
| 349 | }; |
| 350 | |
| 351 | struct drm_amdgpu_wait_fences_in { |
| 352 | /** This points to uint64_t * which points to fences */ |
| 353 | __u64 fences; |
| 354 | __u32 fence_count; |
| 355 | __u32 wait_all; |
| 356 | __u64 timeout_ns; |
| 357 | }; |
| 358 | |
| 359 | struct drm_amdgpu_wait_fences_out { |
| 360 | __u32 status; |
| 361 | __u32 first_signaled; |
| 362 | }; |
| 363 | |
| 364 | union drm_amdgpu_wait_fences { |
| 365 | struct drm_amdgpu_wait_fences_in in; |
| 366 | struct drm_amdgpu_wait_fences_out out; |
| 367 | }; |
| 368 | |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 369 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
| 370 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 |
| 371 | |
| 372 | /* Sets or returns a value associated with a buffer. */ |
| 373 | struct drm_amdgpu_gem_op { |
| 374 | /** GEM object handle */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 375 | __u32 handle; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 376 | /** AMDGPU_GEM_OP_* */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 377 | __u32 op; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 378 | /** Input or return value */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 379 | __u64 value; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 380 | }; |
| 381 | |
| 382 | #define AMDGPU_VA_OP_MAP 1 |
| 383 | #define AMDGPU_VA_OP_UNMAP 2 |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 384 | #define AMDGPU_VA_OP_CLEAR 3 |
| 385 | #define AMDGPU_VA_OP_REPLACE 4 |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 386 | |
| 387 | /* Delay the page table update till the next CS */ |
| 388 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) |
| 389 | |
| 390 | /* Mapping flags */ |
| 391 | /* readable mapping */ |
| 392 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) |
| 393 | /* writable mapping */ |
| 394 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) |
| 395 | /* executable mapping, new for VI */ |
| 396 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 397 | /* partially resident texture */ |
| 398 | #define AMDGPU_VM_PAGE_PRT (1 << 4) |
| 399 | /* MTYPE flags use bit 5 to 8 */ |
| 400 | #define AMDGPU_VM_MTYPE_MASK (0xf << 5) |
| 401 | /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ |
| 402 | #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) |
| 403 | /* Use NC MTYPE instead of default MTYPE */ |
| 404 | #define AMDGPU_VM_MTYPE_NC (1 << 5) |
| 405 | /* Use WC MTYPE instead of default MTYPE */ |
| 406 | #define AMDGPU_VM_MTYPE_WC (2 << 5) |
| 407 | /* Use CC MTYPE instead of default MTYPE */ |
| 408 | #define AMDGPU_VM_MTYPE_CC (3 << 5) |
| 409 | /* Use UC MTYPE instead of default MTYPE */ |
| 410 | #define AMDGPU_VM_MTYPE_UC (4 << 5) |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 411 | |
| 412 | struct drm_amdgpu_gem_va { |
| 413 | /** GEM object handle */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 414 | __u32 handle; |
| 415 | __u32 _pad; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 416 | /** AMDGPU_VA_OP_* */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 417 | __u32 operation; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 418 | /** AMDGPU_VM_PAGE_* */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 419 | __u32 flags; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 420 | /** va address to assign . Must be correctly aligned.*/ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 421 | __u64 va_address; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 422 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 423 | __u64 offset_in_bo; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 424 | /** Specify mapping size. Must be correctly aligned. */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 425 | __u64 map_size; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 426 | }; |
| 427 | |
| 428 | #define AMDGPU_HW_IP_GFX 0 |
| 429 | #define AMDGPU_HW_IP_COMPUTE 1 |
| 430 | #define AMDGPU_HW_IP_DMA 2 |
| 431 | #define AMDGPU_HW_IP_UVD 3 |
| 432 | #define AMDGPU_HW_IP_VCE 4 |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 433 | #define AMDGPU_HW_IP_UVD_ENC 5 |
Christopher Ferris | 2598113 | 2017-11-14 16:53:49 -0800 | [diff] [blame] | 434 | #define AMDGPU_HW_IP_VCN_DEC 6 |
| 435 | #define AMDGPU_HW_IP_VCN_ENC 7 |
| 436 | #define AMDGPU_HW_IP_NUM 8 |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 437 | |
| 438 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 |
| 439 | |
| 440 | #define AMDGPU_CHUNK_ID_IB 0x01 |
| 441 | #define AMDGPU_CHUNK_ID_FENCE 0x02 |
| 442 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
Christopher Ferris | 2598113 | 2017-11-14 16:53:49 -0800 | [diff] [blame] | 443 | #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 |
| 444 | #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 445 | |
| 446 | struct drm_amdgpu_cs_chunk { |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 447 | __u32 chunk_id; |
| 448 | __u32 length_dw; |
| 449 | __u64 chunk_data; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 450 | }; |
| 451 | |
| 452 | struct drm_amdgpu_cs_in { |
| 453 | /** Rendering context id */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 454 | __u32 ctx_id; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 455 | /** Handle of resource list associated with CS */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 456 | __u32 bo_list_handle; |
| 457 | __u32 num_chunks; |
| 458 | __u32 _pad; |
| 459 | /** this points to __u64 * which point to cs chunks */ |
| 460 | __u64 chunks; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 461 | }; |
| 462 | |
| 463 | struct drm_amdgpu_cs_out { |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 464 | __u64 handle; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 465 | }; |
| 466 | |
| 467 | union drm_amdgpu_cs { |
| 468 | struct drm_amdgpu_cs_in in; |
| 469 | struct drm_amdgpu_cs_out out; |
| 470 | }; |
| 471 | |
| 472 | /* Specify flags to be used for IB */ |
| 473 | |
| 474 | /* This IB should be submitted to CE */ |
| 475 | #define AMDGPU_IB_FLAG_CE (1<<0) |
| 476 | |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 477 | /* Preamble flag, which means the IB could be dropped if no context switch */ |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 478 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
| 479 | |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 480 | /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ |
| 481 | #define AMDGPU_IB_FLAG_PREEMPT (1<<2) |
| 482 | |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 483 | struct drm_amdgpu_cs_chunk_ib { |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 484 | __u32 _pad; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 485 | /** AMDGPU_IB_FLAG_* */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 486 | __u32 flags; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 487 | /** Virtual address to begin IB execution */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 488 | __u64 va_start; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 489 | /** Size of submission */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 490 | __u32 ib_bytes; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 491 | /** HW IP to submit to */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 492 | __u32 ip_type; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 493 | /** HW IP index of the same type to submit to */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 494 | __u32 ip_instance; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 495 | /** Ring index to submit to */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 496 | __u32 ring; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 497 | }; |
| 498 | |
| 499 | struct drm_amdgpu_cs_chunk_dep { |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 500 | __u32 ip_type; |
| 501 | __u32 ip_instance; |
| 502 | __u32 ring; |
| 503 | __u32 ctx_id; |
| 504 | __u64 handle; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 505 | }; |
| 506 | |
| 507 | struct drm_amdgpu_cs_chunk_fence { |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 508 | __u32 handle; |
| 509 | __u32 offset; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 510 | }; |
| 511 | |
Christopher Ferris | 2598113 | 2017-11-14 16:53:49 -0800 | [diff] [blame] | 512 | struct drm_amdgpu_cs_chunk_sem { |
| 513 | __u32 handle; |
| 514 | }; |
| 515 | |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 516 | struct drm_amdgpu_cs_chunk_data { |
| 517 | union { |
| 518 | struct drm_amdgpu_cs_chunk_ib ib_data; |
| 519 | struct drm_amdgpu_cs_chunk_fence fence_data; |
| 520 | }; |
| 521 | }; |
| 522 | |
| 523 | /** |
| 524 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU |
| 525 | * |
| 526 | */ |
| 527 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 |
Christopher Ferris | 2fd4b3c | 2017-02-21 12:32:08 -0800 | [diff] [blame] | 528 | #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 529 | |
| 530 | /* indicate if acceleration can be working */ |
| 531 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 |
| 532 | /* get the crtc_id from the mode object id? */ |
| 533 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 |
| 534 | /* query hw IP info */ |
| 535 | #define AMDGPU_INFO_HW_IP_INFO 0x02 |
| 536 | /* query hw IP instance count for the specified type */ |
| 537 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 |
| 538 | /* timestamp for GL_ARB_timer_query */ |
| 539 | #define AMDGPU_INFO_TIMESTAMP 0x05 |
| 540 | /* Query the firmware version */ |
| 541 | #define AMDGPU_INFO_FW_VERSION 0x0e |
| 542 | /* Subquery id: Query VCE firmware version */ |
| 543 | #define AMDGPU_INFO_FW_VCE 0x1 |
| 544 | /* Subquery id: Query UVD firmware version */ |
| 545 | #define AMDGPU_INFO_FW_UVD 0x2 |
| 546 | /* Subquery id: Query GMC firmware version */ |
| 547 | #define AMDGPU_INFO_FW_GMC 0x03 |
| 548 | /* Subquery id: Query GFX ME firmware version */ |
| 549 | #define AMDGPU_INFO_FW_GFX_ME 0x04 |
| 550 | /* Subquery id: Query GFX PFP firmware version */ |
| 551 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 |
| 552 | /* Subquery id: Query GFX CE firmware version */ |
| 553 | #define AMDGPU_INFO_FW_GFX_CE 0x06 |
| 554 | /* Subquery id: Query GFX RLC firmware version */ |
| 555 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 |
| 556 | /* Subquery id: Query GFX MEC firmware version */ |
| 557 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 |
| 558 | /* Subquery id: Query SMC firmware version */ |
| 559 | #define AMDGPU_INFO_FW_SMC 0x0a |
| 560 | /* Subquery id: Query SDMA firmware version */ |
| 561 | #define AMDGPU_INFO_FW_SDMA 0x0b |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 562 | /* Subquery id: Query PSP SOS firmware version */ |
| 563 | #define AMDGPU_INFO_FW_SOS 0x0c |
| 564 | /* Subquery id: Query PSP ASD firmware version */ |
| 565 | #define AMDGPU_INFO_FW_ASD 0x0d |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 566 | /* number of bytes moved for TTM migration */ |
| 567 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f |
| 568 | /* the used VRAM size */ |
| 569 | #define AMDGPU_INFO_VRAM_USAGE 0x10 |
| 570 | /* the used GTT size */ |
| 571 | #define AMDGPU_INFO_GTT_USAGE 0x11 |
| 572 | /* Information about GDS, etc. resource configuration */ |
| 573 | #define AMDGPU_INFO_GDS_CONFIG 0x13 |
| 574 | /* Query information about VRAM and GTT domains */ |
| 575 | #define AMDGPU_INFO_VRAM_GTT 0x14 |
| 576 | /* Query information about register in MMR address space*/ |
| 577 | #define AMDGPU_INFO_READ_MMR_REG 0x15 |
| 578 | /* Query information about device: rev id, family, etc. */ |
| 579 | #define AMDGPU_INFO_DEV_INFO 0x16 |
| 580 | /* visible vram usage */ |
| 581 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 |
Christopher Ferris | 3318540 | 2017-01-13 13:28:52 -0800 | [diff] [blame] | 582 | /* number of TTM buffer evictions */ |
| 583 | #define AMDGPU_INFO_NUM_EVICTIONS 0x18 |
Christopher Ferris | 2fd4b3c | 2017-02-21 12:32:08 -0800 | [diff] [blame] | 584 | /* Query memory about VRAM and GTT domains */ |
| 585 | #define AMDGPU_INFO_MEMORY 0x19 |
| 586 | /* Query vce clock table */ |
| 587 | #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A |
| 588 | /* Query vbios related information */ |
| 589 | #define AMDGPU_INFO_VBIOS 0x1B |
| 590 | /* Subquery id: Query vbios size */ |
| 591 | #define AMDGPU_INFO_VBIOS_SIZE 0x1 |
| 592 | /* Subquery id: Query vbios image */ |
| 593 | #define AMDGPU_INFO_VBIOS_IMAGE 0x2 |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 594 | /* Query UVD handles */ |
| 595 | #define AMDGPU_INFO_NUM_HANDLES 0x1C |
| 596 | /* Query sensor related information */ |
| 597 | #define AMDGPU_INFO_SENSOR 0x1D |
| 598 | /* Subquery id: Query GPU shader clock */ |
| 599 | #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 |
| 600 | /* Subquery id: Query GPU memory clock */ |
| 601 | #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 |
| 602 | /* Subquery id: Query GPU temperature */ |
| 603 | #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 |
| 604 | /* Subquery id: Query GPU load */ |
| 605 | #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 |
| 606 | /* Subquery id: Query average GPU power */ |
| 607 | #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 |
| 608 | /* Subquery id: Query northbridge voltage */ |
| 609 | #define AMDGPU_INFO_SENSOR_VDDNB 0x6 |
| 610 | /* Subquery id: Query graphics voltage */ |
| 611 | #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 |
Christopher Ferris | 2598113 | 2017-11-14 16:53:49 -0800 | [diff] [blame] | 612 | /* Number of VRAM page faults on CPU access. */ |
| 613 | #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 614 | |
| 615 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 |
| 616 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff |
| 617 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 |
| 618 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff |
| 619 | |
Christopher Ferris | 6e3550f | 2016-12-12 14:51:18 -0800 | [diff] [blame] | 620 | struct drm_amdgpu_query_fw { |
| 621 | /** AMDGPU_INFO_FW_* */ |
| 622 | __u32 fw_type; |
| 623 | /** |
| 624 | * Index of the IP if there are more IPs of |
| 625 | * the same type. |
| 626 | */ |
| 627 | __u32 ip_instance; |
| 628 | /** |
| 629 | * Index of the engine. Whether this is used depends |
| 630 | * on the firmware type. (e.g. MEC, SDMA) |
| 631 | */ |
| 632 | __u32 index; |
| 633 | __u32 _pad; |
| 634 | }; |
| 635 | |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 636 | /* Input structure for the INFO ioctl */ |
| 637 | struct drm_amdgpu_info { |
| 638 | /* Where the return value will be stored */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 639 | __u64 return_pointer; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 640 | /* The size of the return value. Just like "size" in "snprintf", |
| 641 | * it limits how many bytes the kernel can write. */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 642 | __u32 return_size; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 643 | /* The query request id. */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 644 | __u32 query; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 645 | |
| 646 | union { |
| 647 | struct { |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 648 | __u32 id; |
| 649 | __u32 _pad; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 650 | } mode_crtc; |
| 651 | |
| 652 | struct { |
| 653 | /** AMDGPU_HW_IP_* */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 654 | __u32 type; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 655 | /** |
| 656 | * Index of the IP if there are more IPs of the same |
| 657 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. |
| 658 | */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 659 | __u32 ip_instance; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 660 | } query_hw_ip; |
| 661 | |
| 662 | struct { |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 663 | __u32 dword_offset; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 664 | /** number of registers to read */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 665 | __u32 count; |
| 666 | __u32 instance; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 667 | /** For future use, no flags defined so far */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 668 | __u32 flags; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 669 | } read_mmr_reg; |
| 670 | |
Christopher Ferris | 6e3550f | 2016-12-12 14:51:18 -0800 | [diff] [blame] | 671 | struct drm_amdgpu_query_fw query_fw; |
Christopher Ferris | 2fd4b3c | 2017-02-21 12:32:08 -0800 | [diff] [blame] | 672 | |
| 673 | struct { |
| 674 | __u32 type; |
| 675 | __u32 offset; |
| 676 | } vbios_info; |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 677 | |
| 678 | struct { |
| 679 | __u32 type; |
| 680 | } sensor_info; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 681 | }; |
| 682 | }; |
| 683 | |
| 684 | struct drm_amdgpu_info_gds { |
| 685 | /** GDS GFX partition size */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 686 | __u32 gds_gfx_partition_size; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 687 | /** GDS compute partition size */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 688 | __u32 compute_partition_size; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 689 | /** total GDS memory size */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 690 | __u32 gds_total_size; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 691 | /** GWS size per GFX partition */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 692 | __u32 gws_per_gfx_partition; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 693 | /** GSW size per compute partition */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 694 | __u32 gws_per_compute_partition; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 695 | /** OA size per GFX partition */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 696 | __u32 oa_per_gfx_partition; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 697 | /** OA size per compute partition */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 698 | __u32 oa_per_compute_partition; |
| 699 | __u32 _pad; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 700 | }; |
| 701 | |
| 702 | struct drm_amdgpu_info_vram_gtt { |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 703 | __u64 vram_size; |
| 704 | __u64 vram_cpu_accessible_size; |
| 705 | __u64 gtt_size; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 706 | }; |
| 707 | |
Christopher Ferris | 2fd4b3c | 2017-02-21 12:32:08 -0800 | [diff] [blame] | 708 | struct drm_amdgpu_heap_info { |
| 709 | /** max. physical memory */ |
| 710 | __u64 total_heap_size; |
| 711 | |
| 712 | /** Theoretical max. available memory in the given heap */ |
| 713 | __u64 usable_heap_size; |
| 714 | |
| 715 | /** |
| 716 | * Number of bytes allocated in the heap. This includes all processes |
| 717 | * and private allocations in the kernel. It changes when new buffers |
| 718 | * are allocated, freed, and moved. It cannot be larger than |
| 719 | * heap_size. |
| 720 | */ |
| 721 | __u64 heap_usage; |
| 722 | |
| 723 | /** |
| 724 | * Theoretical possible max. size of buffer which |
| 725 | * could be allocated in the given heap |
| 726 | */ |
| 727 | __u64 max_allocation; |
| 728 | }; |
| 729 | |
| 730 | struct drm_amdgpu_memory_info { |
| 731 | struct drm_amdgpu_heap_info vram; |
| 732 | struct drm_amdgpu_heap_info cpu_accessible_vram; |
| 733 | struct drm_amdgpu_heap_info gtt; |
| 734 | }; |
| 735 | |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 736 | struct drm_amdgpu_info_firmware { |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 737 | __u32 ver; |
| 738 | __u32 feature; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 739 | }; |
| 740 | |
| 741 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
| 742 | #define AMDGPU_VRAM_TYPE_GDDR1 1 |
| 743 | #define AMDGPU_VRAM_TYPE_DDR2 2 |
| 744 | #define AMDGPU_VRAM_TYPE_GDDR3 3 |
| 745 | #define AMDGPU_VRAM_TYPE_GDDR4 4 |
| 746 | #define AMDGPU_VRAM_TYPE_GDDR5 5 |
| 747 | #define AMDGPU_VRAM_TYPE_HBM 6 |
| 748 | #define AMDGPU_VRAM_TYPE_DDR3 7 |
| 749 | |
| 750 | struct drm_amdgpu_info_device { |
| 751 | /** PCI Device ID */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 752 | __u32 device_id; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 753 | /** Internal chip revision: A0, A1, etc.) */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 754 | __u32 chip_rev; |
| 755 | __u32 external_rev; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 756 | /** Revision id in PCI Config space */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 757 | __u32 pci_rev; |
| 758 | __u32 family; |
| 759 | __u32 num_shader_engines; |
| 760 | __u32 num_shader_arrays_per_engine; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 761 | /* in KHz */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 762 | __u32 gpu_counter_freq; |
| 763 | __u64 max_engine_clock; |
| 764 | __u64 max_memory_clock; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 765 | /* cu information */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 766 | __u32 cu_active_number; |
Christopher Ferris | 2598113 | 2017-11-14 16:53:49 -0800 | [diff] [blame] | 767 | /* NOTE: cu_ao_mask is INVALID, DON'T use it */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 768 | __u32 cu_ao_mask; |
| 769 | __u32 cu_bitmap[4][4]; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 770 | /** Render backend pipe mask. One render backend is CB+DB. */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 771 | __u32 enabled_rb_pipes_mask; |
| 772 | __u32 num_rb_pipes; |
| 773 | __u32 num_hw_gfx_contexts; |
| 774 | __u32 _pad; |
| 775 | __u64 ids_flags; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 776 | /** Starting virtual address for UMDs. */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 777 | __u64 virtual_address_offset; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 778 | /** The maximum virtual address */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 779 | __u64 virtual_address_max; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 780 | /** Required alignment of virtual addresses. */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 781 | __u32 virtual_address_alignment; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 782 | /** Page table entry - fragment size */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 783 | __u32 pte_fragment_size; |
| 784 | __u32 gart_page_size; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 785 | /** constant engine ram size*/ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 786 | __u32 ce_ram_size; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 787 | /** video memory type info*/ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 788 | __u32 vram_type; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 789 | /** video memory bit width*/ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 790 | __u32 vram_bit_width; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 791 | /* vce harvesting instance */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 792 | __u32 vce_harvest_config; |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 793 | /* gfx double offchip LDS buffers */ |
| 794 | __u32 gc_double_offchip_lds_buf; |
| 795 | /* NGG Primitive Buffer */ |
| 796 | __u64 prim_buf_gpu_addr; |
| 797 | /* NGG Position Buffer */ |
| 798 | __u64 pos_buf_gpu_addr; |
| 799 | /* NGG Control Sideband */ |
| 800 | __u64 cntl_sb_buf_gpu_addr; |
| 801 | /* NGG Parameter Cache */ |
| 802 | __u64 param_buf_gpu_addr; |
| 803 | __u32 prim_buf_size; |
| 804 | __u32 pos_buf_size; |
| 805 | __u32 cntl_sb_buf_size; |
| 806 | __u32 param_buf_size; |
| 807 | /* wavefront size*/ |
| 808 | __u32 wave_front_size; |
| 809 | /* shader visible vgprs*/ |
| 810 | __u32 num_shader_visible_vgprs; |
| 811 | /* CU per shader array*/ |
| 812 | __u32 num_cu_per_sh; |
| 813 | /* number of tcc blocks*/ |
| 814 | __u32 num_tcc_blocks; |
| 815 | /* gs vgt table depth*/ |
| 816 | __u32 gs_vgt_table_depth; |
| 817 | /* gs primitive buffer depth*/ |
| 818 | __u32 gs_prim_buffer_depth; |
| 819 | /* max gs wavefront per vgt*/ |
| 820 | __u32 max_gs_waves_per_vgt; |
| 821 | __u32 _pad1; |
Christopher Ferris | 2598113 | 2017-11-14 16:53:49 -0800 | [diff] [blame] | 822 | /* always on cu bitmap */ |
| 823 | __u32 cu_ao_bitmap[4][4]; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 824 | }; |
| 825 | |
| 826 | struct drm_amdgpu_info_hw_ip { |
| 827 | /** Version of h/w IP */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 828 | __u32 hw_ip_version_major; |
| 829 | __u32 hw_ip_version_minor; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 830 | /** Capabilities */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 831 | __u64 capabilities_flags; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 832 | /** command buffer address start alignment*/ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 833 | __u32 ib_start_alignment; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 834 | /** command buffer size alignment*/ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 835 | __u32 ib_size_alignment; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 836 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 837 | __u32 available_rings; |
| 838 | __u32 _pad; |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 839 | }; |
| 840 | |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 841 | struct drm_amdgpu_info_num_handles { |
| 842 | /** Max handles as supported by firmware for UVD */ |
| 843 | __u32 uvd_max_handles; |
| 844 | /** Handles currently in use for UVD */ |
| 845 | __u32 uvd_used_handles; |
| 846 | }; |
| 847 | |
Christopher Ferris | 2fd4b3c | 2017-02-21 12:32:08 -0800 | [diff] [blame] | 848 | #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 |
| 849 | |
| 850 | struct drm_amdgpu_info_vce_clock_table_entry { |
| 851 | /** System clock */ |
| 852 | __u32 sclk; |
| 853 | /** Memory clock */ |
| 854 | __u32 mclk; |
| 855 | /** VCE clock */ |
| 856 | __u32 eclk; |
| 857 | __u32 pad; |
| 858 | }; |
| 859 | |
| 860 | struct drm_amdgpu_info_vce_clock_table { |
| 861 | struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; |
| 862 | __u32 num_valid_entries; |
| 863 | __u32 pad; |
| 864 | }; |
| 865 | |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 866 | /* |
| 867 | * Supported GPU families |
| 868 | */ |
| 869 | #define AMDGPU_FAMILY_UNKNOWN 0 |
Christopher Ferris | 3318540 | 2017-01-13 13:28:52 -0800 | [diff] [blame] | 870 | #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 871 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ |
| 872 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ |
| 873 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ |
| 874 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ |
Christopher Ferris | 0543f74 | 2017-07-26 13:09:46 -0700 | [diff] [blame] | 875 | #define AMDGPU_FAMILY_AI 141 /* Vega10 */ |
Christopher Ferris | 2598113 | 2017-11-14 16:53:49 -0800 | [diff] [blame] | 876 | #define AMDGPU_FAMILY_RV 142 /* Raven */ |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 877 | |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 878 | #if defined(__cplusplus) |
| 879 | } |
| 880 | #endif |
| 881 | |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 882 | #endif |