Christopher Ferris | 2598113 | 2017-11-14 16:53:49 -0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
Christopher Ferris | e084501 | 2014-07-09 14:58:51 -0700 | [diff] [blame] | 2 | #ifndef __GENWQE_CARD_H__ |
| 3 | #define __GENWQE_CARD_H__ |
| 4 | |
| 5 | /** |
| 6 | * IBM Accelerator Family 'GenWQE' |
| 7 | * |
| 8 | * (C) Copyright IBM Corp. 2013 |
| 9 | * |
| 10 | * Author: Frank Haverkamp <haver@linux.vnet.ibm.com> |
| 11 | * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com> |
Christopher Ferris | 7c0b639 | 2015-01-23 15:34:26 -0800 | [diff] [blame] | 12 | * Author: Michael Jung <mijung@gmx.net> |
Christopher Ferris | e084501 | 2014-07-09 14:58:51 -0700 | [diff] [blame] | 13 | * Author: Michael Ruettger <michael@ibmra.de> |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or modify |
| 16 | * it under the terms of the GNU General Public License (version 2 only) |
| 17 | * as published by the Free Software Foundation. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | */ |
| 24 | |
| 25 | /* |
| 26 | * User-space API for the GenWQE card. For debugging and test purposes |
| 27 | * the register addresses are included here too. |
| 28 | */ |
| 29 | |
| 30 | #include <linux/types.h> |
| 31 | #include <linux/ioctl.h> |
| 32 | |
| 33 | /* Basename of sysfs, debugfs and /dev interfaces */ |
| 34 | #define GENWQE_DEVNAME "genwqe" |
| 35 | |
| 36 | #define GENWQE_TYPE_ALTERA_230 0x00 /* GenWQE4 Stratix-IV-230 */ |
| 37 | #define GENWQE_TYPE_ALTERA_530 0x01 /* GenWQE4 Stratix-IV-530 */ |
| 38 | #define GENWQE_TYPE_ALTERA_A4 0x02 /* GenWQE5 A4 Stratix-V-A4 */ |
| 39 | #define GENWQE_TYPE_ALTERA_A7 0x03 /* GenWQE5 A7 Stratix-V-A7 */ |
| 40 | |
| 41 | /* MMIO Unit offsets: Each UnitID occupies a defined address range */ |
| 42 | #define GENWQE_UID_OFFS(uid) ((uid) << 24) |
| 43 | #define GENWQE_SLU_OFFS GENWQE_UID_OFFS(0) |
| 44 | #define GENWQE_HSU_OFFS GENWQE_UID_OFFS(1) |
| 45 | #define GENWQE_APP_OFFS GENWQE_UID_OFFS(2) |
| 46 | #define GENWQE_MAX_UNITS 3 |
| 47 | |
| 48 | /* Common offsets per UnitID */ |
| 49 | #define IO_EXTENDED_ERROR_POINTER 0x00000048 |
| 50 | #define IO_ERROR_INJECT_SELECTOR 0x00000060 |
| 51 | #define IO_EXTENDED_DIAG_SELECTOR 0x00000070 |
| 52 | #define IO_EXTENDED_DIAG_READ_MBX 0x00000078 |
| 53 | #define IO_EXTENDED_DIAG_MAP(ring) (0x00000500 | ((ring) << 3)) |
| 54 | |
| 55 | #define GENWQE_EXTENDED_DIAG_SELECTOR(ring, trace) (((ring) << 8) | (trace)) |
| 56 | |
| 57 | /* UnitID 0: Service Layer Unit (SLU) */ |
| 58 | |
| 59 | /* SLU: Unit Configuration Register */ |
| 60 | #define IO_SLU_UNITCFG 0x00000000 |
| 61 | #define IO_SLU_UNITCFG_TYPE_MASK 0x000000000ff00000 /* 27:20 */ |
| 62 | |
| 63 | /* SLU: Fault Isolation Register (FIR) (ac_slu_fir) */ |
| 64 | #define IO_SLU_FIR 0x00000008 /* read only, wr direct */ |
| 65 | #define IO_SLU_FIR_CLR 0x00000010 /* read and clear */ |
| 66 | |
| 67 | /* SLU: First Error Capture Register (FEC/WOF) */ |
| 68 | #define IO_SLU_FEC 0x00000018 |
| 69 | |
| 70 | #define IO_SLU_ERR_ACT_MASK 0x00000020 |
| 71 | #define IO_SLU_ERR_ATTN_MASK 0x00000028 |
| 72 | #define IO_SLU_FIRX1_ACT_MASK 0x00000030 |
| 73 | #define IO_SLU_FIRX0_ACT_MASK 0x00000038 |
| 74 | #define IO_SLU_SEC_LEM_DEBUG_OVR 0x00000040 |
| 75 | #define IO_SLU_EXTENDED_ERR_PTR 0x00000048 |
| 76 | #define IO_SLU_COMMON_CONFIG 0x00000060 |
| 77 | |
| 78 | #define IO_SLU_FLASH_FIR 0x00000108 |
| 79 | #define IO_SLU_SLC_FIR 0x00000110 |
| 80 | #define IO_SLU_RIU_TRAP 0x00000280 |
| 81 | #define IO_SLU_FLASH_FEC 0x00000308 |
| 82 | #define IO_SLU_SLC_FEC 0x00000310 |
| 83 | |
| 84 | /* |
| 85 | * The Virtual Function's Access is from offset 0x00010000 |
| 86 | * The Physical Function's Access is from offset 0x00050000 |
| 87 | * Single Shared Registers exists only at offset 0x00060000 |
| 88 | * |
| 89 | * SLC: Queue Virtual Window Window for accessing into a specific VF |
| 90 | * queue. When accessing the 0x10000 space using the 0x50000 address |
| 91 | * segment, the value indicated here is used to specify which VF |
| 92 | * register is decoded. This register, and the 0x50000 register space |
| 93 | * can only be accessed by the PF. Example, if this register is set to |
| 94 | * 0x2, then a read from 0x50000 is the same as a read from 0x10000 |
| 95 | * from VF=2. |
| 96 | */ |
| 97 | |
| 98 | /* SLC: Queue Segment */ |
| 99 | #define IO_SLC_QUEUE_SEGMENT 0x00010000 |
| 100 | #define IO_SLC_VF_QUEUE_SEGMENT 0x00050000 |
| 101 | |
| 102 | /* SLC: Queue Offset */ |
| 103 | #define IO_SLC_QUEUE_OFFSET 0x00010008 |
| 104 | #define IO_SLC_VF_QUEUE_OFFSET 0x00050008 |
| 105 | |
| 106 | /* SLC: Queue Configuration */ |
| 107 | #define IO_SLC_QUEUE_CONFIG 0x00010010 |
| 108 | #define IO_SLC_VF_QUEUE_CONFIG 0x00050010 |
| 109 | |
| 110 | /* SLC: Job Timout/Only accessible for the PF */ |
| 111 | #define IO_SLC_APPJOB_TIMEOUT 0x00010018 |
| 112 | #define IO_SLC_VF_APPJOB_TIMEOUT 0x00050018 |
| 113 | #define TIMEOUT_250MS 0x0000000f |
| 114 | #define HEARTBEAT_DISABLE 0x0000ff00 |
| 115 | |
| 116 | /* SLC: Queue InitSequence Register */ |
| 117 | #define IO_SLC_QUEUE_INITSQN 0x00010020 |
| 118 | #define IO_SLC_VF_QUEUE_INITSQN 0x00050020 |
| 119 | |
| 120 | /* SLC: Queue Wrap */ |
| 121 | #define IO_SLC_QUEUE_WRAP 0x00010028 |
| 122 | #define IO_SLC_VF_QUEUE_WRAP 0x00050028 |
| 123 | |
| 124 | /* SLC: Queue Status */ |
| 125 | #define IO_SLC_QUEUE_STATUS 0x00010100 |
| 126 | #define IO_SLC_VF_QUEUE_STATUS 0x00050100 |
| 127 | |
| 128 | /* SLC: Queue Working Time */ |
| 129 | #define IO_SLC_QUEUE_WTIME 0x00010030 |
| 130 | #define IO_SLC_VF_QUEUE_WTIME 0x00050030 |
| 131 | |
| 132 | /* SLC: Queue Error Counts */ |
| 133 | #define IO_SLC_QUEUE_ERRCNTS 0x00010038 |
| 134 | #define IO_SLC_VF_QUEUE_ERRCNTS 0x00050038 |
| 135 | |
| 136 | /* SLC: Queue Loast Response Word */ |
| 137 | #define IO_SLC_QUEUE_LRW 0x00010040 |
| 138 | #define IO_SLC_VF_QUEUE_LRW 0x00050040 |
| 139 | |
| 140 | /* SLC: Freerunning Timer */ |
| 141 | #define IO_SLC_FREE_RUNNING_TIMER 0x00010108 |
| 142 | #define IO_SLC_VF_FREE_RUNNING_TIMER 0x00050108 |
| 143 | |
| 144 | /* SLC: Queue Virtual Access Region */ |
| 145 | #define IO_PF_SLC_VIRTUAL_REGION 0x00050000 |
| 146 | |
| 147 | /* SLC: Queue Virtual Window */ |
| 148 | #define IO_PF_SLC_VIRTUAL_WINDOW 0x00060000 |
| 149 | |
| 150 | /* SLC: DDCB Application Job Pending [n] (n=0:63) */ |
| 151 | #define IO_PF_SLC_JOBPEND(n) (0x00061000 + 8*(n)) |
| 152 | #define IO_SLC_JOBPEND(n) IO_PF_SLC_JOBPEND(n) |
| 153 | |
| 154 | /* SLC: Parser Trap RAM [n] (n=0:31) */ |
| 155 | #define IO_SLU_SLC_PARSE_TRAP(n) (0x00011000 + 8*(n)) |
| 156 | |
| 157 | /* SLC: Dispatcher Trap RAM [n] (n=0:31) */ |
| 158 | #define IO_SLU_SLC_DISP_TRAP(n) (0x00011200 + 8*(n)) |
| 159 | |
| 160 | /* Global Fault Isolation Register (GFIR) */ |
| 161 | #define IO_SLC_CFGREG_GFIR 0x00020000 |
| 162 | #define GFIR_ERR_TRIGGER 0x0000ffff |
| 163 | |
| 164 | /* SLU: Soft Reset Register */ |
| 165 | #define IO_SLC_CFGREG_SOFTRESET 0x00020018 |
| 166 | |
| 167 | /* SLU: Misc Debug Register */ |
| 168 | #define IO_SLC_MISC_DEBUG 0x00020060 |
| 169 | #define IO_SLC_MISC_DEBUG_CLR 0x00020068 |
| 170 | #define IO_SLC_MISC_DEBUG_SET 0x00020070 |
| 171 | |
| 172 | /* Temperature Sensor Reading */ |
| 173 | #define IO_SLU_TEMPERATURE_SENSOR 0x00030000 |
| 174 | #define IO_SLU_TEMPERATURE_CONFIG 0x00030008 |
| 175 | |
| 176 | /* Voltage Margining Control */ |
| 177 | #define IO_SLU_VOLTAGE_CONTROL 0x00030080 |
| 178 | #define IO_SLU_VOLTAGE_NOMINAL 0x00000000 |
| 179 | #define IO_SLU_VOLTAGE_DOWN5 0x00000006 |
| 180 | #define IO_SLU_VOLTAGE_UP5 0x00000007 |
| 181 | |
| 182 | /* Direct LED Control Register */ |
| 183 | #define IO_SLU_LEDCONTROL 0x00030100 |
| 184 | |
| 185 | /* SLU: Flashbus Direct Access -A5 */ |
| 186 | #define IO_SLU_FLASH_DIRECTACCESS 0x00040010 |
| 187 | |
| 188 | /* SLU: Flashbus Direct Access2 -A5 */ |
| 189 | #define IO_SLU_FLASH_DIRECTACCESS2 0x00040020 |
| 190 | |
| 191 | /* SLU: Flashbus Command Interface -A5 */ |
| 192 | #define IO_SLU_FLASH_CMDINTF 0x00040030 |
| 193 | |
| 194 | /* SLU: BitStream Loaded */ |
| 195 | #define IO_SLU_BITSTREAM 0x00040040 |
| 196 | |
| 197 | /* This Register has a switch which will change the CAs to UR */ |
| 198 | #define IO_HSU_ERR_BEHAVIOR 0x01001010 |
| 199 | |
| 200 | #define IO_SLC2_SQB_TRAP 0x00062000 |
| 201 | #define IO_SLC2_QUEUE_MANAGER_TRAP 0x00062008 |
| 202 | #define IO_SLC2_FLS_MASTER_TRAP 0x00062010 |
| 203 | |
| 204 | /* UnitID 1: HSU Registers */ |
| 205 | #define IO_HSU_UNITCFG 0x01000000 |
| 206 | #define IO_HSU_FIR 0x01000008 |
| 207 | #define IO_HSU_FIR_CLR 0x01000010 |
| 208 | #define IO_HSU_FEC 0x01000018 |
| 209 | #define IO_HSU_ERR_ACT_MASK 0x01000020 |
| 210 | #define IO_HSU_ERR_ATTN_MASK 0x01000028 |
| 211 | #define IO_HSU_FIRX1_ACT_MASK 0x01000030 |
| 212 | #define IO_HSU_FIRX0_ACT_MASK 0x01000038 |
| 213 | #define IO_HSU_SEC_LEM_DEBUG_OVR 0x01000040 |
| 214 | #define IO_HSU_EXTENDED_ERR_PTR 0x01000048 |
| 215 | #define IO_HSU_COMMON_CONFIG 0x01000060 |
| 216 | |
| 217 | /* UnitID 2: Application Unit (APP) */ |
| 218 | #define IO_APP_UNITCFG 0x02000000 |
| 219 | #define IO_APP_FIR 0x02000008 |
| 220 | #define IO_APP_FIR_CLR 0x02000010 |
| 221 | #define IO_APP_FEC 0x02000018 |
| 222 | #define IO_APP_ERR_ACT_MASK 0x02000020 |
| 223 | #define IO_APP_ERR_ATTN_MASK 0x02000028 |
| 224 | #define IO_APP_FIRX1_ACT_MASK 0x02000030 |
| 225 | #define IO_APP_FIRX0_ACT_MASK 0x02000038 |
| 226 | #define IO_APP_SEC_LEM_DEBUG_OVR 0x02000040 |
| 227 | #define IO_APP_EXTENDED_ERR_PTR 0x02000048 |
| 228 | #define IO_APP_COMMON_CONFIG 0x02000060 |
| 229 | |
| 230 | #define IO_APP_DEBUG_REG_01 0x02010000 |
| 231 | #define IO_APP_DEBUG_REG_02 0x02010008 |
| 232 | #define IO_APP_DEBUG_REG_03 0x02010010 |
| 233 | #define IO_APP_DEBUG_REG_04 0x02010018 |
| 234 | #define IO_APP_DEBUG_REG_05 0x02010020 |
| 235 | #define IO_APP_DEBUG_REG_06 0x02010028 |
| 236 | #define IO_APP_DEBUG_REG_07 0x02010030 |
| 237 | #define IO_APP_DEBUG_REG_08 0x02010038 |
| 238 | #define IO_APP_DEBUG_REG_09 0x02010040 |
| 239 | #define IO_APP_DEBUG_REG_10 0x02010048 |
| 240 | #define IO_APP_DEBUG_REG_11 0x02010050 |
| 241 | #define IO_APP_DEBUG_REG_12 0x02010058 |
| 242 | #define IO_APP_DEBUG_REG_13 0x02010060 |
| 243 | #define IO_APP_DEBUG_REG_14 0x02010068 |
| 244 | #define IO_APP_DEBUG_REG_15 0x02010070 |
| 245 | #define IO_APP_DEBUG_REG_16 0x02010078 |
| 246 | #define IO_APP_DEBUG_REG_17 0x02010080 |
| 247 | #define IO_APP_DEBUG_REG_18 0x02010088 |
| 248 | |
| 249 | /* Read/write from/to registers */ |
| 250 | struct genwqe_reg_io { |
| 251 | __u64 num; /* register offset/address */ |
| 252 | __u64 val64; |
| 253 | }; |
| 254 | |
| 255 | /* |
| 256 | * All registers of our card will return values not equal this values. |
| 257 | * If we see IO_ILLEGAL_VALUE on any of our MMIO register reads, the |
| 258 | * card can be considered as unusable. It will need recovery. |
| 259 | */ |
| 260 | #define IO_ILLEGAL_VALUE 0xffffffffffffffffull |
| 261 | |
| 262 | /* |
| 263 | * Generic DDCB execution interface. |
| 264 | * |
| 265 | * This interface is a first prototype resulting from discussions we |
| 266 | * had with other teams which wanted to use the Genwqe card. It allows |
| 267 | * to issue a DDCB request in a generic way. The request will block |
| 268 | * until it finishes or time out with error. |
| 269 | * |
| 270 | * Some DDCBs require DMA addresses to be specified in the ASIV |
| 271 | * block. The interface provies the capability to let the kernel |
| 272 | * driver know where those addresses are by specifying the ATS field, |
| 273 | * such that it can replace the user-space addresses with appropriate |
| 274 | * DMA addresses or DMA addresses of a scatter gather list which is |
| 275 | * dynamically created. |
| 276 | * |
| 277 | * Our hardware will refuse DDCB execution if the ATS field is not as |
| 278 | * expected. That means the DDCB execution engine in the chip knows |
| 279 | * where it expects DMA addresses within the ASIV part of the DDCB and |
| 280 | * will check that against the ATS field definition. Any invalid or |
| 281 | * unknown ATS content will lead to DDCB refusal. |
| 282 | */ |
| 283 | |
| 284 | /* Genwqe chip Units */ |
| 285 | #define DDCB_ACFUNC_SLU 0x00 /* chip service layer unit */ |
| 286 | #define DDCB_ACFUNC_APP 0x01 /* chip application */ |
| 287 | |
| 288 | /* DDCB return codes (RETC) */ |
| 289 | #define DDCB_RETC_IDLE 0x0000 /* Unexecuted/DDCB created */ |
| 290 | #define DDCB_RETC_PENDING 0x0101 /* Pending Execution */ |
| 291 | #define DDCB_RETC_COMPLETE 0x0102 /* Cmd complete. No error */ |
| 292 | #define DDCB_RETC_FAULT 0x0104 /* App Err, recoverable */ |
| 293 | #define DDCB_RETC_ERROR 0x0108 /* App Err, non-recoverable */ |
| 294 | #define DDCB_RETC_FORCED_ERROR 0x01ff /* overwritten by driver */ |
| 295 | |
| 296 | #define DDCB_RETC_UNEXEC 0x0110 /* Unexe/Removed from queue */ |
| 297 | #define DDCB_RETC_TERM 0x0120 /* Terminated */ |
| 298 | #define DDCB_RETC_RES0 0x0140 /* Reserved */ |
| 299 | #define DDCB_RETC_RES1 0x0180 /* Reserved */ |
| 300 | |
| 301 | /* DDCB Command Options (CMDOPT) */ |
| 302 | #define DDCB_OPT_ECHO_FORCE_NO 0x0000 /* ECHO DDCB */ |
| 303 | #define DDCB_OPT_ECHO_FORCE_102 0x0001 /* force return code */ |
| 304 | #define DDCB_OPT_ECHO_FORCE_104 0x0002 |
| 305 | #define DDCB_OPT_ECHO_FORCE_108 0x0003 |
| 306 | |
| 307 | #define DDCB_OPT_ECHO_FORCE_110 0x0004 /* only on PF ! */ |
| 308 | #define DDCB_OPT_ECHO_FORCE_120 0x0005 |
| 309 | #define DDCB_OPT_ECHO_FORCE_140 0x0006 |
| 310 | #define DDCB_OPT_ECHO_FORCE_180 0x0007 |
| 311 | |
| 312 | #define DDCB_OPT_ECHO_COPY_NONE (0 << 5) |
| 313 | #define DDCB_OPT_ECHO_COPY_ALL (1 << 5) |
| 314 | |
| 315 | /* Definitions of Service Layer Commands */ |
| 316 | #define SLCMD_ECHO_SYNC 0x00 /* PF/VF */ |
| 317 | #define SLCMD_MOVE_FLASH 0x06 /* PF only */ |
| 318 | #define SLCMD_MOVE_FLASH_FLAGS_MODE 0x03 /* bit 0 and 1 used for mode */ |
| 319 | #define SLCMD_MOVE_FLASH_FLAGS_DLOAD 0 /* mode: download */ |
| 320 | #define SLCMD_MOVE_FLASH_FLAGS_EMUL 1 /* mode: emulation */ |
| 321 | #define SLCMD_MOVE_FLASH_FLAGS_UPLOAD 2 /* mode: upload */ |
| 322 | #define SLCMD_MOVE_FLASH_FLAGS_VERIFY 3 /* mode: verify */ |
| 323 | #define SLCMD_MOVE_FLASH_FLAG_NOTAP (1 << 2)/* just dump DDCB and exit */ |
| 324 | #define SLCMD_MOVE_FLASH_FLAG_POLL (1 << 3)/* wait for RETC >= 0102 */ |
| 325 | #define SLCMD_MOVE_FLASH_FLAG_PARTITION (1 << 4) |
| 326 | #define SLCMD_MOVE_FLASH_FLAG_ERASE (1 << 5) |
| 327 | |
| 328 | enum genwqe_card_state { |
| 329 | GENWQE_CARD_UNUSED = 0, |
| 330 | GENWQE_CARD_USED = 1, |
| 331 | GENWQE_CARD_FATAL_ERROR = 2, |
Christopher Ferris | 7c0b639 | 2015-01-23 15:34:26 -0800 | [diff] [blame] | 332 | GENWQE_CARD_RELOAD_BITSTREAM = 3, |
Christopher Ferris | e084501 | 2014-07-09 14:58:51 -0700 | [diff] [blame] | 333 | GENWQE_CARD_STATE_MAX, |
| 334 | }; |
| 335 | |
| 336 | /* common struct for chip image exchange */ |
| 337 | struct genwqe_bitstream { |
| 338 | __u64 data_addr; /* pointer to image data */ |
| 339 | __u32 size; /* size of image file */ |
| 340 | __u32 crc; /* crc of this image */ |
| 341 | __u64 target_addr; /* starting address in Flash */ |
| 342 | __u32 partition; /* '0', '1', or 'v' */ |
| 343 | __u32 uid; /* 1=host/x=dram */ |
| 344 | |
| 345 | __u64 slu_id; /* informational/sim: SluID */ |
| 346 | __u64 app_id; /* informational/sim: AppID */ |
| 347 | |
| 348 | __u16 retc; /* returned from processing */ |
| 349 | __u16 attn; /* attention code from processing */ |
| 350 | __u32 progress; /* progress code from processing */ |
| 351 | }; |
| 352 | |
| 353 | /* Issuing a specific DDCB command */ |
| 354 | #define DDCB_LENGTH 256 /* for debug data */ |
| 355 | #define DDCB_ASIV_LENGTH 104 /* len of the DDCB ASIV array */ |
| 356 | #define DDCB_ASIV_LENGTH_ATS 96 /* ASIV in ATS architecture */ |
| 357 | #define DDCB_ASV_LENGTH 64 /* len of the DDCB ASV array */ |
| 358 | #define DDCB_FIXUPS 12 /* maximum number of fixups */ |
| 359 | |
| 360 | struct genwqe_debug_data { |
| 361 | char driver_version[64]; |
| 362 | __u64 slu_unitcfg; |
| 363 | __u64 app_unitcfg; |
| 364 | |
| 365 | __u8 ddcb_before[DDCB_LENGTH]; |
| 366 | __u8 ddcb_prev[DDCB_LENGTH]; |
| 367 | __u8 ddcb_finished[DDCB_LENGTH]; |
| 368 | }; |
| 369 | |
| 370 | /* |
| 371 | * Address Translation Specification (ATS) definitions |
| 372 | * |
| 373 | * Each 4 bit within the ATS 64-bit word specify the required address |
| 374 | * translation at the defined offset. |
| 375 | * |
| 376 | * 63 LSB |
| 377 | * 6666.5555.5555.5544.4444.4443.3333.3333 ... 11 |
| 378 | * 3210.9876.5432.1098.7654.3210.9876.5432 ... 1098.7654.3210 |
| 379 | * |
| 380 | * offset: 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 ... 0x68 0x70 0x78 |
| 381 | * res res res res ASIV ... |
| 382 | * The first 4 entries in the ATS word are reserved. The following nibbles |
| 383 | * each describe at an 8 byte offset the format of the required data. |
| 384 | */ |
| 385 | #define ATS_TYPE_DATA 0x0ull /* data */ |
| 386 | #define ATS_TYPE_FLAT_RD 0x4ull /* flat buffer read only */ |
| 387 | #define ATS_TYPE_FLAT_RDWR 0x5ull /* flat buffer read/write */ |
| 388 | #define ATS_TYPE_SGL_RD 0x6ull /* sgl read only */ |
| 389 | #define ATS_TYPE_SGL_RDWR 0x7ull /* sgl read/write */ |
| 390 | |
| 391 | #define ATS_SET_FLAGS(_struct, _field, _flags) \ |
| 392 | (((_flags) & 0xf) << (44 - (4 * (offsetof(_struct, _field) / 8)))) |
| 393 | |
| 394 | #define ATS_GET_FLAGS(_ats, _byte_offs) \ |
| 395 | (((_ats) >> (44 - (4 * ((_byte_offs) / 8)))) & 0xf) |
| 396 | |
| 397 | /** |
| 398 | * struct genwqe_ddcb_cmd - User parameter for generic DDCB commands |
| 399 | * |
| 400 | * On the way into the kernel the driver will read the whole data |
| 401 | * structure. On the way out the driver will not copy the ASIV data |
| 402 | * back to user-space. |
| 403 | */ |
| 404 | struct genwqe_ddcb_cmd { |
| 405 | /* START of data copied to/from driver */ |
| 406 | __u64 next_addr; /* chaining genwqe_ddcb_cmd */ |
| 407 | __u64 flags; /* reserved */ |
| 408 | |
| 409 | __u8 acfunc; /* accelerators functional unit */ |
| 410 | __u8 cmd; /* command to execute */ |
| 411 | __u8 asiv_length; /* used parameter length */ |
| 412 | __u8 asv_length; /* length of valid return values */ |
| 413 | __u16 cmdopts; /* command options */ |
| 414 | __u16 retc; /* return code from processing */ |
| 415 | |
| 416 | __u16 attn; /* attention code from processing */ |
| 417 | __u16 vcrc; /* variant crc16 */ |
| 418 | __u32 progress; /* progress code from processing */ |
| 419 | |
| 420 | __u64 deque_ts; /* dequeue time stamp */ |
| 421 | __u64 cmplt_ts; /* completion time stamp */ |
| 422 | __u64 disp_ts; /* SW processing start */ |
| 423 | |
| 424 | /* move to end and avoid copy-back */ |
| 425 | __u64 ddata_addr; /* collect debug data */ |
| 426 | |
| 427 | /* command specific values */ |
| 428 | __u8 asv[DDCB_ASV_LENGTH]; |
| 429 | |
| 430 | /* END of data copied from driver */ |
| 431 | union { |
| 432 | struct { |
| 433 | __u64 ats; |
| 434 | __u8 asiv[DDCB_ASIV_LENGTH_ATS]; |
| 435 | }; |
| 436 | /* used for flash update to keep it backward compatible */ |
| 437 | __u8 __asiv[DDCB_ASIV_LENGTH]; |
| 438 | }; |
| 439 | /* END of data copied to driver */ |
| 440 | }; |
| 441 | |
| 442 | #define GENWQE_IOC_CODE 0xa5 |
| 443 | |
| 444 | /* Access functions */ |
| 445 | #define GENWQE_READ_REG64 _IOR(GENWQE_IOC_CODE, 30, struct genwqe_reg_io) |
| 446 | #define GENWQE_WRITE_REG64 _IOW(GENWQE_IOC_CODE, 31, struct genwqe_reg_io) |
| 447 | #define GENWQE_READ_REG32 _IOR(GENWQE_IOC_CODE, 32, struct genwqe_reg_io) |
| 448 | #define GENWQE_WRITE_REG32 _IOW(GENWQE_IOC_CODE, 33, struct genwqe_reg_io) |
| 449 | #define GENWQE_READ_REG16 _IOR(GENWQE_IOC_CODE, 34, struct genwqe_reg_io) |
| 450 | #define GENWQE_WRITE_REG16 _IOW(GENWQE_IOC_CODE, 35, struct genwqe_reg_io) |
| 451 | |
| 452 | #define GENWQE_GET_CARD_STATE _IOR(GENWQE_IOC_CODE, 36, enum genwqe_card_state) |
| 453 | |
| 454 | /** |
| 455 | * struct genwqe_mem - Memory pinning/unpinning information |
| 456 | * @addr: virtual user space address |
| 457 | * @size: size of the area pin/dma-map/unmap |
| 458 | * direction: 0: read/1: read and write |
| 459 | * |
| 460 | * Avoid pinning and unpinning of memory pages dynamically. Instead |
| 461 | * the idea is to pin the whole buffer space required for DDCB |
| 462 | * opertionas in advance. The driver will reuse this pinning and the |
| 463 | * memory associated with it to setup the sglists for the DDCB |
| 464 | * requests without the need to allocate and free memory or map and |
| 465 | * unmap to get the DMA addresses. |
| 466 | * |
| 467 | * The inverse operation needs to be called after the pinning is not |
| 468 | * needed anymore. The pinnings else the pinnings will get removed |
| 469 | * after the device is closed. Note that pinnings will required |
| 470 | * memory. |
| 471 | */ |
| 472 | struct genwqe_mem { |
| 473 | __u64 addr; |
| 474 | __u64 size; |
| 475 | __u64 direction; |
| 476 | __u64 flags; |
| 477 | }; |
| 478 | |
| 479 | #define GENWQE_PIN_MEM _IOWR(GENWQE_IOC_CODE, 40, struct genwqe_mem) |
| 480 | #define GENWQE_UNPIN_MEM _IOWR(GENWQE_IOC_CODE, 41, struct genwqe_mem) |
| 481 | |
| 482 | /* |
| 483 | * Generic synchronous DDCB execution interface. |
| 484 | * Synchronously execute a DDCB. |
| 485 | * |
| 486 | * Return: 0 on success or negative error code. |
| 487 | * -EINVAL: Invalid parameters (ASIV_LEN, ASV_LEN, illegal fixups |
| 488 | * no mappings found/could not create mappings |
| 489 | * -EFAULT: illegal addresses in fixups, purging failed |
| 490 | * -EBADMSG: enqueing failed, retc != DDCB_RETC_COMPLETE |
| 491 | */ |
| 492 | #define GENWQE_EXECUTE_DDCB \ |
| 493 | _IOWR(GENWQE_IOC_CODE, 50, struct genwqe_ddcb_cmd) |
| 494 | |
| 495 | #define GENWQE_EXECUTE_RAW_DDCB \ |
| 496 | _IOWR(GENWQE_IOC_CODE, 51, struct genwqe_ddcb_cmd) |
| 497 | |
| 498 | /* Service Layer functions (PF only) */ |
| 499 | #define GENWQE_SLU_UPDATE _IOWR(GENWQE_IOC_CODE, 80, struct genwqe_bitstream) |
| 500 | #define GENWQE_SLU_READ _IOWR(GENWQE_IOC_CODE, 81, struct genwqe_bitstream) |
| 501 | |
| 502 | #endif /* __GENWQE_CARD_H__ */ |