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Christopher Ferris33185402017-01-13 13:28:52 -08001/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_ABI_USER_H
34#define MLX5_ABI_USER_H
35
36#include <linux/types.h>
37
38enum {
39 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
40 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
41};
42
43enum {
44 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
45};
46
47enum {
48 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
49};
50
51/* Increment this value if any changes that break userspace ABI
52 * compatibility are made.
53 */
54#define MLX5_IB_UVERBS_ABI_VERSION 1
55
56/* Make sure that all structs defined in this file remain laid out so
57 * that they pack the same way on 32-bit and 64-bit architectures (to
58 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
59 * In particular do not use pointer types -- pass pointers in __u64
60 * instead.
61 */
62
63struct mlx5_ib_alloc_ucontext_req {
64 __u32 total_num_uuars;
65 __u32 num_low_latency_uuars;
66};
67
68struct mlx5_ib_alloc_ucontext_req_v2 {
69 __u32 total_num_uuars;
70 __u32 num_low_latency_uuars;
71 __u32 flags;
72 __u32 comp_mask;
73 __u8 max_cqe_version;
74 __u8 reserved0;
75 __u16 reserved1;
76 __u32 reserved2;
77};
78
79enum mlx5_ib_alloc_ucontext_resp_mask {
80 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
81};
82
83enum mlx5_user_cmds_supp_uhw {
84 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
Christopher Ferris2fd4b3c2017-02-21 12:32:08 -080085 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
Christopher Ferris33185402017-01-13 13:28:52 -080086};
87
88struct mlx5_ib_alloc_ucontext_resp {
89 __u32 qp_tab_size;
90 __u32 bf_reg_size;
91 __u32 tot_uuars;
92 __u32 cache_line_size;
93 __u16 max_sq_desc_sz;
94 __u16 max_rq_desc_sz;
95 __u32 max_send_wqebb;
96 __u32 max_recv_wr;
97 __u32 max_srq_recv_wr;
98 __u16 num_ports;
99 __u16 reserved1;
100 __u32 comp_mask;
101 __u32 response_length;
102 __u8 cqe_version;
103 __u8 cmds_supp_uhw;
104 __u16 reserved2;
105 __u64 hca_core_clock_offset;
106};
107
108struct mlx5_ib_alloc_pd_resp {
109 __u32 pdn;
110};
111
112struct mlx5_ib_tso_caps {
113 __u32 max_tso; /* Maximum tso payload size in bytes */
114
115 /* Corresponding bit will be set if qp type from
116 * 'enum ib_qp_type' is supported, e.g.
117 * supported_qpts |= 1 << IB_QPT_UD
118 */
119 __u32 supported_qpts;
120};
121
122struct mlx5_ib_rss_caps {
123 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
124 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
125 __u8 reserved[7];
126};
127
Christopher Ferris2fd4b3c2017-02-21 12:32:08 -0800128enum mlx5_ib_cqe_comp_res_format {
129 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
130 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
131 MLX5_IB_CQE_RES_RESERVED = 1 << 2,
132};
133
134struct mlx5_ib_cqe_comp_caps {
135 __u32 max_num;
136 __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
137};
138
139struct mlx5_packet_pacing_caps {
140 __u32 qp_rate_limit_min;
141 __u32 qp_rate_limit_max; /* In kpbs */
142
143 /* Corresponding bit will be set if qp type from
144 * 'enum ib_qp_type' is supported, e.g.
145 * supported_qpts |= 1 << IB_QPT_RAW_PACKET
146 */
147 __u32 supported_qpts;
148 __u32 reserved;
149};
150
Christopher Ferris33185402017-01-13 13:28:52 -0800151struct mlx5_ib_query_device_resp {
152 __u32 comp_mask;
153 __u32 response_length;
154 struct mlx5_ib_tso_caps tso_caps;
155 struct mlx5_ib_rss_caps rss_caps;
Christopher Ferris2fd4b3c2017-02-21 12:32:08 -0800156 struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
157 struct mlx5_packet_pacing_caps packet_pacing_caps;
158 __u32 mlx5_ib_support_multi_pkt_send_wqes;
159 __u32 reserved;
Christopher Ferris33185402017-01-13 13:28:52 -0800160};
161
162struct mlx5_ib_create_cq {
163 __u64 buf_addr;
164 __u64 db_addr;
165 __u32 cqe_size;
Christopher Ferris2fd4b3c2017-02-21 12:32:08 -0800166 __u8 cqe_comp_en;
167 __u8 cqe_comp_res_format;
168 __u16 reserved; /* explicit padding (optional on i386) */
Christopher Ferris33185402017-01-13 13:28:52 -0800169};
170
171struct mlx5_ib_create_cq_resp {
172 __u32 cqn;
173 __u32 reserved;
174};
175
176struct mlx5_ib_resize_cq {
177 __u64 buf_addr;
178 __u16 cqe_size;
179 __u16 reserved0;
180 __u32 reserved1;
181};
182
183struct mlx5_ib_create_srq {
184 __u64 buf_addr;
185 __u64 db_addr;
186 __u32 flags;
187 __u32 reserved0; /* explicit padding (optional on i386) */
188 __u32 uidx;
189 __u32 reserved1;
190};
191
192struct mlx5_ib_create_srq_resp {
193 __u32 srqn;
194 __u32 reserved;
195};
196
197struct mlx5_ib_create_qp {
198 __u64 buf_addr;
199 __u64 db_addr;
200 __u32 sq_wqe_count;
201 __u32 rq_wqe_count;
202 __u32 rq_wqe_shift;
203 __u32 flags;
204 __u32 uidx;
205 __u32 reserved0;
206 __u64 sq_buf_addr;
207};
208
209/* RX Hash function flags */
210enum mlx5_rx_hash_function_flags {
211 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
212};
213
214/*
215 * RX Hash flags, these flags allows to set which incoming packet's field should
216 * participates in RX Hash. Each flag represent certain packet's field,
217 * when the flag is set the field that is represented by the flag will
218 * participate in RX Hash calculation.
219 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
220 * and *TCP and *UDP flags can't be enabled together on the same QP.
221*/
222enum mlx5_rx_hash_fields {
223 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
224 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
225 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
226 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
227 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
228 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
229 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
230 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7
231};
232
233struct mlx5_ib_create_qp_rss {
234 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
235 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
236 __u8 rx_key_len; /* valid only for Toeplitz */
237 __u8 reserved[6];
238 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
239 __u32 comp_mask;
240 __u32 reserved1;
241};
242
243struct mlx5_ib_create_qp_resp {
244 __u32 uuar_index;
245};
246
247struct mlx5_ib_alloc_mw {
248 __u32 comp_mask;
249 __u8 num_klms;
250 __u8 reserved1;
251 __u16 reserved2;
252};
253
254struct mlx5_ib_create_wq {
255 __u64 buf_addr;
256 __u64 db_addr;
257 __u32 rq_wqe_count;
258 __u32 rq_wqe_shift;
259 __u32 user_index;
260 __u32 flags;
261 __u32 comp_mask;
262 __u32 reserved;
263};
264
Christopher Ferris2fd4b3c2017-02-21 12:32:08 -0800265struct mlx5_ib_create_ah_resp {
266 __u32 response_length;
267 __u8 dmac[ETH_ALEN];
268 __u8 reserved[6];
269};
270
Christopher Ferris33185402017-01-13 13:28:52 -0800271struct mlx5_ib_create_wq_resp {
272 __u32 response_length;
273 __u32 reserved;
274};
275
276struct mlx5_ib_create_rwq_ind_tbl_resp {
277 __u32 response_length;
278 __u32 reserved;
279};
280
281struct mlx5_ib_modify_wq {
282 __u32 comp_mask;
283 __u32 reserved;
284};
285#endif /* MLX5_ABI_USER_H */