blob: 5016abc9ee9712abc1fb4e04993940b80460a2be [file] [log] [blame]
Christopher Ferris2fd4b3c2017-02-21 12:32:08 -08001/*
2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#ifndef __VMW_PVRDMA_ABI_H__
47#define __VMW_PVRDMA_ABI_H__
48
49#include <linux/types.h>
50
51#define PVRDMA_UVERBS_ABI_VERSION 3 /* ABI Version. */
52#define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF /* Bottom 24 bits. */
53#define PVRDMA_UAR_QP_OFFSET 0 /* QP doorbell. */
54#define PVRDMA_UAR_QP_SEND BIT(30) /* Send bit. */
55#define PVRDMA_UAR_QP_RECV BIT(31) /* Recv bit. */
56#define PVRDMA_UAR_CQ_OFFSET 4 /* CQ doorbell. */
57#define PVRDMA_UAR_CQ_ARM_SOL BIT(29) /* Arm solicited bit. */
58#define PVRDMA_UAR_CQ_ARM BIT(30) /* Arm bit. */
59#define PVRDMA_UAR_CQ_POLL BIT(31) /* Poll bit. */
60
61enum pvrdma_wr_opcode {
62 PVRDMA_WR_RDMA_WRITE,
63 PVRDMA_WR_RDMA_WRITE_WITH_IMM,
64 PVRDMA_WR_SEND,
65 PVRDMA_WR_SEND_WITH_IMM,
66 PVRDMA_WR_RDMA_READ,
67 PVRDMA_WR_ATOMIC_CMP_AND_SWP,
68 PVRDMA_WR_ATOMIC_FETCH_AND_ADD,
69 PVRDMA_WR_LSO,
70 PVRDMA_WR_SEND_WITH_INV,
71 PVRDMA_WR_RDMA_READ_WITH_INV,
72 PVRDMA_WR_LOCAL_INV,
73 PVRDMA_WR_FAST_REG_MR,
74 PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP,
75 PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD,
76 PVRDMA_WR_BIND_MW,
77 PVRDMA_WR_REG_SIG_MR,
78};
79
80enum pvrdma_wc_status {
81 PVRDMA_WC_SUCCESS,
82 PVRDMA_WC_LOC_LEN_ERR,
83 PVRDMA_WC_LOC_QP_OP_ERR,
84 PVRDMA_WC_LOC_EEC_OP_ERR,
85 PVRDMA_WC_LOC_PROT_ERR,
86 PVRDMA_WC_WR_FLUSH_ERR,
87 PVRDMA_WC_MW_BIND_ERR,
88 PVRDMA_WC_BAD_RESP_ERR,
89 PVRDMA_WC_LOC_ACCESS_ERR,
90 PVRDMA_WC_REM_INV_REQ_ERR,
91 PVRDMA_WC_REM_ACCESS_ERR,
92 PVRDMA_WC_REM_OP_ERR,
93 PVRDMA_WC_RETRY_EXC_ERR,
94 PVRDMA_WC_RNR_RETRY_EXC_ERR,
95 PVRDMA_WC_LOC_RDD_VIOL_ERR,
96 PVRDMA_WC_REM_INV_RD_REQ_ERR,
97 PVRDMA_WC_REM_ABORT_ERR,
98 PVRDMA_WC_INV_EECN_ERR,
99 PVRDMA_WC_INV_EEC_STATE_ERR,
100 PVRDMA_WC_FATAL_ERR,
101 PVRDMA_WC_RESP_TIMEOUT_ERR,
102 PVRDMA_WC_GENERAL_ERR,
103};
104
105enum pvrdma_wc_opcode {
106 PVRDMA_WC_SEND,
107 PVRDMA_WC_RDMA_WRITE,
108 PVRDMA_WC_RDMA_READ,
109 PVRDMA_WC_COMP_SWAP,
110 PVRDMA_WC_FETCH_ADD,
111 PVRDMA_WC_BIND_MW,
112 PVRDMA_WC_LSO,
113 PVRDMA_WC_LOCAL_INV,
114 PVRDMA_WC_FAST_REG_MR,
115 PVRDMA_WC_MASKED_COMP_SWAP,
116 PVRDMA_WC_MASKED_FETCH_ADD,
117 PVRDMA_WC_RECV = 1 << 7,
118 PVRDMA_WC_RECV_RDMA_WITH_IMM,
119};
120
121enum pvrdma_wc_flags {
122 PVRDMA_WC_GRH = 1 << 0,
123 PVRDMA_WC_WITH_IMM = 1 << 1,
124 PVRDMA_WC_WITH_INVALIDATE = 1 << 2,
125 PVRDMA_WC_IP_CSUM_OK = 1 << 3,
126 PVRDMA_WC_WITH_SMAC = 1 << 4,
127 PVRDMA_WC_WITH_VLAN = 1 << 5,
128 PVRDMA_WC_FLAGS_MAX = PVRDMA_WC_WITH_VLAN,
129};
130
131struct pvrdma_alloc_ucontext_resp {
132 __u32 qp_tab_size;
133 __u32 reserved;
134};
135
136struct pvrdma_alloc_pd_resp {
137 __u32 pdn;
138 __u32 reserved;
139};
140
141struct pvrdma_create_cq {
142 __u64 buf_addr;
143 __u32 buf_size;
144 __u32 reserved;
145};
146
147struct pvrdma_create_cq_resp {
148 __u32 cqn;
149 __u32 reserved;
150};
151
152struct pvrdma_resize_cq {
153 __u64 buf_addr;
154 __u32 buf_size;
155 __u32 reserved;
156};
157
158struct pvrdma_create_srq {
159 __u64 buf_addr;
160};
161
162struct pvrdma_create_srq_resp {
163 __u32 srqn;
164 __u32 reserved;
165};
166
167struct pvrdma_create_qp {
168 __u64 rbuf_addr;
169 __u64 sbuf_addr;
170 __u32 rbuf_size;
171 __u32 sbuf_size;
172 __u64 qp_addr;
173};
174
175/* PVRDMA masked atomic compare and swap */
176struct pvrdma_ex_cmp_swap {
177 __u64 swap_val;
178 __u64 compare_val;
179 __u64 swap_mask;
180 __u64 compare_mask;
181};
182
183/* PVRDMA masked atomic fetch and add */
184struct pvrdma_ex_fetch_add {
185 __u64 add_val;
186 __u64 field_boundary;
187};
188
189/* PVRDMA address vector. */
190struct pvrdma_av {
191 __u32 port_pd;
192 __u32 sl_tclass_flowlabel;
193 __u8 dgid[16];
194 __u8 src_path_bits;
195 __u8 gid_index;
196 __u8 stat_rate;
197 __u8 hop_limit;
198 __u8 dmac[6];
199 __u8 reserved[6];
200};
201
202/* PVRDMA scatter/gather entry */
203struct pvrdma_sge {
204 __u64 addr;
205 __u32 length;
206 __u32 lkey;
207};
208
209/* PVRDMA receive queue work request */
210struct pvrdma_rq_wqe_hdr {
211 __u64 wr_id; /* wr id */
212 __u32 num_sge; /* size of s/g array */
213 __u32 total_len; /* reserved */
214};
215/* Use pvrdma_sge (ib_sge) for receive queue s/g array elements. */
216
217/* PVRDMA send queue work request */
218struct pvrdma_sq_wqe_hdr {
219 __u64 wr_id; /* wr id */
220 __u32 num_sge; /* size of s/g array */
221 __u32 total_len; /* reserved */
222 __u32 opcode; /* operation type */
223 __u32 send_flags; /* wr flags */
224 union {
225 __u32 imm_data;
226 __u32 invalidate_rkey;
227 } ex;
228 __u32 reserved;
229 union {
230 struct {
231 __u64 remote_addr;
232 __u32 rkey;
233 __u8 reserved[4];
234 } rdma;
235 struct {
236 __u64 remote_addr;
237 __u64 compare_add;
238 __u64 swap;
239 __u32 rkey;
240 __u32 reserved;
241 } atomic;
242 struct {
243 __u64 remote_addr;
244 __u32 log_arg_sz;
245 __u32 rkey;
246 union {
247 struct pvrdma_ex_cmp_swap cmp_swap;
248 struct pvrdma_ex_fetch_add fetch_add;
249 } wr_data;
250 } masked_atomics;
251 struct {
252 __u64 iova_start;
253 __u64 pl_pdir_dma;
254 __u32 page_shift;
255 __u32 page_list_len;
256 __u32 length;
257 __u32 access_flags;
258 __u32 rkey;
259 } fast_reg;
260 struct {
261 __u32 remote_qpn;
262 __u32 remote_qkey;
263 struct pvrdma_av av;
264 } ud;
265 } wr;
266};
267/* Use pvrdma_sge (ib_sge) for send queue s/g array elements. */
268
269/* Completion queue element. */
270struct pvrdma_cqe {
271 __u64 wr_id;
272 __u64 qp;
273 __u32 opcode;
274 __u32 status;
275 __u32 byte_len;
276 __u32 imm_data;
277 __u32 src_qp;
278 __u32 wc_flags;
279 __u32 vendor_err;
280 __u16 pkey_index;
281 __u16 slid;
282 __u8 sl;
283 __u8 dlid_path_bits;
284 __u8 port_num;
285 __u8 smac[6];
286 __u8 reserved2[7]; /* Pad to next power of 2 (64). */
287};
288
289#endif /* __VMW_PVRDMA_ABI_H__ */