blob: 9abbeb924cbb74a7e0bfba97d178831e92590d4f [file] [log] [blame]
Ben Cheng224b54f2013-10-15 18:26:18 -07001/**
2 * \file drm.h
3 * Header for the Direct Rendering Manager
4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 *
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
9 */
10
11/*
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
15 *
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
22 *
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
25 * Software.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
34 */
35
36#ifndef _DRM_H_
37#define _DRM_H_
38
39#if defined(__KERNEL__) || defined(__linux__)
40
41#include <linux/types.h>
42#include <asm/ioctl.h>
43typedef unsigned int drm_handle_t;
44
45#else /* One of the BSDs */
46
47#include <sys/ioccom.h>
48#include <sys/types.h>
49typedef int8_t __s8;
50typedef uint8_t __u8;
51typedef int16_t __s16;
52typedef uint16_t __u16;
53typedef int32_t __s32;
54typedef uint32_t __u32;
55typedef int64_t __s64;
56typedef uint64_t __u64;
57typedef unsigned long drm_handle_t;
58
59#endif
60
61#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
62#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
63#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
64#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
65
66#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
67#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
68#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
69#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
70#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
71
72typedef unsigned int drm_context_t;
73typedef unsigned int drm_drawable_t;
74typedef unsigned int drm_magic_t;
75
76/**
77 * Cliprect.
78 *
79 * \warning: If you change this structure, make sure you change
80 * XF86DRIClipRectRec in the server as well
81 *
82 * \note KW: Actually it's illegal to change either for
83 * backwards-compatibility reasons.
84 */
85struct drm_clip_rect {
86 unsigned short x1;
87 unsigned short y1;
88 unsigned short x2;
89 unsigned short y2;
90};
91
92/**
93 * Drawable information.
94 */
95struct drm_drawable_info {
96 unsigned int num_rects;
97 struct drm_clip_rect *rects;
98};
99
100/**
101 * Texture region,
102 */
103struct drm_tex_region {
104 unsigned char next;
105 unsigned char prev;
106 unsigned char in_use;
107 unsigned char padding;
108 unsigned int age;
109};
110
111/**
112 * Hardware lock.
113 *
114 * The lock structure is a simple cache-line aligned integer. To avoid
115 * processor bus contention on a multiprocessor system, there should not be any
116 * other data stored in the same cache line.
117 */
118struct drm_hw_lock {
119 __volatile__ unsigned int lock; /**< lock variable */
120 char padding[60]; /**< Pad to cache line */
121};
122
123/**
124 * DRM_IOCTL_VERSION ioctl argument type.
125 *
126 * \sa drmGetVersion().
127 */
128struct drm_version {
129 int version_major; /**< Major version */
130 int version_minor; /**< Minor version */
131 int version_patchlevel; /**< Patch level */
132 size_t name_len; /**< Length of name buffer */
133 char __user *name; /**< Name of driver */
134 size_t date_len; /**< Length of date buffer */
135 char __user *date; /**< User-space buffer to hold date */
136 size_t desc_len; /**< Length of desc buffer */
137 char __user *desc; /**< User-space buffer to hold desc */
138};
139
140/**
141 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
142 *
143 * \sa drmGetBusid() and drmSetBusId().
144 */
145struct drm_unique {
146 size_t unique_len; /**< Length of unique */
147 char __user *unique; /**< Unique name for driver instantiation */
148};
149
150struct drm_list {
151 int count; /**< Length of user-space structures */
152 struct drm_version __user *version;
153};
154
155struct drm_block {
156 int unused;
157};
158
159/**
160 * DRM_IOCTL_CONTROL ioctl argument type.
161 *
162 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
163 */
164struct drm_control {
165 enum {
166 DRM_ADD_COMMAND,
167 DRM_RM_COMMAND,
168 DRM_INST_HANDLER,
169 DRM_UNINST_HANDLER
170 } func;
171 int irq;
172};
173
174/**
175 * Type of memory to map.
176 */
177enum drm_map_type {
178 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
179 _DRM_REGISTERS = 1, /**< no caching, no core dump */
180 _DRM_SHM = 2, /**< shared, cached */
181 _DRM_AGP = 3, /**< AGP/GART */
182 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
183 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
Ben Cheng224b54f2013-10-15 18:26:18 -0700184};
185
186/**
187 * Memory mapping flags.
188 */
189enum drm_map_flags {
190 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
191 _DRM_READ_ONLY = 0x02,
192 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
193 _DRM_KERNEL = 0x08, /**< kernel requires access */
194 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
195 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
196 _DRM_REMOVABLE = 0x40, /**< Removable mapping */
197 _DRM_DRIVER = 0x80 /**< Managed by driver */
198};
199
200struct drm_ctx_priv_map {
201 unsigned int ctx_id; /**< Context requesting private mapping */
202 void *handle; /**< Handle of map */
203};
204
205/**
206 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
207 * argument type.
208 *
209 * \sa drmAddMap().
210 */
211struct drm_map {
212 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
213 unsigned long size; /**< Requested physical size (bytes) */
214 enum drm_map_type type; /**< Type of memory to map */
215 enum drm_map_flags flags; /**< Flags */
216 void *handle; /**< User-space: "Handle" to pass to mmap() */
217 /**< Kernel-space: kernel-virtual address */
218 int mtrr; /**< MTRR slot used */
219 /* Private data */
220};
221
222/**
223 * DRM_IOCTL_GET_CLIENT ioctl argument type.
224 */
225struct drm_client {
226 int idx; /**< Which client desired? */
227 int auth; /**< Is client authenticated? */
228 unsigned long pid; /**< Process ID */
229 unsigned long uid; /**< User ID */
230 unsigned long magic; /**< Magic */
231 unsigned long iocs; /**< Ioctl count */
232};
233
234enum drm_stat_type {
235 _DRM_STAT_LOCK,
236 _DRM_STAT_OPENS,
237 _DRM_STAT_CLOSES,
238 _DRM_STAT_IOCTLS,
239 _DRM_STAT_LOCKS,
240 _DRM_STAT_UNLOCKS,
241 _DRM_STAT_VALUE, /**< Generic value */
242 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
243 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
244
245 _DRM_STAT_IRQ, /**< IRQ */
246 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
247 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
248 _DRM_STAT_DMA, /**< DMA */
249 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
250 _DRM_STAT_MISSED /**< Missed DMA opportunity */
251 /* Add to the *END* of the list */
252};
253
254/**
255 * DRM_IOCTL_GET_STATS ioctl argument type.
256 */
257struct drm_stats {
258 unsigned long count;
259 struct {
260 unsigned long value;
261 enum drm_stat_type type;
262 } data[15];
263};
264
265/**
266 * Hardware locking flags.
267 */
268enum drm_lock_flags {
269 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
270 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
271 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
272 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
273 /* These *HALT* flags aren't supported yet
274 -- they will be used to support the
275 full-screen DGA-like mode. */
276 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
277 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
278};
279
280/**
281 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
282 *
283 * \sa drmGetLock() and drmUnlock().
284 */
285struct drm_lock {
286 int context;
287 enum drm_lock_flags flags;
288};
289
290/**
291 * DMA flags
292 *
293 * \warning
294 * These values \e must match xf86drm.h.
295 *
296 * \sa drm_dma.
297 */
298enum drm_dma_flags {
299 /* Flags for DMA buffer dispatch */
300 _DRM_DMA_BLOCK = 0x01, /**<
301 * Block until buffer dispatched.
302 *
303 * \note The buffer may not yet have
304 * been processed by the hardware --
305 * getting a hardware lock with the
306 * hardware quiescent will ensure
307 * that the buffer has been
308 * processed.
309 */
310 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
311 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
312
313 /* Flags for DMA buffer request */
314 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
315 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
316 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
317};
318
319/**
320 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
321 *
322 * \sa drmAddBufs().
323 */
324struct drm_buf_desc {
325 int count; /**< Number of buffers of this size */
326 int size; /**< Size in bytes */
327 int low_mark; /**< Low water mark */
328 int high_mark; /**< High water mark */
329 enum {
330 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
331 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
332 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
333 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
334 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
335 } flags;
336 unsigned long agp_start; /**<
337 * Start address of where the AGP buffers are
338 * in the AGP aperture
339 */
340};
341
342/**
343 * DRM_IOCTL_INFO_BUFS ioctl argument type.
344 */
345struct drm_buf_info {
346 int count; /**< Entries in list */
347 struct drm_buf_desc __user *list;
348};
349
350/**
351 * DRM_IOCTL_FREE_BUFS ioctl argument type.
352 */
353struct drm_buf_free {
354 int count;
355 int __user *list;
356};
357
358/**
359 * Buffer information
360 *
361 * \sa drm_buf_map.
362 */
363struct drm_buf_pub {
364 int idx; /**< Index into the master buffer list */
365 int total; /**< Buffer size */
366 int used; /**< Amount of buffer in use (for DMA) */
367 void __user *address; /**< Address of buffer */
368};
369
370/**
371 * DRM_IOCTL_MAP_BUFS ioctl argument type.
372 */
373struct drm_buf_map {
374 int count; /**< Length of the buffer list */
375 void __user *virtual; /**< Mmap'd area in user-virtual */
376 struct drm_buf_pub __user *list; /**< Buffer information */
377};
378
379/**
380 * DRM_IOCTL_DMA ioctl argument type.
381 *
382 * Indices here refer to the offset into the buffer list in drm_buf_get.
383 *
384 * \sa drmDMA().
385 */
386struct drm_dma {
387 int context; /**< Context handle */
388 int send_count; /**< Number of buffers to send */
389 int __user *send_indices; /**< List of handles to buffers */
390 int __user *send_sizes; /**< Lengths of data to send */
391 enum drm_dma_flags flags; /**< Flags */
392 int request_count; /**< Number of buffers requested */
393 int request_size; /**< Desired size for buffers */
394 int __user *request_indices; /**< Buffer information */
395 int __user *request_sizes;
396 int granted_count; /**< Number of buffers granted */
397};
398
399enum drm_ctx_flags {
400 _DRM_CONTEXT_PRESERVED = 0x01,
401 _DRM_CONTEXT_2DONLY = 0x02
402};
403
404/**
405 * DRM_IOCTL_ADD_CTX ioctl argument type.
406 *
407 * \sa drmCreateContext() and drmDestroyContext().
408 */
409struct drm_ctx {
410 drm_context_t handle;
411 enum drm_ctx_flags flags;
412};
413
414/**
415 * DRM_IOCTL_RES_CTX ioctl argument type.
416 */
417struct drm_ctx_res {
418 int count;
419 struct drm_ctx __user *contexts;
420};
421
422/**
423 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
424 */
425struct drm_draw {
426 drm_drawable_t handle;
427};
428
429/**
430 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
431 */
432typedef enum {
433 DRM_DRAWABLE_CLIPRECTS,
434} drm_drawable_info_type_t;
435
436struct drm_update_draw {
437 drm_drawable_t handle;
438 unsigned int type;
439 unsigned int num;
440 unsigned long long data;
441};
442
443/**
444 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
445 */
446struct drm_auth {
447 drm_magic_t magic;
448};
449
450/**
451 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
452 *
453 * \sa drmGetInterruptFromBusID().
454 */
455struct drm_irq_busid {
456 int irq; /**< IRQ number */
457 int busnum; /**< bus number */
458 int devnum; /**< device number */
459 int funcnum; /**< function number */
460};
461
462enum drm_vblank_seq_type {
463 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
464 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
465 /* bits 1-6 are reserved for high crtcs */
466 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
467 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
468 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
469 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
470 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
471 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
472};
473#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
474
475#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
476#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
477 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
478
479struct drm_wait_vblank_request {
480 enum drm_vblank_seq_type type;
481 unsigned int sequence;
482 unsigned long signal;
483};
484
485struct drm_wait_vblank_reply {
486 enum drm_vblank_seq_type type;
487 unsigned int sequence;
488 long tval_sec;
489 long tval_usec;
490};
491
492/**
493 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
494 *
495 * \sa drmWaitVBlank().
496 */
497union drm_wait_vblank {
498 struct drm_wait_vblank_request request;
499 struct drm_wait_vblank_reply reply;
500};
501
502#define _DRM_PRE_MODESET 1
503#define _DRM_POST_MODESET 2
504
505/**
506 * DRM_IOCTL_MODESET_CTL ioctl argument type
507 *
508 * \sa drmModesetCtl().
509 */
510struct drm_modeset_ctl {
511 __u32 crtc;
512 __u32 cmd;
513};
514
515/**
516 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
517 *
518 * \sa drmAgpEnable().
519 */
520struct drm_agp_mode {
521 unsigned long mode; /**< AGP mode */
522};
523
524/**
525 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
526 *
527 * \sa drmAgpAlloc() and drmAgpFree().
528 */
529struct drm_agp_buffer {
530 unsigned long size; /**< In bytes -- will round to page boundary */
531 unsigned long handle; /**< Used for binding / unbinding */
532 unsigned long type; /**< Type of memory to allocate */
533 unsigned long physical; /**< Physical used by i810 */
534};
535
536/**
537 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
538 *
539 * \sa drmAgpBind() and drmAgpUnbind().
540 */
541struct drm_agp_binding {
542 unsigned long handle; /**< From drm_agp_buffer */
543 unsigned long offset; /**< In bytes -- will round to page boundary */
544};
545
546/**
547 * DRM_IOCTL_AGP_INFO ioctl argument type.
548 *
549 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
550 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
551 * drmAgpVendorId() and drmAgpDeviceId().
552 */
553struct drm_agp_info {
554 int agp_version_major;
555 int agp_version_minor;
556 unsigned long mode;
557 unsigned long aperture_base; /* physical address */
558 unsigned long aperture_size; /* bytes */
559 unsigned long memory_allowed; /* bytes */
560 unsigned long memory_used;
561
562 /* PCI information */
563 unsigned short id_vendor;
564 unsigned short id_device;
565};
566
567/**
568 * DRM_IOCTL_SG_ALLOC ioctl argument type.
569 */
570struct drm_scatter_gather {
571 unsigned long size; /**< In bytes -- will round to page boundary */
572 unsigned long handle; /**< Used for mapping / unmapping */
573};
574
575/**
576 * DRM_IOCTL_SET_VERSION ioctl argument type.
577 */
578struct drm_set_version {
579 int drm_di_major;
580 int drm_di_minor;
581 int drm_dd_major;
582 int drm_dd_minor;
583};
584
585/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
586struct drm_gem_close {
587 /** Handle of the object to be closed. */
588 __u32 handle;
589 __u32 pad;
590};
591
592/** DRM_IOCTL_GEM_FLINK ioctl argument type */
593struct drm_gem_flink {
594 /** Handle for the object being named */
595 __u32 handle;
596
597 /** Returned global name */
598 __u32 name;
599};
600
601/** DRM_IOCTL_GEM_OPEN ioctl argument type */
602struct drm_gem_open {
603 /** Name of object being opened */
604 __u32 name;
605
606 /** Returned handle for the object */
607 __u32 handle;
608
609 /** Returned size of the object */
610 __u64 size;
611};
612
Christopher Ferrise0845012014-07-09 14:58:51 -0700613#define DRM_CAP_DUMB_BUFFER 0x1
614#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
615#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
616#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
617#define DRM_CAP_PRIME 0x5
618#define DRM_PRIME_CAP_IMPORT 0x1
619#define DRM_PRIME_CAP_EXPORT 0x2
620#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
621#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
Christopher Ferris31475242014-09-02 17:43:51 -0700622/*
623 * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight
624 * combination for the hardware cursor. The intention is that a hardware
625 * agnostic userspace can query a cursor plane size to use.
626 *
627 * Note that the cross-driver contract is to merely return a valid size;
628 * drivers are free to attach another meaning on top, eg. i915 returns the
629 * maximum plane size.
630 */
Christopher Ferrise0845012014-07-09 14:58:51 -0700631#define DRM_CAP_CURSOR_WIDTH 0x8
632#define DRM_CAP_CURSOR_HEIGHT 0x9
633
Ben Cheng224b54f2013-10-15 18:26:18 -0700634/** DRM_IOCTL_GET_CAP ioctl argument type */
635struct drm_get_cap {
636 __u64 capability;
637 __u64 value;
638};
639
Christopher Ferrise0845012014-07-09 14:58:51 -0700640/**
641 * DRM_CLIENT_CAP_STEREO_3D
642 *
643 * if set to 1, the DRM core will expose the stereo 3D capabilities of the
644 * monitor by advertising the supported 3D layouts in the flags of struct
645 * drm_mode_modeinfo.
646 */
647#define DRM_CLIENT_CAP_STEREO_3D 1
648
Christopher Ferris31475242014-09-02 17:43:51 -0700649/**
650 * DRM_CLIENT_CAP_UNIVERSAL_PLANES
651 *
652 * If set to 1, the DRM core will expose all planes (overlay, primary, and
653 * cursor) to userspace.
654 */
655#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
656
Christopher Ferrise0845012014-07-09 14:58:51 -0700657/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
658struct drm_set_client_cap {
659 __u64 capability;
660 __u64 value;
661};
662
Ben Cheng224b54f2013-10-15 18:26:18 -0700663#define DRM_CLOEXEC O_CLOEXEC
664struct drm_prime_handle {
665 __u32 handle;
666
667 /** Flags.. only applicable for handle->fd */
668 __u32 flags;
669
670 /** Returned dmabuf file descriptor */
671 __s32 fd;
672};
673
674#include <drm/drm_mode.h>
675
676#define DRM_IOCTL_BASE 'd'
677#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
678#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
679#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
680#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
681
682#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
683#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
684#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
685#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
686#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
687#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
688#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
689#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
690#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
691#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
692#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
693#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
694#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
Christopher Ferrise0845012014-07-09 14:58:51 -0700695#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap)
Ben Cheng224b54f2013-10-15 18:26:18 -0700696
697#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
698#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
699#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
700#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
701#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
702#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
703#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
704#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
705#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
706#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
707#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
708
709#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
710
711#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
712#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
713
714#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
715#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
716
717#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
718#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
719#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
720#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
721#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
722#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
723#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
724#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
725#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
726#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
727#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
728#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
729#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
730
731#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
732#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
733
734#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
735#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
736#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
737#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
738#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
739#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
740#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
741#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
742
743#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
744#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
745
746#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
747
748#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
749
750#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
751#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
752#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
753#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
754#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
755#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
756#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
757#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
758#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */
759#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */
760
761#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
762#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
763#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
764#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
765#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
766#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
767#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
768#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
769
770#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
771#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
772#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
773#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
774#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
775#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
776#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
777#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
778#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
Christopher Ferrise0845012014-07-09 14:58:51 -0700779#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
Ben Cheng224b54f2013-10-15 18:26:18 -0700780
781/**
782 * Device specific ioctls should only be in their respective headers
783 * The device specific ioctl range is from 0x40 to 0x99.
784 * Generic IOCTLS restart at 0xA0.
785 *
786 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
787 * drmCommandReadWrite().
788 */
789#define DRM_COMMAND_BASE 0x40
790#define DRM_COMMAND_END 0xA0
791
792/**
793 * Header for events written back to userspace on the drm fd. The
794 * type defines the type of event, the length specifies the total
795 * length of the event (including the header), and user_data is
796 * typically a 64 bit value passed with the ioctl that triggered the
797 * event. A read on the drm fd will always only return complete
798 * events, that is, if for example the read buffer is 100 bytes, and
799 * there are two 64 byte events pending, only one will be returned.
800 *
801 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
802 * up are chipset specific.
803 */
804struct drm_event {
805 __u32 type;
806 __u32 length;
807};
808
809#define DRM_EVENT_VBLANK 0x01
810#define DRM_EVENT_FLIP_COMPLETE 0x02
811
812struct drm_event_vblank {
813 struct drm_event base;
814 __u64 user_data;
815 __u32 tv_sec;
816 __u32 tv_usec;
817 __u32 sequence;
818 __u32 reserved;
819};
820
Ben Cheng224b54f2013-10-15 18:26:18 -0700821/* typedef area */
822#ifndef __KERNEL__
823typedef struct drm_clip_rect drm_clip_rect_t;
824typedef struct drm_drawable_info drm_drawable_info_t;
825typedef struct drm_tex_region drm_tex_region_t;
826typedef struct drm_hw_lock drm_hw_lock_t;
827typedef struct drm_version drm_version_t;
828typedef struct drm_unique drm_unique_t;
829typedef struct drm_list drm_list_t;
830typedef struct drm_block drm_block_t;
831typedef struct drm_control drm_control_t;
832typedef enum drm_map_type drm_map_type_t;
833typedef enum drm_map_flags drm_map_flags_t;
834typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
835typedef struct drm_map drm_map_t;
836typedef struct drm_client drm_client_t;
837typedef enum drm_stat_type drm_stat_type_t;
838typedef struct drm_stats drm_stats_t;
839typedef enum drm_lock_flags drm_lock_flags_t;
840typedef struct drm_lock drm_lock_t;
841typedef enum drm_dma_flags drm_dma_flags_t;
842typedef struct drm_buf_desc drm_buf_desc_t;
843typedef struct drm_buf_info drm_buf_info_t;
844typedef struct drm_buf_free drm_buf_free_t;
845typedef struct drm_buf_pub drm_buf_pub_t;
846typedef struct drm_buf_map drm_buf_map_t;
847typedef struct drm_dma drm_dma_t;
848typedef union drm_wait_vblank drm_wait_vblank_t;
849typedef struct drm_agp_mode drm_agp_mode_t;
850typedef enum drm_ctx_flags drm_ctx_flags_t;
851typedef struct drm_ctx drm_ctx_t;
852typedef struct drm_ctx_res drm_ctx_res_t;
853typedef struct drm_draw drm_draw_t;
854typedef struct drm_update_draw drm_update_draw_t;
855typedef struct drm_auth drm_auth_t;
856typedef struct drm_irq_busid drm_irq_busid_t;
857typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
858
859typedef struct drm_agp_buffer drm_agp_buffer_t;
860typedef struct drm_agp_binding drm_agp_binding_t;
861typedef struct drm_agp_info drm_agp_info_t;
862typedef struct drm_scatter_gather drm_scatter_gather_t;
863typedef struct drm_set_version drm_set_version_t;
864#endif
865
866#endif