Christopher Ferris | 2598113 | 2017-11-14 16:53:49 -0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
Ben Cheng | 224b54f | 2013-10-15 18:26:18 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Based on arch/arm/include/asm/ptrace.h |
| 4 | * |
| 5 | * Copyright (C) 1996-2003 Russell King |
| 6 | * Copyright (C) 2012 ARM Ltd. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | #ifndef _UAPI__ASM_PTRACE_H |
| 21 | #define _UAPI__ASM_PTRACE_H |
| 22 | |
| 23 | #include <linux/types.h> |
| 24 | |
| 25 | #include <asm/hwcap.h> |
Christopher Ferris | a1a109e | 2018-01-31 15:03:12 -0800 | [diff] [blame] | 26 | #include <asm/sigcontext.h> |
Ben Cheng | 224b54f | 2013-10-15 18:26:18 -0700 | [diff] [blame] | 27 | |
| 28 | |
| 29 | /* |
| 30 | * PSR bits |
| 31 | */ |
| 32 | #define PSR_MODE_EL0t 0x00000000 |
| 33 | #define PSR_MODE_EL1t 0x00000004 |
| 34 | #define PSR_MODE_EL1h 0x00000005 |
| 35 | #define PSR_MODE_EL2t 0x00000008 |
| 36 | #define PSR_MODE_EL2h 0x00000009 |
| 37 | #define PSR_MODE_EL3t 0x0000000c |
| 38 | #define PSR_MODE_EL3h 0x0000000d |
| 39 | #define PSR_MODE_MASK 0x0000000f |
| 40 | |
| 41 | /* AArch32 CPSR bits */ |
| 42 | #define PSR_MODE32_BIT 0x00000010 |
| 43 | |
| 44 | /* AArch64 SPSR bits */ |
| 45 | #define PSR_F_BIT 0x00000040 |
| 46 | #define PSR_I_BIT 0x00000080 |
| 47 | #define PSR_A_BIT 0x00000100 |
| 48 | #define PSR_D_BIT 0x00000200 |
Christopher Ferris | 12e1f28 | 2016-02-04 12:35:07 -0800 | [diff] [blame] | 49 | #define PSR_PAN_BIT 0x00400000 |
Christopher Ferris | ccfaccd | 2016-08-24 12:11:31 -0700 | [diff] [blame] | 50 | #define PSR_UAO_BIT 0x00800000 |
Ben Cheng | 224b54f | 2013-10-15 18:26:18 -0700 | [diff] [blame] | 51 | #define PSR_V_BIT 0x10000000 |
| 52 | #define PSR_C_BIT 0x20000000 |
| 53 | #define PSR_Z_BIT 0x40000000 |
| 54 | #define PSR_N_BIT 0x80000000 |
| 55 | |
| 56 | /* |
| 57 | * Groups of PSR bits |
| 58 | */ |
| 59 | #define PSR_f 0xff000000 /* Flags */ |
| 60 | #define PSR_s 0x00ff0000 /* Status */ |
| 61 | #define PSR_x 0x0000ff00 /* Extension */ |
| 62 | #define PSR_c 0x000000ff /* Control */ |
| 63 | |
| 64 | |
| 65 | #ifndef __ASSEMBLY__ |
| 66 | |
Christopher Ferris | a1a109e | 2018-01-31 15:03:12 -0800 | [diff] [blame] | 67 | #include <linux/prctl.h> |
| 68 | |
Ben Cheng | 224b54f | 2013-10-15 18:26:18 -0700 | [diff] [blame] | 69 | /* |
| 70 | * User structures for general purpose, floating point and debug registers. |
| 71 | */ |
| 72 | struct user_pt_regs { |
| 73 | __u64 regs[31]; |
| 74 | __u64 sp; |
| 75 | __u64 pc; |
| 76 | __u64 pstate; |
| 77 | }; |
| 78 | |
| 79 | struct user_fpsimd_state { |
| 80 | __uint128_t vregs[32]; |
| 81 | __u32 fpsr; |
| 82 | __u32 fpcr; |
Christopher Ferris | a7e96cb | 2017-01-27 10:50:23 -0800 | [diff] [blame] | 83 | __u32 __reserved[2]; |
Ben Cheng | 224b54f | 2013-10-15 18:26:18 -0700 | [diff] [blame] | 84 | }; |
| 85 | |
| 86 | struct user_hwdebug_state { |
| 87 | __u32 dbg_info; |
| 88 | __u32 pad; |
| 89 | struct { |
| 90 | __u64 addr; |
| 91 | __u32 ctrl; |
| 92 | __u32 pad; |
| 93 | } dbg_regs[16]; |
| 94 | }; |
| 95 | |
Christopher Ferris | a1a109e | 2018-01-31 15:03:12 -0800 | [diff] [blame] | 96 | /* SVE/FP/SIMD state (NT_ARM_SVE) */ |
| 97 | |
| 98 | struct user_sve_header { |
| 99 | __u32 size; /* total meaningful regset content in bytes */ |
| 100 | __u32 max_size; /* maxmium possible size for this thread */ |
| 101 | __u16 vl; /* current vector length */ |
| 102 | __u16 max_vl; /* maximum possible vector length */ |
| 103 | __u16 flags; |
| 104 | __u16 __reserved; |
| 105 | }; |
| 106 | |
| 107 | /* Definitions for user_sve_header.flags: */ |
| 108 | #define SVE_PT_REGS_MASK (1 << 0) |
| 109 | |
| 110 | #define SVE_PT_REGS_FPSIMD 0 |
| 111 | #define SVE_PT_REGS_SVE SVE_PT_REGS_MASK |
| 112 | |
| 113 | /* |
| 114 | * Common SVE_PT_* flags: |
| 115 | * These must be kept in sync with prctl interface in <linux/ptrace.h> |
| 116 | */ |
| 117 | #define SVE_PT_VL_INHERIT (PR_SVE_VL_INHERIT >> 16) |
| 118 | #define SVE_PT_VL_ONEXEC (PR_SVE_SET_VL_ONEXEC >> 16) |
| 119 | |
| 120 | |
| 121 | /* |
| 122 | * The remainder of the SVE state follows struct user_sve_header. The |
| 123 | * total size of the SVE state (including header) depends on the |
| 124 | * metadata in the header: SVE_PT_SIZE(vq, flags) gives the total size |
| 125 | * of the state in bytes, including the header. |
| 126 | * |
| 127 | * Refer to <asm/sigcontext.h> for details of how to pass the correct |
| 128 | * "vq" argument to these macros. |
| 129 | */ |
| 130 | |
| 131 | /* Offset from the start of struct user_sve_header to the register data */ |
| 132 | #define SVE_PT_REGS_OFFSET \ |
| 133 | ((sizeof(struct sve_context) + (SVE_VQ_BYTES - 1)) \ |
| 134 | / SVE_VQ_BYTES * SVE_VQ_BYTES) |
| 135 | |
| 136 | /* |
| 137 | * The register data content and layout depends on the value of the |
| 138 | * flags field. |
| 139 | */ |
| 140 | |
| 141 | /* |
| 142 | * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD case: |
| 143 | * |
| 144 | * The payload starts at offset SVE_PT_FPSIMD_OFFSET, and is of type |
| 145 | * struct user_fpsimd_state. Additional data might be appended in the |
| 146 | * future: use SVE_PT_FPSIMD_SIZE(vq, flags) to compute the total size. |
| 147 | * SVE_PT_FPSIMD_SIZE(vq, flags) will never be less than |
| 148 | * sizeof(struct user_fpsimd_state). |
| 149 | */ |
| 150 | |
| 151 | #define SVE_PT_FPSIMD_OFFSET SVE_PT_REGS_OFFSET |
| 152 | |
| 153 | #define SVE_PT_FPSIMD_SIZE(vq, flags) (sizeof(struct user_fpsimd_state)) |
| 154 | |
| 155 | /* |
| 156 | * (flags & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE case: |
| 157 | * |
| 158 | * The payload starts at offset SVE_PT_SVE_OFFSET, and is of size |
| 159 | * SVE_PT_SVE_SIZE(vq, flags). |
| 160 | * |
| 161 | * Additional macros describe the contents and layout of the payload. |
| 162 | * For each, SVE_PT_SVE_x_OFFSET(args) is the start offset relative to |
| 163 | * the start of struct user_sve_header, and SVE_PT_SVE_x_SIZE(args) is |
| 164 | * the size in bytes: |
| 165 | * |
| 166 | * x type description |
| 167 | * - ---- ----------- |
| 168 | * ZREGS \ |
| 169 | * ZREG | |
| 170 | * PREGS | refer to <asm/sigcontext.h> |
| 171 | * PREG | |
| 172 | * FFR / |
| 173 | * |
| 174 | * FPSR uint32_t FPSR |
| 175 | * FPCR uint32_t FPCR |
| 176 | * |
| 177 | * Additional data might be appended in the future. |
| 178 | */ |
| 179 | |
| 180 | #define SVE_PT_SVE_ZREG_SIZE(vq) SVE_SIG_ZREG_SIZE(vq) |
| 181 | #define SVE_PT_SVE_PREG_SIZE(vq) SVE_SIG_PREG_SIZE(vq) |
| 182 | #define SVE_PT_SVE_FFR_SIZE(vq) SVE_SIG_FFR_SIZE(vq) |
| 183 | #define SVE_PT_SVE_FPSR_SIZE sizeof(__u32) |
| 184 | #define SVE_PT_SVE_FPCR_SIZE sizeof(__u32) |
| 185 | |
| 186 | #define __SVE_SIG_TO_PT(offset) \ |
| 187 | ((offset) - SVE_SIG_REGS_OFFSET + SVE_PT_REGS_OFFSET) |
| 188 | |
| 189 | #define SVE_PT_SVE_OFFSET SVE_PT_REGS_OFFSET |
| 190 | |
| 191 | #define SVE_PT_SVE_ZREGS_OFFSET \ |
| 192 | __SVE_SIG_TO_PT(SVE_SIG_ZREGS_OFFSET) |
| 193 | #define SVE_PT_SVE_ZREG_OFFSET(vq, n) \ |
| 194 | __SVE_SIG_TO_PT(SVE_SIG_ZREG_OFFSET(vq, n)) |
| 195 | #define SVE_PT_SVE_ZREGS_SIZE(vq) \ |
| 196 | (SVE_PT_SVE_ZREG_OFFSET(vq, SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET) |
| 197 | |
| 198 | #define SVE_PT_SVE_PREGS_OFFSET(vq) \ |
| 199 | __SVE_SIG_TO_PT(SVE_SIG_PREGS_OFFSET(vq)) |
| 200 | #define SVE_PT_SVE_PREG_OFFSET(vq, n) \ |
| 201 | __SVE_SIG_TO_PT(SVE_SIG_PREG_OFFSET(vq, n)) |
| 202 | #define SVE_PT_SVE_PREGS_SIZE(vq) \ |
| 203 | (SVE_PT_SVE_PREG_OFFSET(vq, SVE_NUM_PREGS) - \ |
| 204 | SVE_PT_SVE_PREGS_OFFSET(vq)) |
| 205 | |
| 206 | #define SVE_PT_SVE_FFR_OFFSET(vq) \ |
| 207 | __SVE_SIG_TO_PT(SVE_SIG_FFR_OFFSET(vq)) |
| 208 | |
| 209 | #define SVE_PT_SVE_FPSR_OFFSET(vq) \ |
| 210 | ((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) + \ |
| 211 | (SVE_VQ_BYTES - 1)) \ |
| 212 | / SVE_VQ_BYTES * SVE_VQ_BYTES) |
| 213 | #define SVE_PT_SVE_FPCR_OFFSET(vq) \ |
| 214 | (SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE) |
| 215 | |
| 216 | /* |
| 217 | * Any future extension appended after FPCR must be aligned to the next |
| 218 | * 128-bit boundary. |
| 219 | */ |
| 220 | |
| 221 | #define SVE_PT_SVE_SIZE(vq, flags) \ |
| 222 | ((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE \ |
| 223 | - SVE_PT_SVE_OFFSET + (SVE_VQ_BYTES - 1)) \ |
| 224 | / SVE_VQ_BYTES * SVE_VQ_BYTES) |
| 225 | |
| 226 | #define SVE_PT_SIZE(vq, flags) \ |
| 227 | (((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ? \ |
| 228 | SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) \ |
| 229 | : SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags)) |
| 230 | |
Ben Cheng | 224b54f | 2013-10-15 18:26:18 -0700 | [diff] [blame] | 231 | #endif /* __ASSEMBLY__ */ |
| 232 | |
| 233 | #endif /* _UAPI__ASM_PTRACE_H */ |