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gerrit-public.fairphone.software / platform / external / libavc / 134291ea0b1b9794b4d7feee2c3ffdbd941c5237 / . / encoder / ih264e_api.c
blob: 41b1fddab74882cf98180e6a74617650d3815359 [file] [log] [blame]
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1/******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19*/
20
21/**
22*******************************************************************************
23* @file
24* ih264e_api.c
25*
26* @brief
27* Contains api function definitions for H264 encoder
28*
29* @author
30* ittiam
31*
32* @par List of Functions:
33* - api_check_struct_sanity()
34* - ih264e_codec_update_config()
35* - ih264e_set_default_params()
36* - ih264e_init()
37* - ih264e_get_num_rec()
38* - ih264e_fill_num_mem_rec()
39* - ih264e_init_mem_rec()
40* - ih264e_retrieve_memrec()
41* - ih264e_set_flush_mode()
42* - ih264e_get_buf_info()
43* - ih264e_set_dimensions()
44* - ih264e_set_frame_rate()
45* - ih264e_set_bit_rate()
46* - ih264e_set_frame_type()
47* - ih264e_set_qp()
48* - ih264e_set_enc_mode()
49* - ih264e_set_vbv_params()
50* - ih264_set_air_params()
51* - ih264_set_me_params()
52* - ih264_set_ipe_params()
53* - ih264_set_gop_params()
54* - ih264_set_profile_params()
55* - ih264_set_deblock_params()
56* - ih264e_set_num_cores()
57* - ih264e_reset()
58* - ih264e_ctl()
59* - ih264e_api_function()
60*
61* @remarks
62* None
63*
64*******************************************************************************
65*/
66
67/*****************************************************************************/
68/* File Includes */
69/*****************************************************************************/
70
71/* System Include Files */
72#include <stdio.h>
73#include <stddef.h>
74#include <stdlib.h>
75#include <string.h>
76#include <assert.h>
77
78/* User Include Files */
79#include "ih264e_config.h"
80#include "ih264_typedefs.h"
81#include "ih264_size_defs.h"
82#include "iv2.h"
83#include "ive2.h"
84#include "ih264e.h"
85#include "ithread.h"
86#include "ih264_debug.h"
87#include "ih264_defs.h"
88#include "ih264_error.h"
89#include "ih264_structs.h"
90#include "ih264_trans_quant_itrans_iquant.h"
91#include "ih264_inter_pred_filters.h"
92#include "ih264_mem_fns.h"
93#include "ih264_padding.h"
94#include "ih264_intra_pred_filters.h"
95#include "ih264_deblk_edge_filters.h"
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]96#include "ih264_cabac_tables.h"
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]97#include "ih264_macros.h"
98#include "ih264e_defs.h"
99#include "ih264e_globals.h"
100#include "ih264_buf_mgr.h"
101#include "irc_mem_req_and_acq.h"
102#include "irc_cntrl_param.h"
103#include "irc_frame_info_collector.h"
104#include "irc_rate_control_api.h"
105#include "ih264e_time_stamp.h"
106#include "ih264e_modify_frm_rate.h"
107#include "ih264e_rate_control.h"
108#include "ih264e_error.h"
109#include "ih264e_bitstream.h"
110#include "ime_defs.h"
111#include "ime_distortion_metrics.h"
112#include "ime_structs.h"
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]113#include "ih264e_cabac_structs.h"
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]114#include "ih264e_structs.h"
115#include "ih264e_utils.h"
116#include "ih264e_core_coding.h"
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]117#include "ih264_platform_macros.h"
118#include "ih264e_platform_macros.h"
119#include "ih264_list.h"
120#include "ih264_dpb_mgr.h"
121#include "ih264_cavlc_tables.h"
122#include "ih264e_cavlc.h"
123#include "ih264_common_tables.h"
124#include "ih264e_master.h"
125#include "ih264e_fmt_conv.h"
126#include "ih264e_version.h"
127
128
129/*****************************************************************************/
130/* Function Declarations */
131/*****************************************************************************/
132WORD32 ih264e_get_rate_control_mem_tab(void *pv_rate_control,
133 iv_mem_rec_t *ps_mem,
134 ITT_FUNC_TYPE_E e_func_type);
135
136
137/*****************************************************************************/
138/* Function Definitions */
139/*****************************************************************************/
140
141/**
142*******************************************************************************
143*
144* @brief
145* Used to test arguments for corresponding API call
146*
147* @par Description:
148* For each command the arguments are validated
149*
150* @param[in] ps_handle
151* Codec handle at API level
152*
153* @param[in] pv_api_ip
154* Pointer to input structure
155*
156* @param[out] pv_api_op
157* Pointer to output structure
158*
159* @returns error status
160*
161* @remarks none
162*
163*******************************************************************************
164*/
165static IV_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
166 void *pv_api_ip,
167 void *pv_api_op)
168{
169 /* api call */
170 WORD32 command = IV_CMD_NA;
171
172 /* input structure expected by the api call */
173 UWORD32 *pu4_api_ip = pv_api_ip;
174
175 /* output structure expected by the api call */
176 UWORD32 *pu4_api_op = pv_api_op;
177
178 /* temp var */
179 WORD32 i, j;
180
181 if (NULL == pv_api_op || NULL == pv_api_ip)
182 {
183 return (IV_FAIL);
184 }
185
186 /* get command */
187 command = pu4_api_ip[1];
188
189 /* set error code */
190 pu4_api_op[1] = 0;
191
192 /* error checks on handle */
193 switch (command)
194 {
195 case IV_CMD_GET_NUM_MEM_REC:
196 case IV_CMD_FILL_NUM_MEM_REC:
197 break;
198
199 case IV_CMD_INIT:
200 if (ps_handle == NULL)
201 {
202 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
203 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
204 return IV_FAIL;
205 }
206
207 if (ps_handle->u4_size != sizeof(iv_obj_t))
208 {
209 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
210 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
211 return IV_FAIL;
212 }
213 break;
214
215 case IVE_CMD_QUEUE_INPUT:
216 case IVE_CMD_QUEUE_OUTPUT:
217 case IVE_CMD_DEQUEUE_OUTPUT:
218 case IVE_CMD_GET_RECON:
219 case IV_CMD_RETRIEVE_MEMREC:
220 case IVE_CMD_VIDEO_CTL:
221 case IVE_CMD_VIDEO_ENCODE:
222
223 if (ps_handle == NULL)
224 {
225 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
226 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL;
227 return IV_FAIL;
228 }
229
230 if (ps_handle->u4_size != sizeof(iv_obj_t))
231 {
232 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
233 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT;
234 return IV_FAIL;
235 }
236
237 if (ps_handle->pv_fxns != ih264e_api_function)
238 {
239 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
240 *(pu4_api_op + 1) |= IVE_ERR_API_FUNCTION_PTR_NULL;
241 return IV_FAIL;
242 }
243
244 if (ps_handle->pv_codec_handle == NULL)
245 {
246 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
247 *(pu4_api_op + 1) |= IVE_ERR_INVALID_CODEC_HANDLE;
248 return IV_FAIL;
249 }
250 break;
251
252 default:
253 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
254 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
255 return IV_FAIL;
256 }
257
258 /* error checks on input output structures */
259 switch (command)
260 {
261 case IV_CMD_GET_NUM_MEM_REC:
262 {
263 ih264e_num_mem_rec_ip_t *ps_ip = pv_api_ip;
264 ih264e_num_mem_rec_op_t *ps_op = pv_api_op;
265
266 ps_op->s_ive_op.u4_error_code = 0;
267
268 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_num_mem_rec_ip_t))
269 {
270 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
271 ps_op->s_ive_op.u4_error_code |=
272 IVE_ERR_IP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
273 return (IV_FAIL);
274 }
275
276 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_num_mem_rec_op_t))
277 {
278 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
279 ps_op->s_ive_op.u4_error_code |=
280 IVE_ERR_OP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT;
281 return (IV_FAIL);
282 }
283 break;
284 }
285
286 case IV_CMD_FILL_NUM_MEM_REC:
287 {
288 ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
289 ih264e_fill_mem_rec_op_t *ps_op = pv_api_op;
290
291 iv_mem_rec_t *ps_mem_rec = NULL;
292
293 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
294 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
295
296 ps_op->s_ive_op.u4_error_code = 0;
297
298 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_fill_mem_rec_ip_t))
299 {
300 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
301 ps_op->s_ive_op.u4_error_code |=
302 IVE_ERR_IP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
303 return (IV_FAIL);
304 }
305
306 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_fill_mem_rec_op_t))
307 {
308 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
309 ps_op->s_ive_op.u4_error_code |=
310 IVE_ERR_OP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT;
311 return (IV_FAIL);
312 }
313
314 if (max_wd < MIN_WD || max_wd > MAX_WD)
315 {
316 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
317 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
318 return (IV_FAIL);
319 }
320
321 if (max_ht < MIN_HT || max_ht > MAX_HT)
322 {
323 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
324 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
325 return (IV_FAIL);
326 }
327
328 /* verify number of mem rec ptr */
329 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
330 {
331 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
332 ps_op->s_ive_op.u4_error_code |=
333 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
334 return (IV_FAIL);
335 }
336
337 /* verify number of mem records */
338 if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT)
339 {
340 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
341 ps_op->s_ive_op.u4_error_code |=
342 IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
343 return IV_FAIL;
344 }
345
346 /* check mem records sizes are correct */
347 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
348 for (i = 0; i < MEM_REC_CNT; i++)
349 {
350 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
351 {
352 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
353 ps_op->s_ive_op.u4_error_code |=
354 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
355 return IV_FAIL;
356 }
357 }
358 break;
359 }
360
361 case IV_CMD_INIT:
362 {
363 ih264e_init_ip_t *ps_ip = pv_api_ip;
364 ih264e_init_op_t *ps_op = pv_api_op;
365
366 iv_mem_rec_t *ps_mem_rec = NULL;
367
368 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
369 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
370
371 ps_op->s_ive_op.u4_error_code = 0;
372
373 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_init_ip_t))
374 {
375 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
376 ps_op->s_ive_op.u4_error_code |=
377 IVE_ERR_IP_INIT_API_STRUCT_SIZE_INCORRECT;
378 return (IV_FAIL);
379 }
380
381 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_init_op_t))
382 {
383 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
384 ps_op->s_ive_op.u4_error_code |=
385 IVE_ERR_OP_INIT_API_STRUCT_SIZE_INCORRECT;
386 return (IV_FAIL);
387 }
388
389 if (max_wd < MIN_WD || max_wd > MAX_WD)
390 {
391 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
392 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED;
393 return (IV_FAIL);
394 }
395
396 if (max_ht < MIN_HT || max_ht > MAX_HT)
397 {
398 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
399 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED;
400 return (IV_FAIL);
401 }
402
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]403 if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_PIC_CNT ||
404 ps_ip->s_ive_ip.u4_max_ref_cnt < MIN_REF_PIC_CNT)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]405 {
406 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
407 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
408 return (IV_FAIL);
409 }
410
411 if (ps_ip->s_ive_ip.u4_max_reorder_cnt != 0)
412 {
413 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
414 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
415 return (IV_FAIL);
416 }
417
418 if ((ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_10)
419 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_1B)
420 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_11)
421 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_12)
422 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_13)
423 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_20)
424 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_21)
425 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_22)
426 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_30)
427 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_31)
428 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_32)
429 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_40)
430 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_41)
431 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_42)
432 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_50)
433 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_51))
434 {
435 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
436 ps_op->s_ive_op.u4_error_code |=
437 IH264E_CODEC_LEVEL_NOT_SUPPORTED;
438 return (IV_FAIL);
439 }
440
441 if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P)
442 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE)
443 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV)
444 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU))
445 {
446 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
447 ps_op->s_ive_op.u4_error_code |=
448 IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
449 return (IV_FAIL);
450 }
451
452 if ((ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420P)
453 && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_UV)
454 && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_VU))
455 {
456 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
457 ps_op->s_ive_op.u4_error_code |=
458 IH264E_RECON_CHROMA_FORMAT_NOT_SUPPORTED;
459 return (IV_FAIL);
460 }
461
462 if ((ps_ip->s_ive_ip.e_rc_mode != IVE_RC_NONE)
463 && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_STORAGE)
464 && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_CBR_NON_LOW_DELAY))
465 {
466 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
467 ps_op->s_ive_op.u4_error_code |=
468 IH264E_RATE_CONTROL_MODE_NOT_SUPPORTED;
469 return (IV_FAIL);
470 }
471
472 if (ps_ip->s_ive_ip.u4_max_framerate > DEFAULT_MAX_FRAMERATE)
473 {
474 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
475 ps_op->s_ive_op.u4_error_code |=
476 IH264E_FRAME_RATE_NOT_SUPPORTED;
477 return (IV_FAIL);
478 }
479
480 if (ps_ip->s_ive_ip.u4_max_bitrate > DEFAULT_MAX_BITRATE)
481 {
482 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
483 ps_op->s_ive_op.u4_error_code |= IH264E_BITRATE_NOT_SUPPORTED;
484 return (IV_FAIL);
485 }
486
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]487 if (ps_ip->s_ive_ip.u4_num_bframes > MAX_NUM_BFRAMES)
488 {
489 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
490 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
491 return (IV_FAIL);
492 }
493
494 if (ps_ip->s_ive_ip.u4_num_bframes
495 && (ps_ip->s_ive_ip.u4_max_ref_cnt < 2))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]496 {
497 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
498 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED;
499 return (IV_FAIL);
500 }
501
502 if (ps_ip->s_ive_ip.e_content_type != IV_PROGRESSIVE)
503 {
504 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
505 ps_op->s_ive_op.u4_error_code |=
506 IH264E_CONTENT_TYPE_NOT_SUPPORTED;
507 return (IV_FAIL);
508 }
509
510 if (ps_ip->s_ive_ip.u4_max_srch_rng_x > DEFAULT_MAX_SRCH_RANGE_X)
511 {
512 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
513 ps_op->s_ive_op.u4_error_code |=
514 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
515 return (IV_FAIL);
516 }
517
518 if (ps_ip->s_ive_ip.u4_max_srch_rng_y > DEFAULT_MAX_SRCH_RANGE_Y)
519 {
520 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
521 ps_op->s_ive_op.u4_error_code |=
522 IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
523 return (IV_FAIL);
524 }
525
526 if ((ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_NONE)
527 && (ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_BLOCKS))
528 {
529 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
530 ps_op->s_ive_op.u4_error_code |=
531 IH264E_SLICE_TYPE_INPUT_INVALID;
532 return (IV_FAIL);
533 }
534
535 if (ps_ip->s_ive_ip.e_slice_mode == IVE_SLICE_MODE_BLOCKS)
536 {
537 if (ps_ip->s_ive_ip.u4_slice_param == 0
538 || ps_ip->s_ive_ip.u4_slice_param > ((UWORD32)max_ht >> 4))
539 {
540 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
541 ps_op->s_ive_op.u4_error_code |=
542 IH264E_SLICE_PARAM_INPUT_INVALID;
543 return (IV_FAIL);
544 }
545 }
546
547 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
548 {
549 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
550 ps_op->s_ive_op.u4_error_code |=
551 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
552 return (IV_FAIL);
553 }
554
555 /* verify number of mem records */
556 if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT)
557 {
558 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
559 ps_op->s_ive_op.u4_error_code |=
560 IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT;
561 return (IV_FAIL);
562 }
563
564 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
565
566 /* check memrecords sizes are correct */
567 for (i = 0; i <((WORD32)ps_ip->s_ive_ip.u4_num_mem_rec); i++)
568 {
569 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
570 {
571 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
572 ps_op->s_ive_op.u4_error_code |=
573 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
574 return IV_FAIL;
575 }
576
577 /* check memrecords pointers are not NULL */
578 if (ps_mem_rec[i].pv_base == NULL)
579 {
580 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
581 ps_op->s_ive_op.u4_error_code |=
582 IVE_ERR_MEM_REC_BASE_POINTER_NULL;
583 return IV_FAIL;
584 }
585 }
586
587 /* verify memtabs for overlapping regions */
588 {
589 void *start[MEM_REC_CNT];
590 void *end[MEM_REC_CNT];
591
592 start[0] = (ps_mem_rec[0].pv_base);
593 end[0] = ((UWORD8 *) ps_mem_rec[0].pv_base)
594 + ps_mem_rec[0].u4_mem_size - 1;
595
596 for (i = 1; i < MEM_REC_CNT; i++)
597 {
598 /* This array is populated to check memtab overlap */
599 start[i] = (ps_mem_rec[i].pv_base);
600 end[i] = ((UWORD8 *) ps_mem_rec[i].pv_base)
601 + ps_mem_rec[i].u4_mem_size - 1;
602
603 for (j = 0; j < i; j++)
604 {
605 if ((start[i] >= start[j]) && (start[i] <= end[j]))
606 {
607 ps_op->s_ive_op.u4_error_code |= 1
608 << IVE_UNSUPPORTEDPARAM;
609 ps_op->s_ive_op.u4_error_code |=
610 IVE_ERR_MEM_REC_OVERLAP_ERR;
611 return IV_FAIL;
612 }
613
614 if ((end[i] >= start[j]) && (end[i] <= end[j]))
615 {
616 ps_op->s_ive_op.u4_error_code |= 1
617 << IVE_UNSUPPORTEDPARAM;
618 ps_op->s_ive_op.u4_error_code |=
619 IVE_ERR_MEM_REC_OVERLAP_ERR;
620 return IV_FAIL;
621 }
622
623 if ((start[i] < start[j]) && (end[i] > end[j]))
624 {
625 ps_op->s_ive_op.u4_error_code |= 1
626 << IVE_UNSUPPORTEDPARAM;
627 ps_op->s_ive_op.u4_error_code |=
628 IVE_ERR_MEM_REC_OVERLAP_ERR;
629 return IV_FAIL;
630 }
631 }
632 }
633 }
634
635 /* re-validate mem records with init config */
636 {
637 /* mem records */
638 iv_mem_rec_t s_mem_rec_ittiam_api[MEM_REC_CNT];
639
640 /* api interface structs */
641 ih264e_fill_mem_rec_ip_t s_ip;
642 ih264e_fill_mem_rec_op_t s_op;
643
644 /* error status */
645 IV_STATUS_T e_status;
646
647 /* temp var */
648 WORD32 i;
649
650 s_ip.s_ive_ip.u4_size = sizeof(ih264e_fill_mem_rec_ip_t);
651 s_op.s_ive_op.u4_size = sizeof(ih264e_fill_mem_rec_op_t);
652
653 s_ip.s_ive_ip.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
654 s_ip.s_ive_ip.ps_mem_rec = s_mem_rec_ittiam_api;
655 s_ip.s_ive_ip.u4_max_wd = max_wd;
656 s_ip.s_ive_ip.u4_max_ht = max_ht;
657 s_ip.s_ive_ip.u4_num_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
658 s_ip.s_ive_ip.u4_max_level = ps_ip->s_ive_ip.u4_max_level;
659 s_ip.s_ive_ip.u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
660 s_ip.s_ive_ip.u4_max_reorder_cnt =
661 ps_ip->s_ive_ip.u4_max_reorder_cnt;
662 s_ip.s_ive_ip.e_color_format = ps_ip->s_ive_ip.e_inp_color_fmt;
663 s_ip.s_ive_ip.u4_max_srch_rng_x =
664 ps_ip->s_ive_ip.u4_max_srch_rng_x;
665 s_ip.s_ive_ip.u4_max_srch_rng_y =
666 ps_ip->s_ive_ip.u4_max_srch_rng_y;
667
668 for (i = 0; i < MEM_REC_CNT; i++)
669 {
670 s_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
671 }
672
673 /* fill mem records */
674 e_status = ih264e_api_function(NULL, (void *) &s_ip,
675 (void *) &s_op);
676
677 if (IV_FAIL == e_status)
678 {
679 ps_op->s_ive_op.u4_error_code = s_op.s_ive_op.u4_error_code;
680 return (IV_FAIL);
681 }
682
683 /* verify mem records */
684 for (i = 0; i < MEM_REC_CNT; i++)
685 {
686 if (ps_mem_rec[i].u4_mem_size
687 < s_mem_rec_ittiam_api[i].u4_mem_size)
688 {
689 ps_op->s_ive_op.u4_error_code |= 1
690 << IVE_UNSUPPORTEDPARAM;
691 ps_op->s_ive_op.u4_error_code |=
692 IVE_ERR_MEM_REC_INSUFFICIENT_SIZE;
693
694 return IV_FAIL;
695 }
696
697 if (ps_mem_rec[i].u4_mem_alignment
698 != s_mem_rec_ittiam_api[i].u4_mem_alignment)
699 {
700 ps_op->s_ive_op.u4_error_code |= 1
701 << IVE_UNSUPPORTEDPARAM;
702 ps_op->s_ive_op.u4_error_code |=
703 IVE_ERR_MEM_REC_ALIGNMENT_ERR;
704
705 return IV_FAIL;
706 }
707
708 if (ps_mem_rec[i].e_mem_type
709 != s_mem_rec_ittiam_api[i].e_mem_type)
710 {
711 UWORD32 check = IV_SUCCESS;
712 UWORD32 diff = s_mem_rec_ittiam_api[i].e_mem_type
713 - ps_mem_rec[i].e_mem_type;
714
715 if ((ps_mem_rec[i].e_mem_type
716 <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM)
717 && (s_mem_rec_ittiam_api[i].e_mem_type
718 >= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM))
719 {
720 check = IV_FAIL;
721 }
722
723 if (3 != (s_mem_rec_ittiam_api[i].e_mem_type % 4))
724 {
725 /* It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or
726 * IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM */
727
728 if ((diff < 1) || (diff > 3))
729 {
730 /* Difference between 1 and 3 is okay for all cases other than the
731 * two filtered with the MOD condition above */
732 check = IV_FAIL;
733 }
734 }
735 else
736 {
737 if (diff == 1)
738 {
739 /* This particular case is when codec asked for External Persistent,
740 * but got Internal Scratch */
741 check = IV_FAIL;
742 }
743 if ((diff != 2) && (diff != 3))
744 {
745 check = IV_FAIL;
746 }
747 }
748
749 if (check == IV_FAIL)
750 {
751 ps_op->s_ive_op.u4_error_code |= 1
752 << IVE_UNSUPPORTEDPARAM;
753 ps_op->s_ive_op.u4_error_code |=
754 IVE_ERR_MEM_REC_INCORRECT_TYPE;
755
756 return IV_FAIL;
757 }
758 }
759 }
760 }
761 break;
762 }
763
764 case IVE_CMD_QUEUE_INPUT:
765 case IVE_CMD_QUEUE_OUTPUT:
766 case IVE_CMD_DEQUEUE_OUTPUT:
767 case IVE_CMD_GET_RECON:
768 break;
769
770 case IV_CMD_RETRIEVE_MEMREC:
771 {
772 ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
773 ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op;
774
775 iv_mem_rec_t *ps_mem_rec = NULL;
776
777 ps_op->s_ive_op.u4_error_code = 0;
778
779 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_retrieve_mem_rec_ip_t))
780 {
781 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
782 ps_op->s_ive_op.u4_error_code |=
783 IVE_ERR_IP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
784 return (IV_FAIL);
785 }
786
787 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_retrieve_mem_rec_op_t))
788 {
789 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
790 ps_op->s_ive_op.u4_error_code |=
791 IVE_ERR_OP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT;
792 return (IV_FAIL);
793 }
794
795 if (NULL == ps_ip->s_ive_ip.ps_mem_rec)
796 {
797 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
798 ps_op->s_ive_op.u4_error_code |=
799 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL;
800 return (IV_FAIL);
801 }
802
803 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec;
804
805 /* check memrecords sizes are correct */
806 for (i = 0; i < MEM_REC_CNT; i++)
807 {
808 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
809 {
810 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
811 ps_op->s_ive_op.u4_error_code |=
812 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT;
813 return IV_FAIL;
814 }
815 }
816 break;
817 }
818
819 case IVE_CMD_VIDEO_ENCODE:
820 {
821 ih264e_video_encode_ip_t *ps_ip = pv_api_ip;
822 ih264e_video_encode_op_t *ps_op = pv_api_op;
823
824 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_video_encode_ip_t))
825 {
826 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
827 ps_op->s_ive_op.u4_error_code |=
828 IVE_ERR_IP_ENCODE_API_STRUCT_SIZE_INCORRECT;
829 return (IV_FAIL);
830 }
831
832 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_video_encode_op_t))
833 {
834 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM;
835 ps_op->s_ive_op.u4_error_code |=
836 IVE_ERR_OP_ENCODE_API_STRUCT_SIZE_INCORRECT;
837 return (IV_FAIL);
838 }
839 break;
840 }
841
842 case IVE_CMD_VIDEO_CTL:
843 {
844 /* ptr to input structure */
845 WORD32 *pu4_ptr_cmd = pv_api_ip;
846
847 /* sub command */
848 WORD32 sub_command = pu4_ptr_cmd[2];
849
850 switch (sub_command)
851 {
852 case IVE_CMD_CTL_SETDEFAULT:
853 {
854 ih264e_ctl_setdefault_ip_t *ps_ip = pv_api_ip;
855 ih264e_ctl_setdefault_op_t *ps_op = pv_api_op;
856
857 if (ps_ip->s_ive_ip.u4_size
858 != sizeof(ih264e_ctl_setdefault_ip_t))
859 {
860 ps_op->s_ive_op.u4_error_code |= 1
861 << IVE_UNSUPPORTEDPARAM;
862 ps_op->s_ive_op.u4_error_code |=
863 IVE_ERR_IP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
864 return IV_FAIL;
865 }
866
867 if (ps_op->s_ive_op.u4_size
868 != sizeof(ih264e_ctl_setdefault_op_t))
869 {
870 ps_op->s_ive_op.u4_error_code |= 1
871 << IVE_UNSUPPORTEDPARAM;
872 ps_op->s_ive_op.u4_error_code |=
873 IVE_ERR_OP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT;
874 return IV_FAIL;
875 }
876 break;
877 }
878
879 case IVE_CMD_CTL_GETBUFINFO:
880 {
881 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
882
883 ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
884 ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op;
885
886 if (ps_ip->s_ive_ip.u4_size
887 != sizeof(ih264e_ctl_getbufinfo_ip_t))
888 {
889 ps_op->s_ive_op.u4_error_code |= 1
890 << IVE_UNSUPPORTEDPARAM;
891 ps_op->s_ive_op.u4_error_code |=
892 IVE_ERR_IP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
893 return IV_FAIL;
894 }
895
896 if (ps_op->s_ive_op.u4_size
897 != sizeof(ih264e_ctl_getbufinfo_op_t))
898 {
899 ps_op->s_ive_op.u4_error_code |= 1
900 << IVE_UNSUPPORTEDPARAM;
901 ps_op->s_ive_op.u4_error_code |=
902 IVE_ERR_OP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT;
903 return IV_FAIL;
904 }
905
906 if (ps_ip->s_ive_ip.u4_max_wd < MIN_WD)
907 {
908 ps_op->s_ive_op.u4_error_code |= 1
909 << IVE_UNSUPPORTEDPARAM;
910 ps_op->s_ive_op.u4_error_code |=
911 IH264E_WIDTH_NOT_SUPPORTED;
912 return (IV_FAIL);
913 }
914
915 if (ps_ip->s_ive_ip.u4_max_wd > ps_codec->s_cfg.u4_max_wd)
916 {
917 ps_op->s_ive_op.u4_error_code |= 1
918 << IVE_UNSUPPORTEDPARAM;
919 ps_op->s_ive_op.u4_error_code |=
920 IH264E_WIDTH_NOT_SUPPORTED;
921 return (IV_FAIL);
922 }
923
924 if (ps_ip->s_ive_ip.u4_max_ht < MIN_HT)
925 {
926 ps_op->s_ive_op.u4_error_code |= 1
927 << IVE_UNSUPPORTEDPARAM;
928 ps_op->s_ive_op.u4_error_code |=
929 IH264E_HEIGHT_NOT_SUPPORTED;
930 return (IV_FAIL);
931 }
932
933 if (ps_ip->s_ive_ip.u4_max_ht > ps_codec->s_cfg.u4_max_ht)
934 {
935 ps_op->s_ive_op.u4_error_code |= 1
936 << IVE_UNSUPPORTEDPARAM;
937 ps_op->s_ive_op.u4_error_code |=
938 IH264E_HEIGHT_NOT_SUPPORTED;
939 return (IV_FAIL);
940 }
941
942 if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P)
943 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE)
944 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV)
945 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU))
946 {
947 ps_op->s_ive_op.u4_error_code |= 1
948 << IVE_UNSUPPORTEDPARAM;
949 ps_op->s_ive_op.u4_error_code |=
950 IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED;
951 return (IV_FAIL);
952 }
953 break;
954 }
955
956 case IVE_CMD_CTL_GETVERSION:
957 {
958 ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
959 ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op;
960
961 if (ps_ip->s_ive_ip.u4_size
962 != sizeof(ih264e_ctl_getversioninfo_ip_t))
963 {
964 ps_op->s_ive_op.u4_error_code |= 1
965 << IVE_UNSUPPORTEDPARAM;
966 ps_op->s_ive_op.u4_error_code |=
967 IVE_ERR_IP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
968 return IV_FAIL;
969 }
970
971 if (ps_op->s_ive_op.u4_size
972 != sizeof(ih264e_ctl_getversioninfo_op_t))
973 {
974 ps_op->s_ive_op.u4_error_code |= 1
975 << IVE_UNSUPPORTEDPARAM;
976 ps_op->s_ive_op.u4_error_code |=
977 IVE_ERR_OP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT;
978 return IV_FAIL;
979 }
980
981 if (ps_ip->s_ive_ip.pu1_version == NULL)
982 {
983 ps_op->s_ive_op.u4_error_code |= 1
984 << IVE_UNSUPPORTEDPARAM;
985 ps_op->s_ive_op.u4_error_code |=
986 IVE_ERR_CTL_GET_VERSION_BUFFER_IS_NULL;
987 return IV_FAIL;
988 }
989
990 break;
991 }
992
993 case IVE_CMD_CTL_FLUSH:
994 {
995 ih264e_ctl_flush_ip_t *ps_ip = pv_api_ip;
996 ih264e_ctl_flush_op_t *ps_op = pv_api_op;
997
998 if (ps_ip->s_ive_ip.u4_size
999 != sizeof(ih264e_ctl_flush_ip_t))
1000 {
1001 ps_op->s_ive_op.u4_error_code |= 1
1002 << IVE_UNSUPPORTEDPARAM;
1003 ps_op->s_ive_op.u4_error_code |=
1004 IVE_ERR_IP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
1005 return IV_FAIL;
1006 }
1007
1008 if (ps_op->s_ive_op.u4_size
1009 != sizeof(ih264e_ctl_flush_op_t))
1010 {
1011 ps_op->s_ive_op.u4_error_code |= 1
1012 << IVE_UNSUPPORTEDPARAM;
1013 ps_op->s_ive_op.u4_error_code |=
1014 IVE_ERR_OP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT;
1015 return IV_FAIL;
1016 }
1017
1018 break;
1019 }
1020
1021 case IVE_CMD_CTL_RESET:
1022 {
1023 ih264e_ctl_reset_ip_t *ps_ip = pv_api_ip;
1024 ih264e_ctl_reset_op_t *ps_op = pv_api_op;
1025
1026 if (ps_ip->s_ive_ip.u4_size
1027 != sizeof(ih264e_ctl_reset_ip_t))
1028 {
1029 ps_op->s_ive_op.u4_error_code |= 1
1030 << IVE_UNSUPPORTEDPARAM;
1031 ps_op->s_ive_op.u4_error_code |=
1032 IVE_ERR_IP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
1033 return IV_FAIL;
1034 }
1035
1036 if (ps_op->s_ive_op.u4_size
1037 != sizeof(ih264e_ctl_reset_op_t))
1038 {
1039 ps_op->s_ive_op.u4_error_code |= 1
1040 << IVE_UNSUPPORTEDPARAM;
1041 ps_op->s_ive_op.u4_error_code |=
1042 IVE_ERR_OP_CTL_RESET_API_STRUCT_SIZE_INCORRECT;
1043 return IV_FAIL;
1044 }
1045
1046 break;
1047 }
1048
1049 case IVE_CMD_CTL_SET_NUM_CORES:
1050 {
1051 ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
1052 ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op;
1053
1054 if (ps_ip->s_ive_ip.u4_size
1055 != sizeof(ih264e_ctl_set_num_cores_ip_t))
1056 {
1057 ps_op->s_ive_op.u4_error_code |= 1
1058 << IVE_UNSUPPORTEDPARAM;
1059 ps_op->s_ive_op.u4_error_code |=
1060 IVE_ERR_IP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
1061 return IV_FAIL;
1062 }
1063
1064 if (ps_op->s_ive_op.u4_size
1065 != sizeof(ih264e_ctl_set_num_cores_op_t))
1066 {
1067 ps_op->s_ive_op.u4_error_code |= 1
1068 << IVE_UNSUPPORTEDPARAM;
1069 ps_op->s_ive_op.u4_error_code |=
1070 IVE_ERR_OP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT;
1071 return IV_FAIL;
1072 }
1073
1074 if ((ps_ip->s_ive_ip.u4_num_cores < 1)
1075 || (ps_ip->s_ive_ip.u4_num_cores > MAX_NUM_CORES))
1076 {
1077 ps_op->s_ive_op.u4_error_code |= 1
1078 << IVE_UNSUPPORTEDPARAM;
1079 ps_op->s_ive_op.u4_error_code |=
1080 IH264E_INVALID_NUM_CORES;
1081 return IV_FAIL;
1082 }
1083
1084 break;
1085 }
1086
1087 case IVE_CMD_CTL_SET_DIMENSIONS:
1088 {
1089 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
1090
1091 ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
1092 ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op;
1093
1094 if (ps_ip->s_ive_ip.u4_size
1095 != sizeof(ih264e_ctl_set_dimensions_ip_t))
1096 {
1097 ps_op->s_ive_op.u4_error_code |= 1
1098 << IVE_UNSUPPORTEDPARAM;
1099 ps_op->s_ive_op.u4_error_code |=
1100 IVE_ERR_IP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
1101 return IV_FAIL;
1102 }
1103
1104 if (ps_op->s_ive_op.u4_size
1105 != sizeof(ih264e_ctl_set_dimensions_op_t))
1106 {
1107 ps_op->s_ive_op.u4_error_code |= 1
1108 << IVE_UNSUPPORTEDPARAM;
1109 ps_op->s_ive_op.u4_error_code |=
1110 IVE_ERR_OP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT;
1111 return IV_FAIL;
1112 }
1113
1114 if (ps_ip->s_ive_ip.u4_wd < MIN_WD)
1115 {
1116 ps_op->s_ive_op.u4_error_code |= 1
1117 << IVE_UNSUPPORTEDPARAM;
1118 ps_op->s_ive_op.u4_error_code |=
1119 IH264E_WIDTH_NOT_SUPPORTED;
1120 return (IV_FAIL);
1121 }
1122
1123 if (ps_ip->s_ive_ip.u4_wd > ps_codec->s_cfg.u4_max_wd)
1124 {
1125 ps_op->s_ive_op.u4_error_code |= 1
1126 << IVE_UNSUPPORTEDPARAM;
1127 ps_op->s_ive_op.u4_error_code |=
1128 IH264E_WIDTH_NOT_SUPPORTED;
1129 return (IV_FAIL);
1130 }
1131
1132 if (ps_ip->s_ive_ip.u4_ht < MIN_HT)
1133 {
1134 ps_op->s_ive_op.u4_error_code |= 1
1135 << IVE_UNSUPPORTEDPARAM;
1136 ps_op->s_ive_op.u4_error_code |=
1137 IH264E_HEIGHT_NOT_SUPPORTED;
1138 return (IV_FAIL);
1139 }
1140
1141 if (ps_ip->s_ive_ip.u4_ht > ps_codec->s_cfg.u4_max_ht)
1142 {
1143 ps_op->s_ive_op.u4_error_code |= 1
1144 << IVE_UNSUPPORTEDPARAM;
1145 ps_op->s_ive_op.u4_error_code |=
1146 IH264E_HEIGHT_NOT_SUPPORTED;
1147 return (IV_FAIL);
1148 }
1149
1150 break;
1151 }
1152
1153 case IVE_CMD_CTL_SET_FRAMERATE:
1154 {
1155 ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
1156 ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
1157
1158 if (ps_ip->s_ive_ip.u4_size
1159 != sizeof(ih264e_ctl_set_frame_rate_ip_t))
1160 {
1161 ps_op->s_ive_op.u4_error_code |= 1
1162 << IVE_UNSUPPORTEDPARAM;
1163 ps_op->s_ive_op.u4_error_code |=
1164 IVE_ERR_IP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1165 return IV_FAIL;
1166 }
1167
1168 if (ps_op->s_ive_op.u4_size
1169 != sizeof(ih264e_ctl_set_frame_rate_op_t))
1170 {
1171 ps_op->s_ive_op.u4_error_code |= 1
1172 << IVE_UNSUPPORTEDPARAM;
1173 ps_op->s_ive_op.u4_error_code |=
1174 IVE_ERR_OP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT;
1175 return IV_FAIL;
1176 }
1177
1178 if (((ps_ip->s_ive_ip.u4_src_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE)
1179 || ((ps_ip->s_ive_ip.u4_tgt_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE))
1180 {
1181 ps_op->s_ive_op.u4_error_code |= 1
1182 << IVE_UNSUPPORTEDPARAM;
1183 ps_op->s_ive_op.u4_error_code |=
1184 IH264E_FRAME_RATE_NOT_SUPPORTED;
1185 return (IV_FAIL);
1186 }
1187
1188 if ((ps_ip->s_ive_ip.u4_src_frame_rate == 0)
1189 || (ps_ip->s_ive_ip.u4_tgt_frame_rate == 0))
1190 {
1191 ps_op->s_ive_op.u4_error_code |= 1
1192 << IVE_UNSUPPORTEDPARAM;
1193 ps_op->s_ive_op.u4_error_code |=
1194 IH264E_FRAME_RATE_NOT_SUPPORTED;
1195 return (IV_FAIL);
1196 }
1197
1198 if (ps_ip->s_ive_ip.u4_tgt_frame_rate
1199 > ps_ip->s_ive_ip.u4_src_frame_rate)
1200 {
1201 ps_op->s_ive_op.u4_error_code |= 1
1202 << IVE_UNSUPPORTEDPARAM;
1203 ps_op->s_ive_op.u4_error_code |=
1204 IH264E_TGT_FRAME_RATE_EXCEEDS_SRC_FRAME_RATE;
1205 return (IV_FAIL);
1206 }
1207
1208 break;
1209 }
1210
1211 case IVE_CMD_CTL_SET_BITRATE:
1212 {
1213 ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
1214 ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op;
1215
1216 if (ps_ip->s_ive_ip.u4_size
1217 != sizeof(ih264e_ctl_set_bitrate_ip_t))
1218 {
1219 ps_op->s_ive_op.u4_error_code |= 1
1220 << IVE_UNSUPPORTEDPARAM;
1221 ps_op->s_ive_op.u4_error_code |=
1222 IVE_ERR_IP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1223 return IV_FAIL;
1224 }
1225
1226 if (ps_op->s_ive_op.u4_size
1227 != sizeof(ih264e_ctl_set_bitrate_op_t))
1228 {
1229 ps_op->s_ive_op.u4_error_code |= 1
1230 << IVE_UNSUPPORTEDPARAM;
1231 ps_op->s_ive_op.u4_error_code |=
1232 IVE_ERR_OP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT;
1233 return IV_FAIL;
1234 }
1235
1236 if ((ps_ip->s_ive_ip.u4_target_bitrate > DEFAULT_MAX_BITRATE)
1237 || (ps_ip->s_ive_ip.u4_target_bitrate == 0))
1238 {
1239 ps_op->s_ive_op.u4_error_code |= 1
1240 << IVE_UNSUPPORTEDPARAM;
1241 ps_op->s_ive_op.u4_error_code |=
1242 IH264E_BITRATE_NOT_SUPPORTED;
1243 return (IV_FAIL);
1244 }
1245
1246 break;
1247 }
1248
1249 case IVE_CMD_CTL_SET_FRAMETYPE:
1250 {
1251 ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
1252 ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op;
1253
1254 if (ps_ip->s_ive_ip.u4_size
1255 != sizeof(ih264e_ctl_set_frame_type_ip_t))
1256 {
1257 ps_op->s_ive_op.u4_error_code |= 1
1258 << IVE_UNSUPPORTEDPARAM;
1259 ps_op->s_ive_op.u4_error_code |=
1260 IVE_ERR_IP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1261 return IV_FAIL;
1262 }
1263
1264 if (ps_op->s_ive_op.u4_size
1265 != sizeof(ih264e_ctl_set_frame_type_op_t))
1266 {
1267 ps_op->s_ive_op.u4_error_code |= 1
1268 << IVE_UNSUPPORTEDPARAM;
1269 ps_op->s_ive_op.u4_error_code |=
1270 IVE_ERR_OP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT;
1271 return IV_FAIL;
1272 }
1273
1274 if ((ps_ip->s_ive_ip.e_frame_type != IV_NA_FRAME)
1275 && (ps_ip->s_ive_ip.e_frame_type != IV_I_FRAME)
1276 && (ps_ip->s_ive_ip.e_frame_type != IV_P_FRAME)
1277 && (ps_ip->s_ive_ip.e_frame_type != IV_IDR_FRAME))
1278 {
1279 ps_op->s_ive_op.u4_error_code |= 1
1280 << IVE_UNSUPPORTEDPARAM;
1281 ps_op->s_ive_op.u4_error_code |=
1282 IH264E_INVALID_FORCE_FRAME_INPUT;
1283 return IV_FAIL;
1284 }
1285 break;
1286 }
1287
1288 case IVE_CMD_CTL_SET_ME_PARAMS:
1289 {
1290 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle);
1291
1292 ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
1293 ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op;
1294
1295 if (ps_ip->s_ive_ip.u4_size
1296 != sizeof(ih264e_ctl_set_me_params_ip_t))
1297 {
1298 ps_op->s_ive_op.u4_error_code |= 1
1299 << IVE_UNSUPPORTEDPARAM;
1300 ps_op->s_ive_op.u4_error_code |=
1301 IVE_ERR_IP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1302 return IV_FAIL;
1303 }
1304
1305 if (ps_op->s_ive_op.u4_size
1306 != sizeof(ih264e_ctl_set_me_params_op_t))
1307 {
1308 ps_op->s_ive_op.u4_error_code |= 1
1309 << IVE_UNSUPPORTEDPARAM;
1310 ps_op->s_ive_op.u4_error_code |=
1311 IVE_ERR_OP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT;
1312 return IV_FAIL;
1313 }
1314
1315 if ((ps_ip->s_ive_ip.u4_me_speed_preset != FULL_SRCH)
1316 && (ps_ip->s_ive_ip.u4_me_speed_preset != DMND_SRCH)
1317 && (ps_ip->s_ive_ip.u4_me_speed_preset != HEX_SRCH))
1318 {
1319 ps_op->s_ive_op.u4_error_code |= 1
1320 << IVE_UNSUPPORTEDPARAM;
1321 ps_op->s_ive_op.u4_error_code |=
1322 IH264E_INVALID_ME_SPEED_PRESET;
1323 return IV_FAIL;
1324 }
1325
1326 if ((ps_ip->s_ive_ip.u4_enable_hpel != 0)
1327 && (ps_ip->s_ive_ip.u4_enable_hpel != 1))
1328 {
1329 ps_op->s_ive_op.u4_error_code |= 1
1330 << IVE_UNSUPPORTEDPARAM;
1331 ps_op->s_ive_op.u4_error_code |=
1332 IH264E_INVALID_HALFPEL_OPTION;
1333 return IV_FAIL;
1334 }
1335
1336 if ((ps_ip->s_ive_ip.u4_enable_qpel != 0)
1337 && (ps_ip->s_ive_ip.u4_enable_qpel != 1))
1338 {
1339 ps_op->s_ive_op.u4_error_code |= 1
1340 << IVE_UNSUPPORTEDPARAM;
1341 ps_op->s_ive_op.u4_error_code |=
1342 IH264E_INVALID_QPEL_OPTION;
1343 return IV_FAIL;
1344 }
1345
1346 if ((ps_ip->s_ive_ip.u4_enable_fast_sad != 0)
1347 && (ps_ip->s_ive_ip.u4_enable_fast_sad != 1))
1348 {
1349 ps_op->s_ive_op.u4_error_code |= 1
1350 << IVE_UNSUPPORTEDPARAM;
1351 ps_op->s_ive_op.u4_error_code |=
1352 IH264E_INVALID_FAST_SAD_OPTION;
1353 return IV_FAIL;
1354 }
1355
1356 if (ps_ip->s_ive_ip.u4_enable_alt_ref > 255)
1357 {
1358 ps_op->s_ive_op.u4_error_code |= 1
1359 << IVE_UNSUPPORTEDPARAM;
1360 ps_op->s_ive_op.u4_error_code |=
1361 IH264E_INVALID_ALT_REF_OPTION;
1362 return IV_FAIL;
1363 }
1364
1365 if (ps_ip->s_ive_ip.u4_srch_rng_x
1366 > ps_codec->s_cfg.u4_max_srch_rng_x)
1367 {
1368 ps_op->s_ive_op.u4_error_code |= 1
1369 << IVE_UNSUPPORTEDPARAM;
1370 ps_op->s_ive_op.u4_error_code |=
1371 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED;
1372 return (IV_FAIL);
1373 }
1374
1375 if (ps_ip->s_ive_ip.u4_srch_rng_y
1376 > ps_codec->s_cfg.u4_max_srch_rng_y)
1377 {
1378 ps_op->s_ive_op.u4_error_code |= 1
1379 << IVE_UNSUPPORTEDPARAM;
1380 ps_op->s_ive_op.u4_error_code |=
1381 IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED;
1382 return (IV_FAIL);
1383 }
1384
1385 break;
1386 }
1387
1388 case IVE_CMD_CTL_SET_IPE_PARAMS:
1389 {
1390 ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
1391 ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
1392
1393 if (ps_ip->s_ive_ip.u4_size
1394 != sizeof(ih264e_ctl_set_ipe_params_ip_t))
1395 {
1396 ps_op->s_ive_op.u4_error_code |= 1
1397 << IVE_UNSUPPORTEDPARAM;
1398 ps_op->s_ive_op.u4_error_code |=
1399 IVE_ERR_IP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1400 return IV_FAIL;
1401 }
1402
1403 if (ps_op->s_ive_op.u4_size
1404 != sizeof(ih264e_ctl_set_ipe_params_op_t))
1405 {
1406 ps_op->s_ive_op.u4_error_code |= 1
1407 << IVE_UNSUPPORTEDPARAM;
1408 ps_op->s_ive_op.u4_error_code |=
1409 IVE_ERR_OP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT;
1410 return IV_FAIL;
1411 }
1412
1413 if ((ps_ip->s_ive_ip.u4_enable_intra_4x4 != 0)
1414 && (ps_ip->s_ive_ip.u4_enable_intra_4x4 != 1))
1415 {
1416 ps_op->s_ive_op.u4_error_code |= 1
1417 << IVE_UNSUPPORTEDPARAM;
1418 ps_op->s_ive_op.u4_error_code |=
1419 IH264E_INVALID_INTRA4x4_OPTION;
1420 return IV_FAIL;
1421 }
1422
1423 if ((ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_CONFIG)
1424 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_SLOWEST)
1425 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_NORMAL)
1426 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FAST)
1427 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_HIGH_SPEED)
1428 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FASTEST))
1429 {
1430 ps_op->s_ive_op.u4_error_code |= 1
1431 << IVE_UNSUPPORTEDPARAM;
1432 ps_op->s_ive_op.u4_error_code |=
1433 IH264E_INVALID_ENC_SPEED_PRESET;
1434 return IV_FAIL;
1435 }
1436
1437 break;
1438 }
1439
1440 case IVE_CMD_CTL_SET_GOP_PARAMS:
1441 {
1442 ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
1443 ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op;
1444
1445 if (ps_ip->s_ive_ip.u4_size
1446 != sizeof(ih264e_ctl_set_gop_params_ip_t))
1447 {
1448 ps_op->s_ive_op.u4_error_code |= 1
1449 << IVE_UNSUPPORTEDPARAM;
1450 ps_op->s_ive_op.u4_error_code |=
1451 IVE_ERR_IP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1452 return IV_FAIL;
1453 }
1454
1455 if (ps_op->s_ive_op.u4_size
1456 != sizeof(ih264e_ctl_set_gop_params_op_t))
1457 {
1458 ps_op->s_ive_op.u4_error_code |= 1
1459 << IVE_UNSUPPORTEDPARAM;
1460 ps_op->s_ive_op.u4_error_code |=
1461 IVE_ERR_OP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT;
1462 return IV_FAIL;
1463 }
1464
1465 if ((ps_ip->s_ive_ip.u4_i_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE)
1466 || (ps_ip->s_ive_ip.u4_i_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1467 {
1468 ps_op->s_ive_op.u4_error_code |= 1
1469 << IVE_UNSUPPORTEDPARAM;
1470 ps_op->s_ive_op.u4_error_code |=
1471 IH264E_INVALID_INTRA_FRAME_INTERVAL;
1472 return IV_FAIL;
1473 }
1474
1475 if ((ps_ip->s_ive_ip.u4_idr_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE)
1476 || (ps_ip->s_ive_ip.u4_idr_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE))
1477 {
1478 ps_op->s_ive_op.u4_error_code |= 1
1479 << IVE_UNSUPPORTEDPARAM;
1480 ps_op->s_ive_op.u4_error_code |=
1481 IH264E_INVALID_IDR_FRAME_INTERVAL;
1482 return IV_FAIL;
1483 }
1484
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1485 break;
1486 }
1487
1488 case IVE_CMD_CTL_SET_DEBLOCK_PARAMS:
1489 {
1490 ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
1491 ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
1492
1493 if (ps_ip->s_ive_ip.u4_size
1494 != sizeof(ih264e_ctl_set_deblock_params_ip_t))
1495 {
1496 ps_op->s_ive_op.u4_error_code |= 1
1497 << IVE_UNSUPPORTEDPARAM;
1498 ps_op->s_ive_op.u4_error_code |=
1499 IVE_ERR_IP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1500 return IV_FAIL;
1501 }
1502
1503 if (ps_op->s_ive_op.u4_size
1504 != sizeof(ih264e_ctl_set_deblock_params_op_t))
1505 {
1506 ps_op->s_ive_op.u4_error_code |= 1
1507 << IVE_UNSUPPORTEDPARAM;
1508 ps_op->s_ive_op.u4_error_code |=
1509 IVE_ERR_OP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT;
1510 return IV_FAIL;
1511 }
1512
1513 if ((ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_0)
1514 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_2)
1515 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_3)
1516 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_4))
1517 {
1518 ps_op->s_ive_op.u4_error_code |= 1
1519 << IVE_UNSUPPORTEDPARAM;
1520 ps_op->s_ive_op.u4_error_code |=
1521 IH264E_INVALID_DEBLOCKING_TYPE_INPUT;
1522 return IV_FAIL;
1523 }
1524
1525 break;
1526 }
1527
1528 case IVE_CMD_CTL_SET_QP:
1529 {
1530 ih264e_ctl_set_qp_ip_t *ps_ip = pv_api_ip;
1531 ih264e_ctl_set_qp_op_t *ps_op = pv_api_op;
1532
1533 if (ps_ip->s_ive_ip.u4_size
1534 != sizeof(ih264e_ctl_set_qp_ip_t))
1535 {
1536 ps_op->s_ive_op.u4_error_code |= 1
1537 << IVE_UNSUPPORTEDPARAM;
1538 ps_op->s_ive_op.u4_error_code |=
1539 IVE_ERR_IP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1540 return IV_FAIL;
1541 }
1542
1543 if (ps_op->s_ive_op.u4_size
1544 != sizeof(ih264e_ctl_set_qp_op_t))
1545 {
1546 ps_op->s_ive_op.u4_error_code |= 1
1547 << IVE_UNSUPPORTEDPARAM;
1548 ps_op->s_ive_op.u4_error_code |=
1549 IVE_ERR_OP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT;
1550 return IV_FAIL;
1551 }
1552
1553 if ((ps_ip->s_ive_ip.u4_i_qp_max > MAX_H264_QP)
1554 || (ps_ip->s_ive_ip.u4_p_qp_max > MAX_H264_QP)
1555 || (ps_ip->s_ive_ip.u4_b_qp_max > MAX_H264_QP))
1556 {
1557 ps_op->s_ive_op.u4_error_code |= 1
1558 << IVE_UNSUPPORTEDPARAM;
1559 ps_op->s_ive_op.u4_error_code |=
1560 IH264E_INVALID_MAX_FRAME_QP;
1561 return IV_FAIL;
1562 }
1563
1564 if ((ps_ip->s_ive_ip.u4_i_qp_min > ps_ip->s_ive_ip.u4_i_qp_max)
1565 || (ps_ip->s_ive_ip.u4_p_qp_min > ps_ip->s_ive_ip.u4_p_qp_max)
1566 || (ps_ip->s_ive_ip.u4_b_qp_min > ps_ip->s_ive_ip.u4_b_qp_max))
1567 {
1568 ps_op->s_ive_op.u4_error_code |= 1
1569 << IVE_UNSUPPORTEDPARAM;
1570 ps_op->s_ive_op.u4_error_code |=
1571 IH264E_INVALID_MIN_FRAME_QP;
1572 return IV_FAIL;
1573 }
1574
1575 if ((ps_ip->s_ive_ip.u4_i_qp > ps_ip->s_ive_ip.u4_i_qp_max)
1576 || (ps_ip->s_ive_ip.u4_p_qp > ps_ip->s_ive_ip.u4_p_qp_max)
1577 || (ps_ip->s_ive_ip.u4_b_qp > ps_ip->s_ive_ip.u4_b_qp_max))
1578 {
1579 ps_op->s_ive_op.u4_error_code |= 1
1580 << IVE_UNSUPPORTEDPARAM;
1581 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP;
1582 return IV_FAIL;
1583 }
1584
1585 if ((ps_ip->s_ive_ip.u4_i_qp < ps_ip->s_ive_ip.u4_i_qp_min)
1586 || (ps_ip->s_ive_ip.u4_p_qp < ps_ip->s_ive_ip.u4_p_qp_min)
1587 || (ps_ip->s_ive_ip.u4_b_qp < ps_ip->s_ive_ip.u4_b_qp_min))
1588 {
1589 ps_op->s_ive_op.u4_error_code |= 1
1590 << IVE_UNSUPPORTEDPARAM;
1591 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP;
1592 return IV_FAIL;
1593 }
1594
1595 break;
1596 }
1597
1598 case IVE_CMD_CTL_SET_ENC_MODE:
1599 {
1600 ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
1601 ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
1602
1603 if (ps_ip->s_ive_ip.u4_size
1604 != sizeof(ih264e_ctl_set_enc_mode_ip_t))
1605 {
1606 ps_op->s_ive_op.u4_error_code |= 1
1607 << IVE_UNSUPPORTEDPARAM;
1608 ps_op->s_ive_op.u4_error_code |=
1609 IVE_ERR_IP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
1610 return IV_FAIL;
1611 }
1612
1613 if (ps_op->s_ive_op.u4_size
1614 != sizeof(ih264e_ctl_set_enc_mode_op_t))
1615 {
1616 ps_op->s_ive_op.u4_error_code |= 1
1617 << IVE_UNSUPPORTEDPARAM;
1618 ps_op->s_ive_op.u4_error_code |=
1619 IVE_ERR_OP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT;
1620 return IV_FAIL;
1621 }
1622
1623 if ((ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_HEADER)
1624 && (ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_PICTURE))
1625 {
1626 ps_op->s_ive_op.u4_error_code |= 1
1627 << IVE_UNSUPPORTEDPARAM;
1628 ps_op->s_ive_op.u4_error_code |=
1629 IH264E_INVALID_ENC_OPERATION_MODE;
1630 return IV_FAIL;
1631 }
1632
1633 break;
1634 }
1635
1636 case IVE_CMD_CTL_SET_VBV_PARAMS:
1637 {
1638 ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
1639 ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
1640
1641 if (ps_ip->s_ive_ip.u4_size
1642 != sizeof(ih264e_ctl_set_vbv_params_ip_t))
1643 {
1644 ps_op->s_ive_op.u4_error_code |= 1
1645 << IVE_UNSUPPORTEDPARAM;
1646 ps_op->s_ive_op.u4_error_code |=
1647 IVE_ERR_IP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
1648 return IV_FAIL;
1649 }
1650
1651 if (ps_op->s_ive_op.u4_size
1652 != sizeof(ih264e_ctl_set_vbv_params_op_t))
1653 {
1654 ps_op->s_ive_op.u4_error_code |= 1
1655 << IVE_UNSUPPORTEDPARAM;
1656 ps_op->s_ive_op.u4_error_code |=
1657 IVE_ERR_OP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT;
1658 return IV_FAIL;
1659 }
1660
1661 if ((ps_ip->s_ive_ip.u4_vbv_buffer_delay < DEFAULT_MIN_BUFFER_DELAY)
1662 || (ps_ip->s_ive_ip.u4_vbv_buffer_delay > DEFAULT_MAX_BUFFER_DELAY))
1663 {
1664 ps_op->s_ive_op.u4_error_code |= 1
1665 << IVE_UNSUPPORTEDPARAM;
1666 ps_op->s_ive_op.u4_error_code |=
1667 IH264E_INVALID_BUFFER_DELAY;
1668 return IV_FAIL;
1669 }
1670
1671 break;
1672 }
1673
1674 case IVE_CMD_CTL_SET_AIR_PARAMS:
1675 {
1676 ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
1677 ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op;
1678
1679 if (ps_ip->s_ive_ip.u4_size
1680 != sizeof(ih264e_ctl_set_air_params_ip_t))
1681 {
1682 ps_op->s_ive_op.u4_error_code |= 1
1683 << IVE_UNSUPPORTEDPARAM;
1684 ps_op->s_ive_op.u4_error_code |=
1685 IVE_ERR_IP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
1686 return IV_FAIL;
1687 }
1688
1689 if (ps_op->s_ive_op.u4_size
1690 != sizeof(ih264e_ctl_set_air_params_op_t))
1691 {
1692 ps_op->s_ive_op.u4_error_code |= 1
1693 << IVE_UNSUPPORTEDPARAM;
1694 ps_op->s_ive_op.u4_error_code |=
1695 IVE_ERR_OP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT;
1696 return IV_FAIL;
1697 }
1698
1699 if ((ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_NONE)
1700 && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_CYCLIC)
1701 && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_RANDOM))
1702 {
1703 ps_op->s_ive_op.u4_error_code |= 1
1704 << IVE_UNSUPPORTEDPARAM;
1705 ps_op->s_ive_op.u4_error_code |=
1706 IH264E_INVALID_AIR_MODE;
1707 return IV_FAIL;
1708 }
1709
1710 if (ps_ip->s_ive_ip.u4_air_refresh_period == 0)
1711 {
1712 ps_op->s_ive_op.u4_error_code |= 1
1713 << IVE_UNSUPPORTEDPARAM;
1714 ps_op->s_ive_op.u4_error_code |=
1715 IH264E_INVALID_AIR_REFRESH_PERIOD;
1716 return IV_FAIL;
1717 }
1718
1719 break;
1720 }
1721
1722 case IVE_CMD_CTL_SET_PROFILE_PARAMS:
1723 {
1724 ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
1725 ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op;
1726
1727 if (ps_ip->s_ive_ip.u4_size
1728 != sizeof(ih264e_ctl_set_profile_params_ip_t))
1729 {
1730 ps_op->s_ive_op.u4_error_code |= 1
1731 << IVE_UNSUPPORTEDPARAM;
1732 ps_op->s_ive_op.u4_error_code |=
1733 IVE_ERR_IP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
1734 return IV_FAIL;
1735 }
1736
1737 if (ps_op->s_ive_op.u4_size
1738 != sizeof(ih264e_ctl_set_profile_params_op_t))
1739 {
1740 ps_op->s_ive_op.u4_error_code |= 1
1741 << IVE_UNSUPPORTEDPARAM;
1742 ps_op->s_ive_op.u4_error_code |=
1743 IVE_ERR_OP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT;
1744 return IV_FAIL;
1745 }
1746
1747 if (ps_ip->s_ive_ip.e_profile != IV_PROFILE_BASE)
1748 {
1749 ps_op->s_ive_op.u4_error_code |= 1
1750 << IVE_UNSUPPORTEDPARAM;
1751 ps_op->s_ive_op.u4_error_code |=
1752 IH264E_PROFILE_NOT_SUPPORTED;
1753 return IV_FAIL;
1754 }
1755
1756 break;
1757 }
1758
1759 default:
1760 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
1761 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_SUB_CMD;
1762 return IV_FAIL;
1763 }
1764
1765 break;
1766 }
1767
1768 default:
1769 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM;
1770 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD;
1771 return IV_FAIL;
1772 }
1773
1774 return IV_SUCCESS;
1775}
1776
1777/**
1778*******************************************************************************
1779*
1780* @brief update encoder configuration parameters
1781*
1782* @par Description:
1783* updates encoder configuration parameters from the given config set.
1784* Initialize/reinitialize codec parameters according to new configurations.
1785*
1786* @param[in] ps_codec
1787* Pointer to codec context
1788*
1789* @param[in] ps_cfg
1790* Pointer to config param set
1791*
1792* @remarks none
1793*
1794*******************************************************************************
1795*/
1796IH264E_ERROR_T ih264e_codec_update_config(codec_t *ps_codec,
1797 cfg_params_t *ps_cfg)
1798{
1799 /* config params */
1800 cfg_params_t *ps_curr_cfg = &ps_codec->s_cfg;
1801
1802 /* error status */
1803 IH264E_ERROR_T err = IH264E_SUCCESS;
1804
1805 /* temp var */
1806 UWORD32 u4_init_rc = 0;
1807
1808 /***********************/
1809 /* UPDATE CODEC CONFIG */
1810 /***********************/
1811 if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DIMENSIONS)
1812 {
1813 UWORD32 wd_aln = ALIGN16(ps_cfg->u4_wd);
1814 UWORD32 ht_aln = ALIGN16(ps_cfg->u4_ht);
1815
1816 if (ps_curr_cfg->u4_wd != wd_aln || ps_curr_cfg->u4_ht != ht_aln
1817 || ps_curr_cfg->u4_strd != ps_cfg->u4_strd
1818 || ps_curr_cfg->u4_disp_wd != ps_cfg->u4_disp_wd
1819 || ps_curr_cfg->u4_disp_ht != ps_cfg->u4_disp_ht)
1820 {
1821 ps_curr_cfg->u4_wd = wd_aln;
1822 ps_curr_cfg->u4_ht = ht_aln;
1823 ps_curr_cfg->u4_strd = ps_cfg->u4_strd;
1824
1825 if (ps_curr_cfg->u4_strd == 0)
1826 {
1827 ps_curr_cfg->u4_strd = ps_curr_cfg->u4_wd;
1828 }
1829
1830 ps_curr_cfg->u4_disp_wd = ps_cfg->u4_disp_wd;
1831 ps_curr_cfg->u4_disp_ht = ps_cfg->u4_disp_ht;
1832
1833 ps_curr_cfg->i4_wd_mbs = ps_curr_cfg->u4_wd >> 4;
1834 ps_curr_cfg->i4_ht_mbs = ps_curr_cfg->u4_ht >> 4;
1835
1836 ps_codec->i4_src_strd = ps_codec->s_cfg.u4_strd;
1837 ps_codec->i4_rec_strd = ALIGN16(ps_cfg->u4_wd) + PAD_WD;
1838
1839 /* If number of MBs in a frame changes the air map also changes.
1840 * Hence recompute air map also reset air pic cnt */
1841 if (ps_codec->s_cfg.e_air_mode != IVE_AIR_MODE_NONE)
1842 {
1843 /* re-init the air map */
1844 ih264e_init_air_map(ps_codec);
1845
1846 /* reset air counter */
1847 ps_codec->i4_air_pic_cnt = -1;
1848 }
1849
1850 /* initialize mv bank buffer manager */
1851 err = ih264e_mv_buf_mgr_add_bufs(ps_codec);
1852 if (err != IH264E_SUCCESS)
1853 return err;
1854
1855 /* initialize ref bank buffer manager */
1856 err = ih264e_pic_buf_mgr_add_bufs(ps_codec);
1857 if (err != IH264E_SUCCESS)
1858 return err;
1859
1860 /* since dimension changed, start new sequence by forcing IDR */
1861 ps_codec->force_curr_frame_type = IV_IDR_FRAME;
1862
1863 /* in case dimension changes, we need to reinitialize RC as the
1864 * old model shall not fit further */
1865 u4_init_rc = 1;
1866
1867 /* when the dimension changes, the header needs to be regenerated */
Martin Storsjoafe8d032015-06-23 11:14:45 +0300[diff] [blame]1868 ps_codec->i4_gen_header = 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1869 }
1870 }
1871 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMERATE)
1872 {
1873 /* temp var */
1874 UWORD32 u4_src_ticks, u4_tgt_ticks;
1875
1876 u4_src_ticks = ih264e_frame_time_get_src_ticks(
1877 ps_codec->s_rate_control.pps_frame_time);
1878
1879 u4_tgt_ticks = ih264e_frame_time_get_tgt_ticks(
1880 ps_codec->s_rate_control.pps_frame_time);
1881
1882 /* Change frame rate */
1883 if (ps_codec->s_cfg.u4_src_frame_rate
1884 != ps_cfg->u4_src_frame_rate * 1000)
1885 {
1886 ps_codec->s_cfg.u4_src_frame_rate = ps_cfg->u4_src_frame_rate
1887 * 1000;
1888
1889 ih264e_frame_time_update_src_frame_rate(
1890 ps_codec->s_rate_control.pps_frame_time,
1891 ps_codec->s_cfg.u4_src_frame_rate);
1892
1893 ih264_time_stamp_update_frame_rate(
1894 ps_codec->s_rate_control.pps_time_stamp,
1895 ps_codec->s_cfg.u4_src_frame_rate);
1896
1897 irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api,
1898 ps_codec->s_cfg.u4_src_frame_rate,
1899 u4_src_ticks, u4_tgt_ticks);
1900 }
1901
1902 if (ps_codec->s_cfg.u4_tgt_frame_rate
1903 != ps_cfg->u4_tgt_frame_rate * 1000)
1904 {
1905 ps_codec->s_cfg.u4_tgt_frame_rate = ps_cfg->u4_tgt_frame_rate
1906 * 1000;
1907
1908 ih264e_frame_time_update_tgt_frame_rate(
1909 ps_codec->s_rate_control.pps_frame_time,
1910 ps_codec->s_cfg.u4_tgt_frame_rate);
1911
1912 irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api,
1913 ps_codec->s_cfg.u4_src_frame_rate,
1914 u4_src_ticks, u4_tgt_ticks);
1915
1916 irc_change_frm_rate_for_bit_alloc(
1917 ps_codec->s_rate_control.pps_rate_control_api,
1918 ps_codec->s_cfg.u4_tgt_frame_rate);
1919 }
1920
1921 }
1922 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_BITRATE)
1923 {
1924 if (ps_curr_cfg->u4_target_bitrate != ps_cfg->u4_target_bitrate)
1925 {
1926 if (IVE_RC_NONE != ps_curr_cfg->e_rc_mode)
1927 irc_change_avg_bit_rate(
1928 ps_codec->s_rate_control.pps_rate_control_api,
1929 ps_cfg->u4_target_bitrate);
1930
1931 ps_curr_cfg->u4_target_bitrate = ps_cfg->u4_target_bitrate;
1932 }
1933 }
1934 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMETYPE)
1935 {
1936 switch (ps_cfg->e_frame_type)
1937 {
1938 case IV_I_FRAME:
1939 ps_codec->force_curr_frame_type = IV_I_FRAME;
1940 break;
1941
1942 case IV_IDR_FRAME:
1943 ps_codec->force_curr_frame_type = IV_IDR_FRAME;
1944 break;
1945
1946 case IV_P_FRAME:
1947 default:
1948 break;
1949 }
1950 }
1951 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ME_PARAMS)
1952 {
1953 if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
1954 {
1955 ps_codec->s_cfg.u4_enable_hpel = ps_cfg->u4_enable_hpel;
1956 ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad;
1957 ps_codec->s_cfg.u4_me_speed_preset = ps_cfg->u4_me_speed_preset;
1958 ps_codec->s_cfg.u4_enable_qpel = ps_cfg->u4_enable_qpel;
1959 }
1960 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FASTEST)
1961 {
1962 ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad;
1963 }
1964 ps_codec->s_cfg.u4_srch_rng_x = ps_cfg->u4_srch_rng_x;
1965 ps_codec->s_cfg.u4_srch_rng_y = ps_cfg->u4_srch_rng_y;
1966
1967 if (ps_codec->s_cfg.u4_enable_alt_ref != ps_cfg->u4_enable_alt_ref)
1968 {
1969 ps_codec->s_cfg.u4_enable_alt_ref = ps_cfg->u4_enable_alt_ref;
1970 ps_codec->u4_is_curr_frm_ref = 1;
1971 }
1972 }
1973 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_IPE_PARAMS)
1974 {
1975 ps_curr_cfg->u4_enc_speed_preset = ps_cfg->u4_enc_speed_preset;
1976
1977 if (ps_curr_cfg->u4_enc_speed_preset == IVE_SLOWEST)
1978 {/* high quality */
1979 /* enable diamond search */
1980 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
1981 ps_curr_cfg->u4_enable_fast_sad = 0;
1982
1983 /* disable intra 4x4 */
1984 ps_curr_cfg->u4_enable_intra_4x4 = 1;
1985 ps_codec->luma_energy_compaction[1] =
1986 ih264e_code_luma_intra_macroblock_4x4_rdopt_on;
1987
1988 /* sub pel off */
1989 ps_curr_cfg->u4_enable_hpel = 1;
1990
1991 /* deblocking off */
1992 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0;
1993
1994 /* disabled intra inter gating in Inter slices */
1995 ps_codec->u4_inter_gate = 0;
1996 }
1997 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_NORMAL)
1998 {/* normal */
1999 /* enable diamond search */
2000 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2001 ps_curr_cfg->u4_enable_fast_sad = 0;
2002
2003 /* disable intra 4x4 */
2004 ps_curr_cfg->u4_enable_intra_4x4 = 1;
2005
2006 /* sub pel off */
2007 ps_curr_cfg->u4_enable_hpel = 1;
2008
2009 /* deblocking off */
2010 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0;
2011
2012 /* disabled intra inter gating in Inter slices */
2013 ps_codec->u4_inter_gate = 0;
2014 }
2015 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FAST)
2016 {/* normal */
2017 /* enable diamond search */
2018 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2019 ps_curr_cfg->u4_enable_fast_sad = 0;
2020
2021 /* disable intra 4x4 */
2022 ps_curr_cfg->u4_enable_intra_4x4 = 0;
2023
2024 /* sub pel off */
2025 ps_curr_cfg->u4_enable_hpel = 1;
2026
2027 /* deblocking off */
2028 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0;
2029
2030 /* disabled intra inter gating in Inter slices */
2031 ps_codec->u4_inter_gate = 1;
2032 }
2033 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_HIGH_SPEED)
2034 {/* fast */
2035 /* enable diamond search */
2036 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2037 ps_curr_cfg->u4_enable_fast_sad = 0;
2038
2039 /* disable intra 4x4 */
2040 ps_curr_cfg->u4_enable_intra_4x4 = 0;
2041
2042 /* sub pel off */
2043 ps_curr_cfg->u4_enable_hpel = 0;
2044
2045 /* deblocking off */
2046 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_4;
2047
2048 /* disabled intra inter gating in Inter slices */
2049 ps_codec->u4_inter_gate = 0;
2050 }
2051 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FASTEST)
2052 {/* fastest */
2053 /* enable diamond search */
2054 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH;
2055 //u4_num_layers = 4;
2056
2057 /* disable intra 4x4 */
2058 ps_curr_cfg->u4_enable_intra_4x4 = 0;
2059
2060 /* sub pel off */
2061 ps_curr_cfg->u4_enable_hpel = 0;
2062
2063 /* deblocking off */
2064 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_4;
2065
2066 /* disabled intra inter gating in Inter slices */
2067 ps_codec->u4_inter_gate = 1;
2068 }
2069 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
2070 {
2071 ps_curr_cfg->u4_enable_intra_4x4 = ps_cfg->u4_enable_intra_4x4;
2072 }
2073 }
2074 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_GOP_PARAMS)
2075 {
2076 if (ps_curr_cfg->u4_i_frm_interval != ps_cfg->u4_i_frm_interval)
2077 {
2078 ps_curr_cfg->u4_i_frm_interval = ps_cfg->u4_i_frm_interval;
2079
2080 /* reset air counter */
2081 ps_codec->i4_air_pic_cnt = -1;
2082
2083 /* re-init air map */
2084 ih264e_init_air_map(ps_codec);
2085
2086 /*Effect intra frame interval change*/
2087
2088 irc_change_intra_frm_int_call(
2089 ps_codec->s_rate_control.pps_rate_control_api,
2090 ps_curr_cfg->u4_i_frm_interval);
2091 }
2092
2093 ps_curr_cfg->u4_idr_frm_interval = ps_cfg->u4_idr_frm_interval;
2094
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2095 }
2096 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DEBLOCK_PARAMS)
2097 {
2098 if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG)
2099 {
2100 ps_curr_cfg->u4_disable_deblock_level =
2101 ps_cfg->u4_disable_deblock_level;
2102 }
2103 }
2104 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_QP)
2105 {
2106 UWORD8 au1_init_qp[MAX_PIC_TYPE];
2107 UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE];
2108
2109 ps_codec->s_cfg.u4_i_qp_max = ps_cfg->u4_i_qp_max;
2110 ps_codec->s_cfg.u4_i_qp_min = ps_cfg->u4_i_qp_min;
2111 ps_codec->s_cfg.u4_i_qp = ps_cfg->u4_i_qp;
2112
2113 ps_codec->s_cfg.u4_p_qp_max = ps_cfg->u4_p_qp_max;
2114 ps_codec->s_cfg.u4_p_qp_min = ps_cfg->u4_p_qp_min;
2115 ps_codec->s_cfg.u4_p_qp = ps_cfg->u4_p_qp;
2116
2117 ps_codec->s_cfg.u4_b_qp_max = ps_cfg->u4_b_qp_max;
2118 ps_codec->s_cfg.u4_b_qp_min = ps_cfg->u4_b_qp_min;
2119 ps_codec->s_cfg.u4_b_qp = ps_cfg->u4_b_qp;
2120
2121 /* update rc lib with modified qp */
2122 au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp];
2123 au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp];
2124 au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp];
2125
2126 irc_change_init_qp(ps_codec->s_rate_control.pps_rate_control_api,
2127 au1_init_qp);
2128
2129 au1_min_max_qp[2 * I_PIC] =
2130 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min];
2131 au1_min_max_qp[2 * I_PIC + 1] =
2132 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max];
2133
2134 au1_min_max_qp[2 * P_PIC] =
2135 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min];
2136 au1_min_max_qp[2 * P_PIC + 1] =
2137 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max];
2138
2139 au1_min_max_qp[2 * B_PIC] =
2140 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min];
2141 au1_min_max_qp[2 * B_PIC + 1] =
2142 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max];
2143
2144 irc_change_min_max_qp(ps_codec->s_rate_control.pps_rate_control_api,
2145 au1_min_max_qp);
2146 }
2147 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ENC_MODE)
2148 {
2149 ps_codec->s_cfg.e_enc_mode = ps_cfg->e_enc_mode;
2150
2151 if (ps_codec->s_cfg.e_enc_mode == IVE_ENC_MODE_HEADER)
2152 {
2153 ps_codec->i4_header_mode = 1;
2154 ps_codec->s_cfg.e_enc_mode = IVE_ENC_MODE_PICTURE;
2155 }
2156 else
2157 {
2158 ps_codec->i4_header_mode = 0;
2159 }
2160 }
2161 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_VBV_PARAMS
2162 && IVE_RC_NONE != ps_codec->s_cfg.e_rc_mode)
2163 {
2164 ps_codec->s_cfg.u4_vbv_buf_size = ps_cfg->u4_vbv_buf_size;
2165 ps_codec->s_cfg.u4_vbv_buffer_delay = ps_cfg->u4_vbv_buffer_delay;
2166
2167 // irc_change_buffer_delay(ps_codec->s_rate_control.pps_rate_control_api, ps_codec->s_cfg.u4_vbv_buffer_delay);
2168
2169 // TODO: remove this when the support for changing buffer dynamically
2170 // is yet to be added.
2171 u4_init_rc = 1;
2172 }
2173 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_AIR_PARAMS)
2174 {
2175 if (ps_curr_cfg->e_air_mode != ps_cfg->e_air_mode
2176 || ps_curr_cfg->u4_air_refresh_period
2177 != ps_cfg->u4_air_refresh_period)
2178 {
2179 ps_curr_cfg->e_air_mode = ps_cfg->e_air_mode;
2180 ps_curr_cfg->u4_air_refresh_period = ps_cfg->u4_air_refresh_period;
2181
2182 ih264e_init_air_map(ps_codec);
2183
2184 /* reset air counter */
2185 ps_codec->i4_air_pic_cnt = -1;
2186 }
2187 }
2188 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_PROFILE_PARAMS)
2189 {
2190 ps_codec->s_cfg.e_profile = ps_cfg->e_profile;
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]2191 ps_codec->s_cfg.u4_entropy_coding_mode = ps_cfg->u4_entropy_coding_mode;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2192 }
2193 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_NUM_CORES)
2194 {
2195 ps_codec->s_cfg.u4_num_cores = ps_cfg->u4_num_cores;
2196 }
2197
2198 /* reset RC model */
2199 if (u4_init_rc)
2200 {
2201 /* init qp */
2202 UWORD8 au1_init_qp[MAX_PIC_TYPE];
2203
2204 /* min max qp */
2205 UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE];
2206
2207 /* init i,p,b qp */
2208 au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp];
2209 au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp];
2210 au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp];
2211
2212 /* init min max qp */
2213 au1_min_max_qp[2 * I_PIC] =
2214 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min];
2215 au1_min_max_qp[2 * I_PIC + 1] =
2216 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max];
2217
2218 au1_min_max_qp[2 * P_PIC] =
2219 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min];
2220 au1_min_max_qp[2 * P_PIC + 1] =
2221 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max];
2222
2223 au1_min_max_qp[2 * B_PIC] =
2224 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min];
2225 au1_min_max_qp[2 * B_PIC + 1] =
2226 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max];
2227
2228 /* get rc mode */
2229 switch (ps_codec->s_cfg.e_rc_mode)
2230 {
2231 case IVE_RC_STORAGE:
2232 ps_codec->s_rate_control.e_rc_type = VBR_STORAGE;
2233 break;
2234
2235 case IVE_RC_CBR_NON_LOW_DELAY:
2236 ps_codec->s_rate_control.e_rc_type = CBR_NLDRC;
2237 break;
2238
2239 case IVE_RC_CBR_LOW_DELAY:
2240 ps_codec->s_rate_control.e_rc_type = CBR_LDRC;
2241 break;
2242
2243 case IVE_RC_NONE:
2244 ps_codec->s_rate_control.e_rc_type = CONST_QP;
2245 break;
2246
2247 default:
2248 break;
2249 }
2250
2251 /* init rate control */
2252 ih264e_rc_init(ps_codec->s_rate_control.pps_rate_control_api,
2253 ps_codec->s_rate_control.pps_frame_time,
2254 ps_codec->s_rate_control.pps_time_stamp,
2255 ps_codec->s_rate_control.pps_pd_frm_rate,
2256 ps_codec->s_cfg.u4_max_framerate,
2257 ps_codec->s_cfg.u4_src_frame_rate,
2258 ps_codec->s_cfg.u4_tgt_frame_rate,
2259 ps_codec->s_rate_control.e_rc_type,
2260 ps_codec->s_cfg.u4_target_bitrate,
2261 ps_codec->s_cfg.u4_max_bitrate,
2262 ps_codec->s_cfg.u4_vbv_buffer_delay,
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]2263 ps_codec->s_cfg.u4_i_frm_interval,
2264 ps_codec->s_cfg.u4_num_bframes + 1, au1_init_qp,
2265 ps_codec->s_cfg.u4_num_bframes + 2, au1_min_max_qp,
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2266 ps_codec->s_cfg.u4_max_level);
2267 }
2268
2269 return err;
2270}
2271
2272/**
2273*******************************************************************************
2274*
2275* @brief
2276* Sets default encoder config parameters
2277*
2278* @par Description:
2279* Sets default dynamic parameters. Will be called in ih264e_init() to ensure
2280* that even if set_params is not called, codec continues to work
2281*
2282* @param[in] ps_cfg
2283* Pointer to encoder config params
2284*
2285* @returns error status
2286*
2287* @remarks none
2288*
2289*******************************************************************************
2290*/
2291static WORD32 ih264e_set_default_params(cfg_params_t *ps_cfg)
2292{
2293 WORD32 ret = IV_SUCCESS;
2294
2295 ps_cfg->u4_max_wd = MAX_WD;
2296 ps_cfg->u4_max_ht = MAX_HT;
2297 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
2298 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
2299 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
2300 ps_cfg->e_inp_color_fmt = IV_YUV_420SP_UV;
2301 ps_cfg->u4_enable_recon = DEFAULT_RECON_ENABLE;
2302 ps_cfg->e_recon_color_fmt = IV_YUV_420P;
2303 ps_cfg->u4_enc_speed_preset = IVE_FASTEST;
2304 ps_cfg->e_rc_mode = DEFAULT_RC;
2305 ps_cfg->u4_max_framerate = DEFAULT_MAX_FRAMERATE;
2306 ps_cfg->u4_max_bitrate = DEFAULT_MAX_BITRATE;
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]2307 ps_cfg->u4_num_bframes = DEFAULT_MAX_NUM_BFRAMES;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2308 ps_cfg->e_content_type = IV_PROGRESSIVE;
2309 ps_cfg->u4_max_srch_rng_x = DEFAULT_MAX_SRCH_RANGE_X;
2310 ps_cfg->u4_max_srch_rng_y = DEFAULT_MAX_SRCH_RANGE_Y;
2311 ps_cfg->e_slice_mode = IVE_SLICE_MODE_NONE;
2312 ps_cfg->u4_slice_param = DEFAULT_SLICE_PARAM;
2313 ps_cfg->e_arch = ih264e_default_arch();
2314 ps_cfg->e_soc = SOC_GENERIC;
2315 ps_cfg->u4_disp_wd = MAX_WD;
2316 ps_cfg->u4_disp_ht = MAX_HT;
2317 ps_cfg->u4_wd = MAX_WD;
2318 ps_cfg->u4_ht = MAX_HT;
2319 ps_cfg->u4_strd = ALIGN16(MAX_WD);
2320 ps_cfg->u4_src_frame_rate = DEFAULT_SRC_FRAME_RATE;
2321 ps_cfg->u4_tgt_frame_rate = DEFAULT_TGT_FRAME_RATE;
2322 ps_cfg->u4_target_bitrate = DEFAULT_BITRATE;
2323 ps_cfg->e_frame_type = IV_NA_FRAME;
2324 ps_cfg->e_enc_mode = IVE_ENC_MODE_DEFAULT;
2325 ps_cfg->u4_i_qp = DEFAULT_I_QP;
2326 ps_cfg->u4_p_qp = DEFAULT_P_QP;
2327 ps_cfg->u4_b_qp = DEFAULT_B_QP;
2328 ps_cfg->u4_i_qp_min = DEFAULT_QP_MIN;
2329 ps_cfg->u4_i_qp_max = DEFAULT_QP_MAX;
2330 ps_cfg->u4_p_qp_min = DEFAULT_QP_MIN;
2331 ps_cfg->u4_p_qp_max = DEFAULT_QP_MAX;
2332 ps_cfg->u4_b_qp_min = DEFAULT_QP_MIN;
2333 ps_cfg->u4_b_qp_max = DEFAULT_QP_MAX;
2334 ps_cfg->e_air_mode = DEFAULT_AIR_MODE;
2335 ps_cfg->u4_air_refresh_period = DEFAULT_AIR_REFRESH_PERIOD;
2336 ps_cfg->u4_vbv_buffer_delay = DEFAULT_VBV_DELAY;
2337 ps_cfg->u4_vbv_buf_size = DEFAULT_VBV_SIZE;
2338 ps_cfg->u4_num_cores = DEFAULT_NUM_CORES;
2339 ps_cfg->u4_me_speed_preset = DEFAULT_ME_SPEED_PRESET;
2340 ps_cfg->u4_enable_hpel = DEFAULT_HPEL;
2341 ps_cfg->u4_enable_qpel = DEFAULT_QPEL;
2342 ps_cfg->u4_enable_intra_4x4 = DEFAULT_I4;
2343 ps_cfg->u4_enable_intra_8x8 = DEFAULT_I8;
2344 ps_cfg->u4_enable_intra_16x16 = DEFAULT_I16;
2345 ps_cfg->u4_enable_fast_sad = DEFAULT_ENABLE_FAST_SAD;
2346 ps_cfg->u4_enable_satqd = DEFAULT_ENABLE_SATQD;
2347 ps_cfg->i4_min_sad =
2348 (ps_cfg->u4_enable_satqd == DEFAULT_ENABLE_SATQD) ?
2349 DEFAULT_MIN_SAD_ENABLE :
2350 DEFAULT_MIN_SAD_DISABLE;
2351 ps_cfg->u4_srch_rng_x = DEFAULT_SRCH_RNG_X;
2352 ps_cfg->u4_srch_rng_y = DEFAULT_SRCH_RNG_Y;
2353 ps_cfg->u4_i_frm_interval = DEFAULT_I_INTERVAL;
2354 ps_cfg->u4_idr_frm_interval = DEFAULT_IDR_INTERVAL;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2355 ps_cfg->u4_disable_deblock_level = DEFAULT_DISABLE_DEBLK_LEVEL;
2356 ps_cfg->e_profile = DEFAULT_PROFILE;
2357 ps_cfg->u4_timestamp_low = 0;
2358 ps_cfg->u4_timestamp_high = 0;
2359 ps_cfg->u4_is_valid = 1;
2360 ps_cfg->e_cmd = IVE_CMD_CT_NA;
2361 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
2362 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
2363 ps_cfg->u4_entropy_coding_mode = CAVLC;
2364 ps_cfg->u4_weighted_prediction = 0;
2365 ps_cfg->u4_constrained_intra_pred = 0;
2366 ps_cfg->u4_pic_info_type = 0;
2367 ps_cfg->u4_mb_info_type = 0;
2368
2369 return ret;
2370}
2371
2372/**
2373*******************************************************************************
2374*
2375* @brief
2376* Initialize encoder context. This will be called by init_mem_rec and during
2377* codec reset
2378*
2379* @par Description:
2380* Initializes the context
2381*
2382* @param[in] ps_codec
2383* Codec context pointer
2384*
2385* @returns error status
2386*
2387* @remarks none
2388*
2389*******************************************************************************
2390*/
2391static WORD32 ih264e_init(codec_t *ps_codec)
2392{
2393 /* enc config param set */
2394 cfg_params_t *ps_cfg = &(ps_codec->s_cfg);
2395
2396 /* temp var */
2397 WORD32 i;
2398
2399 /* coded pic count */
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]2400 ps_codec->i4_poc = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2401
2402 /* Number of API calls to encode are made */
2403 ps_codec->i4_encode_api_call_cnt = -1;
2404
2405 /* Indicates no header has been generated yet */
2406 ps_codec->u4_header_generated = 0;
2407
2408 /* Number of pictures encoded */
2409 ps_codec->i4_pic_cnt = -1;
2410
2411 /* Number of threads created */
2412 ps_codec->i4_proc_thread_cnt = 0;
2413
2414 /* ctl mutex init */
2415 ithread_mutex_init(ps_codec->pv_ctl_mutex);
2416
2417 /* Set encoder chroma format */
2418 ps_codec->e_codec_color_format =
2419 (ps_cfg->e_inp_color_fmt == IV_YUV_420SP_VU) ?
2420 IV_YUV_420SP_VU : IV_YUV_420SP_UV;
2421
2422 /* Number of continuous frames where deblocking was disabled */
2423 ps_codec->i4_disable_deblk_pic_cnt = 0;
2424
2425 /* frame num */
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]2426 ps_codec->i4_frame_num = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2427
2428 /* set the current frame type to I frame, since we are going to start encoding*/
2429 ps_codec->force_curr_frame_type = IV_NA_FRAME;
2430
2431 /* idr_pic_id */
2432 ps_codec->i4_idr_pic_id = -1;
2433
2434 /* Flush mode */
2435 ps_codec->i4_flush_mode = 0;
2436
2437 /* Encode header mode */
2438 ps_codec->i4_header_mode = 0;
2439
2440 /* Encode generate header */
2441 ps_codec->i4_gen_header = 0;
2442
2443 /* To signal successful completion of init */
2444 ps_codec->i4_init_done = 1;
2445
2446 /* To signal that at least one picture was decoded */
2447 ps_codec->i4_first_pic_done = 0;
2448
2449 /* Reset Codec */
2450 ps_codec->i4_reset_flag = 0;
2451
2452 /* Current error code */
2453 ps_codec->i4_error_code = IH264E_SUCCESS;
2454
2455 /* threshold residue */
2456 ps_codec->u4_thres_resi = 1;
2457
2458 /* inter gating enable */
2459 ps_codec->u4_inter_gate = 0;
2460
2461 /* entropy mutex init */
2462 ithread_mutex_init(ps_codec->pv_entropy_mutex);
2463
2464 /* sps id */
2465 ps_codec->i4_sps_id = 0;
2466
2467 /* sps id */
2468 ps_codec->i4_pps_id = 0;
2469
2470 /* Process thread created status */
2471 memset(ps_codec->ai4_process_thread_created, 0, MAX_PROCESS_THREADS);
2472
2473 /* Number of MBs processed together */
2474 ps_codec->i4_proc_nmb = 8;
2475
2476 /* Previous POC msb */
2477 ps_codec->i4_prev_poc_msb = 0;
2478
2479 /* Previous POC lsb */
2480 ps_codec->i4_prev_poc_lsb = -1;
2481
2482 /* max Previous POC lsb */
2483 ps_codec->i4_max_prev_poc_lsb = -1;
2484
2485 /* sps, pps status */
2486 {
2487 sps_t *ps_sps = ps_codec->ps_sps_base;
2488 pps_t *ps_pps = ps_codec->ps_pps_base;
2489
2490 for (i = 0; i < MAX_SPS_CNT; i++)
2491 {
2492 ps_sps->i1_sps_valid = 0;
2493 ps_sps++;
2494 }
2495
2496 for (i = 0; i < MAX_PPS_CNT; i++)
2497 {
2498 ps_pps->i1_pps_valid = 0;
2499 ps_pps++;
2500 }
2501 }
2502
2503 {
2504 WORD32 max_mb_rows = ps_cfg->i4_ht_mbs;
2505
2506 WORD32 num_jobs = max_mb_rows * 2;
2507 WORD32 clz;
2508
2509 /* Use next power of two number of entries*/
2510 clz = CLZ(num_jobs);
2511 num_jobs = 1 << (32 - clz);
2512
2513 /* init process jobq */
2514 ps_codec->pv_proc_jobq = ih264_list_init(
2515 ps_codec->pv_proc_jobq_buf,
2516 ps_codec->i4_proc_jobq_buf_size, num_jobs,
2517 sizeof(job_t), 10);
2518 RETURN_IF((ps_codec->pv_proc_jobq == NULL), IV_FAIL);
2519 ih264_list_reset(ps_codec->pv_proc_jobq);
2520
2521 /* init entropy jobq */
2522 ps_codec->pv_entropy_jobq = ih264_list_init(
2523 ps_codec->pv_entropy_jobq_buf,
2524 ps_codec->i4_entropy_jobq_buf_size, num_jobs,
2525 sizeof(job_t), 10);
2526 RETURN_IF((ps_codec->pv_entropy_jobq == NULL), IV_FAIL);
2527 ih264_list_reset(ps_codec->pv_entropy_jobq);
2528 }
2529
2530 /* Update the jobq context to all the threads */
2531 for (i = 0; i < MAX_PROCESS_CTXT; i++)
2532 {
2533 ps_codec->as_process[i].pv_proc_jobq = ps_codec->pv_proc_jobq;
2534 ps_codec->as_process[i].pv_entropy_jobq = ps_codec->pv_entropy_jobq;
2535
2536 /* i4_id always stays between 0 and MAX_PROCESS_THREADS */
2537 ps_codec->as_process[i].i4_id =
2538 (i >= MAX_PROCESS_THREADS) ?
2539 (i - MAX_PROCESS_THREADS) : i;
2540 ps_codec->as_process[i].ps_codec = ps_codec;
2541
2542 ps_codec->as_process[i].s_entropy.pv_proc_jobq = ps_codec->pv_proc_jobq;
2543 ps_codec->as_process[i].s_entropy.pv_entropy_jobq =
2544 ps_codec->pv_entropy_jobq;
2545 ps_codec->as_process[i].s_entropy.i4_abs_pic_order_cnt = -1;
2546 }
2547
2548 /* Initialize MV Bank buffer manager */
2549 ps_codec->pv_mv_buf_mgr = ih264_buf_mgr_init(ps_codec->pv_mv_buf_mgr_base);
2550
2551 /* Initialize Picture buffer manager for reference buffers*/
2552 ps_codec->pv_ref_buf_mgr = ih264_buf_mgr_init(
2553 ps_codec->pv_ref_buf_mgr_base);
2554
2555 /* Initialize Picture buffer manager for input buffers*/
2556 ps_codec->pv_inp_buf_mgr = ih264_buf_mgr_init(
2557 ps_codec->pv_inp_buf_mgr_base);
2558
2559 /* Initialize buffer manager for output buffers*/
2560 ps_codec->pv_out_buf_mgr = ih264_buf_mgr_init(
2561 ps_codec->pv_out_buf_mgr_base);
2562
2563 /* buffer cnt in buffer manager */
2564 ps_codec->i4_inp_buf_cnt = 0;
2565 ps_codec->i4_out_buf_cnt = 0;
2566 ps_codec->i4_ref_buf_cnt = 0;
2567
2568 ps_codec->ps_pic_buf = (pic_buf_t *) ps_codec->pv_pic_buf_base;
2569 memset(ps_codec->ps_pic_buf, 0, BUF_MGR_MAX_CNT * sizeof(pic_buf_t));
2570
2571 /* Initialize dpb manager */
2572 ih264_dpb_mgr_init((dpb_mgr_t*) ps_codec->pv_dpb_mgr);
2573
2574 memset(ps_codec->as_ref_set, 0,
2575 sizeof(ref_set_t) * (MAX_DPB_SIZE + MAX_CTXT_SETS));
2576 for (i = 0; i < (MAX_DPB_SIZE + MAX_CTXT_SETS); i++)
2577 {
2578 ps_codec->as_ref_set[i].i4_pic_cnt = -1;
2579 }
2580
2581 /* fn ptr init */
2582 ih264e_init_function_ptr(ps_codec);
2583
2584 /* reset status flags */
2585 for (i = 0; i < MAX_CTXT_SETS; i++)
2586 {
2587 ps_codec->au4_entropy_thread_active[i] = 0;
2588 ps_codec->ai4_pic_cnt[i] = -1;
2589
2590 ps_codec->s_rate_control.pre_encode_skip[i] = 0;
2591 ps_codec->s_rate_control.post_encode_skip[i] = 0;
2592 }
2593
2594 ps_codec->s_rate_control.num_intra_in_prev_frame = 0;
2595 ps_codec->s_rate_control.i4_avg_activity = 0;
2596
2597 return IV_SUCCESS;
2598}
2599
2600/**
2601*******************************************************************************
2602*
2603* @brief
2604* Gets number of memory records required by the codec
2605*
2606* @par Description:
2607* Gets codec memory requirements
2608*
2609* @param[in] pv_api_ip
2610* Pointer to input argument structure
2611*
2612* @param[out] pv_api_op
2613* Pointer to output argument structure
2614*
2615* @returns status
2616*
2617* @remarks
2618*
2619*******************************************************************************
2620*/
2621static WORD32 ih264e_get_num_rec(void *pv_api_ip, void *pv_api_op)
2622{
2623 UNUSED(pv_api_ip);
2624 /* api call I/O structures */
2625 ih264e_num_mem_rec_op_t *ps_op = pv_api_op;
2626
2627 ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT;
2628
2629 return IV_SUCCESS;
2630}
2631
2632/**
2633*******************************************************************************
2634*
2635* @brief
2636* Fills memory records of the codec
2637*
2638* @par Description:
2639* Fills codec memory requirements
2640*
2641* @param[in] pv_api_ip
2642* Pointer to input argument structure
2643*
2644* @param[out] pv_api_op
2645* Pointer to output argument structure
2646*
2647* @returns error status
2648*
2649* @remarks none
2650*
2651*******************************************************************************
2652*/
2653static WORD32 ih264e_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op)
2654{
2655 /* api call I/O structures */
2656 ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip;
2657 ih264e_fill_mem_rec_op_t *ps_op = pv_api_op;
2658
2659 /* profile / level info */
2660 WORD32 level;
2661 WORD32 num_reorder_frames;
2662 WORD32 num_ref_frames;
2663
2664 /* mem records */
2665 WORD32 no_of_mem_rec;
2666 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
2667
2668 /* frame dimensions */
2669 WORD32 max_wd_luma, max_ht_luma;
2670 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
2671
2672 /* temp var */
2673 WORD32 i;
2674
2675 /* error status */
2676 IV_STATUS_T status = IV_SUCCESS;
2677
2678 /* profile / level info */
2679 level = ps_ip->s_ive_ip.u4_max_level;
2680 num_reorder_frames = ps_ip->s_ive_ip.u4_max_reorder_cnt;
2681 num_ref_frames = ps_ip->s_ive_ip.u4_max_ref_cnt;
2682
2683 /* mem records */
2684 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
2685 no_of_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec;
2686
2687 /* frame dimensions */
2688 max_ht_luma = ps_ip->s_ive_ip.u4_max_ht;
2689 max_wd_luma = ps_ip->s_ive_ip.u4_max_wd;
2690 max_ht_luma = ALIGN16(max_ht_luma);
2691 max_wd_luma = ALIGN16(max_wd_luma);
2692 max_mb_rows = max_ht_luma / MB_SIZE;
2693 max_mb_cols = max_wd_luma / MB_SIZE;
2694 max_mb_cnt = max_mb_rows * max_mb_cols;
2695
2696 /* validate params */
2697 if ((level < MIN_LEVEL) || (level > MAX_LEVEL))
2698 {
2699 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
2700 level = MAX_LEVEL;
2701 }
2702
2703 if (num_ref_frames > MAX_REF_CNT)
2704 {
2705 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
2706 num_ref_frames = MAX_REF_CNT;
2707 }
2708
2709 if (num_reorder_frames > MAX_REF_CNT)
2710 {
2711 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
2712 num_reorder_frames = MAX_REF_CNT;
2713 }
2714
2715 /* Set all memory records as persistent and alignment as 128 by default */
2716 ps_mem_rec = ps_mem_rec_base;
2717 for (i = 0; i < no_of_mem_rec; i++)
2718 {
2719 ps_mem_rec->u4_mem_alignment = 128;
2720 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2721 ps_mem_rec++;
2722 }
2723
2724 /************************************************************************
2725 * Request memory for h264 encoder handle *
2726 ***********************************************************************/
2727 ps_mem_rec = &ps_mem_rec_base[MEM_REC_IV_OBJ];
2728 {
2729 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
2730 }
2731 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_IV_OBJ, ps_mem_rec->u4_mem_size);
2732
2733 /************************************************************************
2734 * Request memory for h264 encoder context *
2735 ***********************************************************************/
2736 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC];
2737 {
2738 ps_mem_rec->u4_mem_size = sizeof(codec_t);
2739 }
2740 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CODEC, ps_mem_rec->u4_mem_size);
2741
2742 /************************************************************************
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]2743 * Request memory for CABAC context *
2744 ***********************************************************************/
2745 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC];
2746 {
2747 ps_mem_rec->u4_mem_size = sizeof(cabac_ctxt_t);
2748 }
2749 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC, ps_mem_rec->u4_mem_size);
2750
2751 /************************************************************************
2752 * Request memory for CABAC MB info *
2753 ***********************************************************************/
2754 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO];
2755 {
2756 ps_mem_rec->u4_mem_size = ((max_mb_cols + 1) + 1)
2757 * sizeof(mb_info_ctxt_t);
2758 }
2759 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC_MB_INFO, ps_mem_rec->u4_mem_size);
2760
2761
2762 /************************************************************************
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2763 * Request memory for entropy context *
2764 * In multi core encoding, each row is assumed to be launched on a *
2765 * thread. The rows below can only start after its neighbors are coded *
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]2766 * The status of an mb coded/uncoded is signaled via entropy map. *
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2767 * 1. One word32 to store skip run cnt *
2768 * 2. mb entropy map (mb status entropy coded/uncoded). The size*
2769 * of the entropy map is max mb cols. Further allocate one *
2770 * more additional row to evade checking for row -1. *
2771 * 3. size of bit stream buffer to store bit stream ctxt. *
2772 * 4. Entropy coding is dependent on nnz coefficient count for *
2773 * the neighbor blocks. It is sufficient to maintain one row *
2774 * worth of nnz as entropy for lower row waits on entropy map*
2775 ************************************************************************/
2776 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY];
2777 {
2778 /* total size of the mem record */
2779 WORD32 total_size = 0;
2780
2781 /* size of skip mb run */
2782 total_size += sizeof(WORD32);
2783 total_size = ALIGN8(total_size);
2784
2785 /* size in bytes to store entropy status of an entire frame */
2786 total_size += (max_mb_cols * max_mb_rows);
2787 /* add an additional 1 row of bytes to evade the special case of row 0 */
2788 total_size += max_mb_cols;
2789 total_size = ALIGN128(total_size);
2790
2791 /* size of bit stream buffer */
2792 total_size += sizeof(bitstrm_t);
2793 total_size = ALIGN128(total_size);
2794
2795 /* top nnz luma */
2796 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
2797 total_size = ALIGN128(total_size);
2798
2799 /* top nnz cbcr */
2800 total_size += (max_mb_cols * 4 * sizeof(UWORD8));
2801 total_size = ALIGN128(total_size);
2802
2803 /* total size per each proc ctxt */
2804 total_size *= MAX_CTXT_SETS;
2805
2806 ps_mem_rec->u4_mem_size = total_size;
2807 }
2808 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY, ps_mem_rec->u4_mem_size);
2809
2810 /************************************************************************
2811 * The residue coefficients that needs to be entropy coded are packed *
2812 * at a buffer space by the proc threads. The entropy thread shall *
2813 * read from the buffer space, unpack them and encode the same. The *
2814 * buffer space required to pack a row of mbs are as follows. *
2815 * Assuming transform_8x8_flag is disabled, *
2816 * In the worst case, 1 mb contains 1 dc 4x4 luma sub block, followed *
2817 * by 16 ac 4x4 luma sub blocks, 2 dc chroma 2x2 sub blocks, followed *
2818 * by 8 ac 4x4 chroma sub blocks. *
2819 * For the sake of simplicity we assume that all sub blocks are of *
2820 * type 4x4. The packing of each 4x4 is depicted by the structure *
2821 * tu_sblk_coeff_data_t *
2822 ************************************************************************/
2823 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA];
2824 {
2825 /* temp var */
2826 WORD32 size = 0;
2827
2828 /* size of coeff data of 1 mb */
2829 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
2830
2831 /* size of coeff data of 1 row of mb's */
2832 size *= max_mb_cols;
2833
2834 /* align to avoid any false sharing across threads */
2835 size = ALIGN64(size);
2836
2837 /* size for one full frame */
2838 size *= max_mb_rows;
2839
2840 /* size of each proc buffer set (ping, pong) */
2841 size *= MAX_CTXT_SETS;
2842
2843 ps_mem_rec->u4_mem_size = size;
2844 }
2845 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_COEFF_DATA, ps_mem_rec->u4_mem_size);
2846
2847 /************************************************************************
2848 * while encoding an mb, the mb header data is signaled to the entropy*
2849 * thread by writing to a buffer space. the size of header data per mb *
2850 * is assumed to be 40 bytes *
2851 * TODO: revisit this inference *
2852 ************************************************************************/
2853 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA];
2854 {
2855 /* temp var */
2856 WORD32 size;
2857
2858 /* size per MB */
2859 size = 40;
2860
2861 /* size for 1 row of mbs */
2862 size = size * max_mb_cols;
2863
2864 /* align to avoid any false sharing across threads */
2865 size = ALIGN64(size);
2866
2867 /* size for one full frame */
2868 size *= max_mb_rows;
2869
2870 /* size of each proc buffer set (ping, pong) */
2871 size *= MAX_CTXT_SETS;
2872
2873 ps_mem_rec->u4_mem_size = size;
2874 }
2875 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_HEADER_DATA, ps_mem_rec->u4_mem_size);
2876
2877 /************************************************************************
2878 * Size for holding mv_buf_t for each MV Bank. *
2879 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
2880 * MAX_DPB_SIZE or max_dpb_size for following reasons *
2881 * max_dpb_size will be based on max_wd and max_ht *
2882 * For higher max_wd and max_ht this number will be smaller than *
2883 * MAX_DPB_SIZE But during actual initialization number of buffers *
2884 * allocated can be more. *
2885 * *
2886 * One extra MV Bank is needed to hold current pics MV bank. *
2887 * Since this is only a structure allocation and not actual buffer *
2888 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
2889 ************************************************************************/
2890 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK];
2891 {
2892 /* max luma samples */
2893 WORD32 max_luma_samples = 0;
2894
2895 /* determine max luma samples */
2896 for (i = 0; i < 16; i++)
2897 if (level ==(WORD32)gas_ih264_lvl_tbl[i].u4_level_idc)
2898 max_luma_samples = gas_ih264_lvl_tbl[i].u4_max_fs
2899 << (BLK_SIZE + BLK_SIZE);
2900
2901 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
2902
2903 /************************************************************************
2904 * Allocate for pu_map, enc_pu_t and pic_pu_idx for each MV bank *
2905 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
2906 * is set to maximum number of luma samples allowed at the given level. *
2907 * This is done to ensure that any stream with width and height lesser *
2908 * than max_wd and max_ht is supported. Number of buffers required can *
2909 * be greater for lower width and heights at a given level and this *
2910 * increased number of buffers might require more memory than what *
2911 * max_wd and max_ht buffer would have required Also note one extra *
2912 * buffer is allocated to store current pictures MV bank. *
2913 ***********************************************************************/
2914
2915 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(mv_buf_t);
2916
2917 ps_mem_rec->u4_mem_size += (num_ref_frames + num_reorder_frames
2918 + MAX_CTXT_SETS)
2919 * ih264e_get_pic_mv_bank_size(max_luma_samples);
2920 }
2921 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBANK, ps_mem_rec->u4_mem_size);
2922
2923 /************************************************************************
2924 * While encoding inter slices, to compute the cost of encoding an mb *
2925 * with the mv's at hand, we employ the expression cost = sad + lambda *
2926 * x mv_bits. Here mv_bits is the total number of bits taken to represe*
2927 * nt the mv in the stream. The mv bits for all the possible mv are *
2928 * stored in the look up table. The mem record for this look up table *
2929 * is given below. *
2930 ************************************************************************/
2931 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS];
2932 {
2933 /* max srch range x */
2934 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
2935
2936 /* max srch range y */
2937 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
2938
2939 /* max srch range */
2940 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
2941
2942 /* due to subpel */
2943 u4_max_srch_range <<= 2;
2944
2945 /* due to mv on either direction */
2946 u4_max_srch_range = (u4_max_srch_range << 1);
2947
2948 /* due to pred mv + zero */
2949 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
2950
2951 u4_max_srch_range = ALIGN128(u4_max_srch_range);
2952
2953 ps_mem_rec->u4_mem_size = u4_max_srch_range;
2954 }
2955 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBITS, ps_mem_rec->u4_mem_size);
2956
2957 /************************************************************************
2958 * Request memory for SPS *
2959 ***********************************************************************/
2960 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS];
2961 {
2962 ps_mem_rec->u4_mem_size = MAX_SPS_CNT * sizeof(sps_t);
2963 }
2964 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SPS, ps_mem_rec->u4_mem_size);
2965
2966 /************************************************************************
2967 * Request memory for PPS *
2968 ***********************************************************************/
2969 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS];
2970 {
2971 ps_mem_rec->u4_mem_size = MAX_PPS_CNT * sizeof(pps_t);
2972 }
2973 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PPS, ps_mem_rec->u4_mem_size);
2974
2975 /************************************************************************
2976 * Request memory for Slice Header *
2977 ***********************************************************************/
2978 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR];
2979 {
2980 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS * MAX_SLICE_HDR_CNT
2981 * sizeof(slice_header_t);
2982 }
2983 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_HDR, ps_mem_rec->u4_mem_size);
2984
2985 /************************************************************************
2986 * Request memory for Adaptive Intra Refresh *
2987 ***********************************************************************/
2988 ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP];
2989 {
2990 /* total size of the mem record */
2991 WORD32 total_size = 0;
2992
2993 /* intra coded map */
2994 total_size += max_mb_cnt;
2995 total_size *= MAX_CTXT_SETS;
2996
2997 /* mb refresh map */
2998 total_size += sizeof(UWORD16) * max_mb_cnt;
2999
3000 /* alignment */
3001 total_size = ALIGN128(total_size);
3002
3003 ps_mem_rec->u4_mem_size = total_size;
3004 }
3005 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_AIR_MAP, ps_mem_rec->u4_mem_size);
3006
3007 /************************************************************************
3008 * In multi slice encoding, this memory record helps tracking the start*
3009 * of slice with reference to mb. *
3010 * MEM RECORD for holding *
3011 * 1. mb slice map *
3012 ************************************************************************/
3013 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP];
3014 {
3015 /* total size of the mem record */
3016 WORD32 total_size = 0;
3017
3018 /* size in bytes to slice index of all mbs of a frame */
3019 total_size = ALIGN64(max_mb_cnt);
3020
Martin Storsjofc508f22015-05-24 01:26:35 +0300[diff] [blame]3021 /* ih264e_update_proc_ctxt can overread by 1 at the end */
3022 total_size += 1;
3023
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3024 /* total size per each proc ctxt */
3025 total_size *= MAX_CTXT_SETS;
3026 ps_mem_rec->u4_mem_size = total_size;
3027 }
3028 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_MAP, ps_mem_rec->u4_mem_size);
3029
3030 /************************************************************************
3031 * Request memory to hold thread handles for each processing thread *
3032 ************************************************************************/
3033 ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE];
3034 {
3035 WORD32 handle_size = ithread_get_handle_size();
3036
3037 ps_mem_rec->u4_mem_size = MAX_PROCESS_THREADS * handle_size;
3038 }
3039 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_THREAD_HANDLE, ps_mem_rec->u4_mem_size);
3040
3041 /************************************************************************
3042 * Request memory to hold mutex for control calls *
3043 ************************************************************************/
3044 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX];
3045 {
3046 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
3047 }
3048 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CTL_MUTEX, ps_mem_rec->u4_mem_size);
3049
3050 /************************************************************************
3051 * Request memory to hold mutex for entropy calls *
3052 ************************************************************************/
3053 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX];
3054 {
3055 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size();
3056 }
3057 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_MUTEX, ps_mem_rec->u4_mem_size);
3058
3059 /************************************************************************
3060 * Request memory to hold process jobs *
3061 ***********************************************************************/
3062 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ];
3063 {
3064 /* One process job per row of MBs */
3065 /* Allocate for two pictures, so that wrap around can be handled easily */
3066 WORD32 num_jobs = max_mb_rows * 2;
3067
3068 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
3069
3070 ps_mem_rec->u4_mem_size = job_queue_size;
3071 }
3072 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_JOBQ, ps_mem_rec->u4_mem_size);
3073
3074 /************************************************************************
3075 * Request memory to hold entropy jobs *
3076 ***********************************************************************/
3077 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ];
3078 {
3079 /* One process job per row of MBs */
3080 /* Allocate for two pictures, so that wrap around can be handled easily */
3081 WORD32 num_jobs = max_mb_rows * 2;
3082
3083 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t));
3084
3085 ps_mem_rec->u4_mem_size = job_queue_size;
3086 }
3087 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_JOBQ, ps_mem_rec->u4_mem_size);
3088
3089 /************************************************************************
3090 * In multi core encoding, each row is assumed to be launched on a *
3091 * thread. The rows below can only start after its neighbors are coded *
3092 * The status of an mb coded/uncoded is signaled via proc map. *
3093 * MEM RECORD for holding *
3094 * 1. mb proc map (mb status core coded/uncoded) *
3095 ************************************************************************/
3096 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP];
3097 {
3098 /* total size of the mem record */
3099 WORD32 total_size = 0;
3100
3101 /* size in bytes to mb core coding status of an entire frame */
3102 total_size = max_mb_cnt;
3103
3104 /* add an additional 1 row of bytes to evade the special case of row 0 */
3105 total_size += max_mb_cols;
3106
3107 /* total size per each proc ctxt */
3108 total_size *= MAX_CTXT_SETS;
3109 ps_mem_rec->u4_mem_size = total_size;
3110 }
3111 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_MAP, ps_mem_rec->u4_mem_size);
3112
3113 /************************************************************************
3114 * mem record for holding a particular MB is deblocked or not *
3115 * 1. mb deblk map (mb status deblocked/not deblocked) *
3116 ************************************************************************/
3117 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP];
3118 {
3119 /* total size of the mem record */
3120 WORD32 total_size = 0;
3121
3122 /* size in bytes to mb core coding status of an entire frame */
3123 total_size = max_mb_cnt;
3124
3125 /* add an additional 1 row of bytes to evade the special case of row 0 */
3126 total_size += max_mb_cols;
3127
3128 total_size = ALIGN64(total_size);
3129
3130 /* total size per each proc ctxt */
3131 total_size *= MAX_CTXT_SETS;
3132 ps_mem_rec->u4_mem_size = total_size;
3133 }
3134 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DBLK_MAP, ps_mem_rec->u4_mem_size);
3135
3136 /************************************************************************
3137 * mem record for holding a particular MB's me is done or not *
3138 * 1. mb me map *
3139 ************************************************************************/
3140 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP];
3141 {
3142 /* total size of the mem record */
3143 WORD32 total_size = 0;
3144
3145 /* size in bytes to mb core coding status of an entire frame */
3146 total_size = max_mb_cnt;
3147
3148 /* add an additional 1 row of bytes to evade the special case of row 0 */
3149 total_size += max_mb_cols;
3150
3151 /* total size per each proc ctxt */
3152 total_size *= MAX_CTXT_SETS;
3153
3154 ps_mem_rec->u4_mem_size = total_size;
3155 }
3156 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ME_MAP, ps_mem_rec->u4_mem_size);
3157
3158 /************************************************************************
3159 * size for holding dpb manager context *
3160 ************************************************************************/
3161 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR];
3162 {
3163 ps_mem_rec->u4_mem_size = sizeof(dpb_mgr_t);
3164 }
3165 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DPB_MGR, ps_mem_rec->u4_mem_size);
3166
3167 /************************************************************************
3168 * luma or chroma core coding involves mb estimation, error computation*
3169 * between the estimated singnal and the actual signal, transform the *
3170 * error, quantize the error, then inverse transform and inverse quant *
3171 * ize the residue and add the result back to estimated signal. *
3172 * To perform all these, a set of temporary buffers are needed. *
3173 * MEM RECORD for holding scratch buffers *
3174 * 1. prediction buffer used during mb mode analysis *
3175 * 2 temp. reference buffer when intra 4x4 with rdopt on is *
3176 * enabled *
3177 * - when intra 4x4 is enabled, rdopt is on, to store the *
3178 * reconstructed values and use them later this temp. buffer *
3179 * is used. *
3180 * 3. prediction buffer used during intra mode analysis *
3181 * 4. prediction buffer used during intra 16x16 plane mode *
3182 * analysis
3183 * 5. prediction buffer used during intra chroma mode analysis *
3184 * 6. prediction buffer used during intra chroma 16x16 plane *
3185 * mode analysis
3186 * 7. forward transform output buffer *
3187 * - to store the error between estimated and the actual inp *
3188 * ut and to store the fwd transformed quantized output *
3189 * 8. forward transform output buffer *
3190 * - when intra 4x4 is enabled, rdopt is on, to store the *
3191 * fwd transform values and use them later this temp. buffer *
3192 * is used. *
3193 * 9. temporary buffer for inverse transform *
3194 * - temporary buffer used in inverse transform and inverse *
3195 * quantization *
3196 * A. Buffers for holding half_x , half_y and half_xy planes *
3197 ************************************************************************/
3198 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH];
3199 {
3200 WORD32 total_size = 0;
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]3201 WORD32 i4_tmp_size;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3202
3203 /* size to hold prediction buffer */
3204 total_size += sizeof(UWORD8) * 16 * 16;
3205 total_size = ALIGN64(total_size);
3206
3207 /* size to hold recon for intra 4x4 buffer */
3208 total_size += sizeof(UWORD8) * 16 * 16;
3209 total_size = ALIGN64(total_size);
3210
3211 /* prediction buffer intra 16x16 */
3212 total_size += sizeof(UWORD8) * 16 * 16;
3213 total_size = ALIGN64(total_size);
3214
3215 /* prediction buffer intra 16x16 plane*/
3216 total_size += sizeof(UWORD8) * 16 * 16;
3217 total_size = ALIGN64(total_size);
3218
3219 /* prediction buffer intra chroma*/
3220 total_size += sizeof(UWORD8) * 16 * 8;
3221 total_size = ALIGN64(total_size);
3222
3223 /* prediction buffer intra chroma plane*/
3224 total_size += sizeof(UWORD8) * 16 * 8;
3225 total_size = ALIGN64(total_size);
3226
3227 /* size to hold fwd transform output */
3228 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
3229 total_size = ALIGN64(total_size);
3230
3231 /* size to hold fwd transform output */
3232 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF;
3233 total_size = ALIGN64(total_size);
3234
3235 /* size to hold temporary data during inverse transform */
3236 total_size += sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
3237 total_size = ALIGN64(total_size);
3238
3239 /* Buffers for holding half_x , half_y and half_xy planes */
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]3240 i4_tmp_size = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
3241 total_size += (ALIGN64(i4_tmp_size) * SUBPEL_BUFF_CNT);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3242
3243 /* Allocate for each process thread */
3244 total_size *= MAX_PROCESS_CTXT;
3245
3246 ps_mem_rec->u4_mem_size = total_size;
3247 }
3248 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_SCRATCH, ps_mem_rec->u4_mem_size);
3249
3250 /************************************************************************
3251 * When transform_8x8_flag is disabled, the size of a sub block is *
3252 * 4x4 and when the transform_8x8_flag is enabled the size of the sub *
3253 * block is 8x8. The threshold matrix and the forward scaling list *
3254 * is of the size of the sub block. *
3255 * MEM RECORD for holding *
3256 * 1. quantization parameters for plane y, cb, cr *
3257 * - threshold matrix for quantization *
3258 * - forward weight matrix *
3259 * - satqd threshold matrix *
3260 ************************************************************************/
3261 ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM];
3262 {
3263 /* total size of the mem record */
3264 WORD32 total_size = 0;
3265
3266 /* quantization parameter list for planes y,cb and cr */
3267 total_size += ALIGN64(sizeof(quant_params_t)) * 3;
3268
3269 /* size of threshold matrix for quantization
3270 * (assuming the transform_8x8_flag is disabled).
3271 * for all 3 planes */
3272 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
3273
3274 /* size of forward weight matrix for quantization
3275 * (assuming the transform_8x8_flag is disabled).
3276 * for all 3 planes */
3277 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3;
3278
3279 /* Size for SATDQ threshold matrix for palnes y, cb and cr */
3280 total_size += ALIGN64(sizeof(UWORD16) * 9) * 3;
3281
3282 /* total size per each proc thread */
3283 total_size *= MAX_PROCESS_CTXT;
3284
3285 ps_mem_rec->u4_mem_size = total_size;
3286 }
3287 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_QUANT_PARAM, ps_mem_rec->u4_mem_size);
3288
3289 /************************************************************************
3290 * While computing blocking strength for the current mb, the csbp, mb *
3291 * type for the neighboring mbs are necessary. memtab for storing top *
3292 * row mbtype and csbp is evaluated here. *
3293 * *
3294 * when encoding intra 4x4 or intra 8x8 the submb types are estimated *
3295 * and sent. The estimation is dependent on neighbor mbs. For this *
3296 * store the top row sub mb types for intra mbs *
3297 * *
3298 * During motion vector prediction, the curr mb mv is predicted from *
3299 * neigbors left, top, top right and sometimes top left depending on *
3300 * the availability. The top and top right content is accessed from *
3301 * the memtab specified below. *
3302 ************************************************************************/
3303 ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO];
3304 {
3305 /* total size of the mem record */
3306 WORD32 total_size = 0;
3307
3308 /* size in bytes to store 1 row of mb_info_t */
3309 /* one additional mb, to avoid checking end of row condition */
3310 total_size += (max_mb_cols + 1) * sizeof(mb_info_t);
3311
3312 /* size in bytes to store 1 row of intra macroblock sub modes */
3313 total_size += max_mb_cols * sizeof(UWORD8) * 16;
3314
3315 /* size in bytes to store 1 row + 1 of enc_pu_t */
3316 /* one additional mb, to avoid checking end of row condition */
3317 total_size += (max_mb_cols + 1) * sizeof(enc_pu_t);
3318
3319 /* total size per proc ctxt */
3320 total_size = ALIGN128(total_size);
3321
3322 /* total size per each proc ctxt */
3323 total_size *= MAX_CTXT_SETS;
3324 ps_mem_rec->u4_mem_size = total_size;
3325 }
3326 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_TOP_ROW_SYN_INFO, ps_mem_rec->u4_mem_size);
3327
3328 /************************************************************************
3329 * When transform_8x8_flag is disabled, the mb is partitioned into *
3330 * 4 sub blocks. This corresponds to 1 vertical left edge and 1 *
3331 * vertical inner edge, 1 horizontal top edge and 1 horizontal *
3332 * inner edge per mb. Further, When transform_8x8_flag is enabled, *
3333 * the mb is partitioned in to 16 sub blocks. This corresponds to *
3334 * 1 vertical left edge and 3 vertical inner edges, 1 horizontal top *
3335 * edge and 3 horizontal inner edges per mb. *
3336 * MEM RECORD for holding *
3337 * 1. vertical edge blocking strength *
3338 * 2. horizontal edge blocking strength *
3339 * 3. mb qp *
3340 * all are frame level *
3341 ************************************************************************/
3342 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP];
3343 {
3344 /* total size of the mem record */
3345 WORD32 total_size = 0;
3346
3347 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/
3348 WORD32 vert_bs_size, horz_bs_size, qp_size;
3349
3350 /* vertical edge bs = total number of vertical edges * number of bytes per each edge */
3351 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
3352 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
3353 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
3354
3355 /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */
3356 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
3357 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
3358 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
3359
3360 /* qp of each mb requires 1 byte */
3361 qp_size = ALIGN64(max_mb_cnt);
3362
3363 /* total size */
3364 total_size = vert_bs_size + horz_bs_size + qp_size;
3365
3366 /* total size per each proc ctxt */
3367 total_size *= MAX_CTXT_SETS;
3368
3369 ps_mem_rec->u4_mem_size = total_size;
3370 }
3371 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BS_QP, ps_mem_rec->u4_mem_size);
3372
3373 /************************************************************************
3374 * size for holding dpb manager context *
3375 ************************************************************************/
3376 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC];
3377 {
3378 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3379 }
3380 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_INP_PIC, ps_mem_rec->u4_mem_size);
3381
3382 /************************************************************************
3383 * size for holding dpb manager context *
3384 ************************************************************************/
3385 ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT];
3386 {
3387 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3388 }
3389 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_OUT, ps_mem_rec->u4_mem_size);
3390
3391 /************************************************************************
3392 * Size for color space conversion *
3393 ************************************************************************/
3394 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC];
3395 {
3396 /* We need a total a memory for a single frame of 420 sp, ie
3397 * (wd * ht) for luma and (wd * ht / 2) for chroma*/
3398 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS
3399 * ((3 * max_ht_luma * max_wd_luma) >> 1);
Harish Mahendrakar5cdb8882015-06-09 17:48:53 +0530[diff] [blame]3400 /* Allocate an extra row, since inverse transform functions for
3401 * chroma access(only read, not used) few extra bytes due to
3402 * interleaved input
3403 */
3404 ps_mem_rec->u4_mem_size += max_wd_luma;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3405 }
3406 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CSC, ps_mem_rec->u4_mem_size);
3407
3408 /************************************************************************
3409 * Size for holding pic_buf_t for each reference picture *
3410 * Note this allocation is done for BUF_MGR_MAX_CNT instead of *
3411 * MAX_DPB_SIZE or max_dpb_size for following reasons *
3412 * max_dpb_size will be based on max_wd and max_ht *
3413 * For higher max_wd and max_ht this number will be smaller than *
3414 * MAX_DPB_SIZE But during actual initialization number of buffers *
3415 * allocated can be more. *
3416 * *
3417 * Also to handle display depth application can allocate more than *
3418 * what codec asks for in case of non-shared mode *
3419 * Since this is only a structure allocation and not actual buffer *
3420 * allocation, it is allocated for BUF_MGR_MAX_CNT entries *
3421 ************************************************************************/
3422 ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC];
3423 {
3424 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size();
3425 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(pic_buf_t);
3426
3427 /************************************************************************
3428 * Note: Number of luma samples is not max_wd * max_ht here, instead it *
3429 * is set to maximum number of luma samples allowed at the given level. *
3430 * This is done to ensure that any stream with width and height lesser *
3431 * than max_wd and max_ht is supported. Number of buffers required can *
3432 * be greater for lower width and heights at a given level and this *
3433 * increased number of buffers might require more memory than what *
3434 * max_wd and max_ht buffer would have required. Number of buffers is *
3435 * doubled in order to return one frame at a time instead of sending *
3436 * multiple outputs during dpb full case. Also note one extra buffer is *
3437 * allocted to store current picture. *
3438 * *
3439 * Half-pel planes for each reference buffer are allocated along with *
3440 * the reference buffer. So each reference buffer is 4 times the *
3441 * required size. This way buffer management for the half-pel planes is *
3442 * easier and while using the half-pel planes in MC, an offset can be *
3443 * used from a single pointer *
3444 ***********************************************************************/
3445 ps_mem_rec->u4_mem_size += HPEL_PLANES_CNT
3446 * ih264e_get_total_pic_buf_size(
3447 max_wd_luma * max_ht_luma, level,
3448 PAD_WD, PAD_HT, num_ref_frames,
3449 num_reorder_frames);
3450 }
3451 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_REF_PIC, ps_mem_rec->u4_mem_size);
3452
3453 /************************************************************************
3454 * Request memory to hold mem recs to be returned during retrieve call *
3455 ************************************************************************/
3456 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP];
3457 {
3458 ps_mem_rec->u4_mem_size = MEM_REC_CNT * sizeof(iv_mem_rec_t);
3459 }
3460 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BACKUP, ps_mem_rec->u4_mem_size);
3461
3462 /************************************************************************
3463 * size for memory required by NMB info structs and buffer for storing *
3464 * half pel plane *
3465 ************************************************************************/
3466 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB];
3467 {
3468 ps_mem_rec->u4_mem_size = MAX_PROCESS_CTXT * MAX_NMB
3469 * (sizeof(mb_info_nmb_t)
3470 + MB_SIZE * MB_SIZE * sizeof(UWORD8));
3471 }
3472 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_INFO_NMB, ps_mem_rec->u4_mem_size);
3473
3474 /************************************************************************
3475 * RC mem records *
3476 ************************************************************************/
3477 ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC];
3478 {
3479 ih264e_get_rate_control_mem_tab(NULL, ps_mem_rec, FILL_MEMTAB);
3480 }
3481 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_RC, ps_mem_rec->u4_mem_size);
3482
3483 /* Each memtab size is aligned to next multiple of 128 bytes */
3484 /* This is to ensure all the memtabs start at different cache lines */
3485 ps_mem_rec = ps_mem_rec_base;
3486 for (i = 0; i < MEM_REC_CNT; i++)
3487 {
3488 ps_mem_rec->u4_mem_size = ALIGN128(ps_mem_rec->u4_mem_size);
3489 ps_mem_rec++;
3490 }
3491
3492 ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT;
3493
3494 DEBUG("Num mem recs in fill call : %d\n", ps_op->s_ive_op.u4_num_mem_rec);
3495
3496 return (status);
3497}
3498
3499/**
3500*******************************************************************************
3501*
3502* @brief
3503* Initializes from mem records passed to the codec
3504*
3505* @par Description:
3506* Initializes pointers based on mem records passed
3507*
3508* @param[in] ps_codec_obj
3509* Pointer to codec object at API level
3510*
3511* @param[in] pv_api_ip
3512* Pointer to input argument structure
3513*
3514* @param[out] pv_api_op
3515* Pointer to output argument structure
3516*
3517* @returns error status
3518*
3519* @remarks none
3520*
3521*******************************************************************************
3522*/
3523static WORD32 ih264e_init_mem_rec(iv_obj_t *ps_codec_obj,
3524 void *pv_api_ip,
3525 void *pv_api_op)
3526{
3527 /* api call I/O structures */
3528 ih264e_init_ip_t *ps_ip = pv_api_ip;
3529 ih264e_init_op_t *ps_op = pv_api_op;
3530
3531 /* mem records */
3532 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec;
3533
3534 /* codec variables */
3535 codec_t * ps_codec;
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]3536 cabac_ctxt_t *ps_cabac;
3537 mb_info_ctxt_t *ps_mb_map_ctxt_inc;
3538
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3539 cfg_params_t *ps_cfg;
3540
3541 /* frame dimensions */
3542 WORD32 max_wd_luma, max_ht_luma;
3543 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt;
3544
3545 /* temp var */
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]3546 WORD32 i, j;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3547 WORD32 status = IV_SUCCESS;
3548
3549 /* frame dimensions */
3550 max_ht_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
3551 max_wd_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
3552 max_mb_rows = max_ht_luma / MB_SIZE;
3553 max_mb_cols = max_wd_luma / MB_SIZE;
3554 max_mb_cnt = max_mb_rows * max_mb_cols;
3555
3556 /* mem records */
3557 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec;
3558
3559 /* Init mem records */
3560 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC];
3561 {
3562 ps_codec_obj->pv_codec_handle = ps_mem_rec->pv_base;
3563 ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle);
3564 }
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]3565 /* Init mem records_cabac ctxt */
3566 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC];
3567 {
3568 ps_cabac = (cabac_ctxt_t *)(ps_mem_rec->pv_base);
3569 }
3570
3571 /* Init mem records mb info array for CABAC */
3572 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO];
3573 {
3574 ps_mb_map_ctxt_inc = (mb_info_ctxt_t *)(ps_mem_rec->pv_base);
3575 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3576
3577 /* Note this memset can not be done in init() call, since init will called
3578 during reset as well. And calling this during reset will mean all pointers
3579 need to reinitialized */
3580 memset(ps_codec, 0, sizeof(codec_t));
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]3581 memset(ps_cabac, 0, sizeof(cabac_ctxt_t));
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3582
3583 /* Set default Config Params */
3584 ps_cfg = &ps_codec->s_cfg;
3585 ih264e_set_default_params(ps_cfg);
3586
3587 /* Update config params as per input */
3588 ps_cfg->u4_max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
3589 ps_cfg->u4_max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
3590 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4;
3591 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4;
3592 ps_cfg->u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt;
3593 ps_cfg->u4_max_reorder_cnt = ps_ip->s_ive_ip.u4_max_reorder_cnt;
3594 ps_cfg->u4_max_level = ps_ip->s_ive_ip.u4_max_level;
3595 ps_cfg->e_inp_color_fmt = ps_ip->s_ive_ip.e_inp_color_fmt;
3596 ps_cfg->e_recon_color_fmt = ps_ip->s_ive_ip.e_recon_color_fmt;
3597 ps_cfg->u4_max_framerate = ps_ip->s_ive_ip.u4_max_framerate;
3598 ps_cfg->u4_max_bitrate = ps_ip->s_ive_ip.u4_max_bitrate;
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]3599 ps_cfg->u4_num_bframes = ps_ip->s_ive_ip.u4_num_bframes;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3600 ps_cfg->e_content_type = ps_ip->s_ive_ip.e_content_type;
3601 ps_cfg->u4_max_srch_rng_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
3602 ps_cfg->u4_max_srch_rng_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
3603 ps_cfg->e_slice_mode = ps_ip->s_ive_ip.e_slice_mode;
3604 ps_cfg->u4_slice_param = ps_ip->s_ive_ip.u4_slice_param;
3605 ps_cfg->e_arch = ps_ip->s_ive_ip.e_arch;
3606 ps_cfg->e_soc = ps_ip->s_ive_ip.e_soc;
3607 ps_cfg->u4_enable_recon = ps_ip->s_ive_ip.u4_enable_recon;
3608 ps_cfg->e_rc_mode = ps_ip->s_ive_ip.e_rc_mode;
3609
3610 /* Validate params */
3611 if ((ps_ip->s_ive_ip.u4_max_level < MIN_LEVEL)
3612 || (ps_ip->s_ive_ip.u4_max_level > MAX_LEVEL))
3613 {
3614 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED;
3615 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL;
3616 }
3617
3618 if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_CNT)
3619 {
3620 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED;
3621 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT;
3622 }
3623
3624 if (ps_ip->s_ive_ip.u4_max_reorder_cnt > MAX_REF_CNT)
3625 {
3626 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED;
3627 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT;
3628 }
3629
3630 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP];
3631 {
3632 ps_codec->ps_mem_rec_backup = (iv_mem_rec_t *) ps_mem_rec->pv_base;
3633
3634 memcpy(ps_codec->ps_mem_rec_backup, ps_mem_rec_base,
3635 MEM_REC_CNT * sizeof(iv_mem_rec_t));
3636 }
3637
3638 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY];
3639 {
3640 /* temp var */
3641 WORD32 size = 0, offset;
3642
3643 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3644 {
3645 if (i < MAX_PROCESS_CTXT / 2)
3646 {
3647 /* base ptr */
3648 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3649
3650 /* reset size */
3651 size = 0;
3652
3653 /* skip mb run */
3654 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run =
3655 (void *) (pu1_buf + size);
3656 size += sizeof(WORD32);
3657 size = ALIGN8(size);
3658
3659 /* entropy map */
3660 ps_codec->as_process[i].s_entropy.pu1_entropy_map =
3661 (void *) (pu1_buf + size + max_mb_cols);
3662 /* size in bytes to store entropy status of an entire frame */
3663 size += (max_mb_cols * max_mb_rows);
3664 /* add an additional 1 row of bytes to evade the special case of row 0 */
3665 size += max_mb_cols;
3666 size = ALIGN128(size);
3667
3668 /* bit stream ptr */
3669 ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf
3670 + size);
3671 size += sizeof(bitstrm_t);
3672 size = ALIGN128(size);
3673
3674 /* nnz luma */
3675 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma =
3676 (void *) (pu1_buf + size);
3677 size += (max_mb_cols * 4 * sizeof(UWORD8));
3678 size = ALIGN128(size);
3679
3680 /* nnz chroma */
3681 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr =
3682 (void *) (pu1_buf + size);
3683 size += (max_mb_cols * 4 * sizeof(UWORD8));
3684 size = ALIGN128(size);
3685 offset = size;
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]3686 /* cabac Context */
3687 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3688 }
3689 else
3690 {
3691 /* base ptr */
3692 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3693
3694 /* reset size */
3695 size = offset;
3696
3697 /* skip mb run */
3698 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run =
3699 (void *) (pu1_buf + size);
3700 size += sizeof(WORD32);
3701 size = ALIGN8(size);
3702
3703 /* entropy map */
3704 ps_codec->as_process[i].s_entropy.pu1_entropy_map =
3705 (void *) (pu1_buf + size + max_mb_cols);
3706 /* size in bytes to store entropy status of an entire frame */
3707 size += (max_mb_cols * max_mb_rows);
3708 /* add an additional 1 row of bytes to evade the special case of row 0 */
3709 size += max_mb_cols;
3710 size = ALIGN128(size);
3711
3712 /* bit stream ptr */
3713 ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf
3714 + size);
3715 size += sizeof(bitstrm_t);
3716 size = ALIGN128(size);
3717
3718 /* nnz luma */
3719 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma =
3720 (void *) (pu1_buf + size);
3721 size += (max_mb_cols * 4 * sizeof(UWORD8));
3722 size = ALIGN128(size);
3723
3724 /* nnz chroma */
3725 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr =
3726 (void *) (pu1_buf + size);
3727 size += (max_mb_cols * 4 * sizeof(UWORD8));
3728 size = ALIGN128(size);
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]3729 /* cabac Context */
3730 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3731 }
3732 }
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]3733 ps_codec->as_process[0].s_entropy.ps_cabac->ps_mb_map_ctxt_inc_base =
3734 ps_mb_map_ctxt_inc;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3735 }
3736
3737 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA];
3738 {
3739 /* temp var */
3740 WORD32 size = 0, size_of_row;
3741 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3742
3743 /* size of coeff data of 1 mb */
3744 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS;
3745
3746 /* size of coeff data of 1 row of mb's */
3747 size *= max_mb_cols;
3748
3749 /* align to avoid false sharing */
3750 size = ALIGN64(size);
3751 size_of_row = size;
3752
3753 /* size for one full frame */
3754 size *= max_mb_rows;
3755
3756 ps_codec->u4_size_coeff_data = size_of_row;
3757
3758 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3759 {
3760 if (i < MAX_PROCESS_CTXT / 2)
3761 {
3762 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf;
3763 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data =
3764 pu1_buf;
3765 }
3766 else
3767 {
3768 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf + size;
3769 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data = pu1_buf
3770 + size;
3771 }
3772 }
3773 }
3774
3775 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA];
3776 {
3777 /* temp var */
3778 WORD32 size, size_of_row;
3779 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3780
3781 /* size of header data of 1 mb */
3782 size = 40;
3783
3784 /* size for 1 row of mbs */
3785 size = size * max_mb_cols;
3786
3787 /* align to avoid any false sharing across threads */
3788 size = ALIGN64(size);
3789 size_of_row = size;
3790
3791 /* size for one full frame */
3792 size *= max_mb_rows;
3793
3794 ps_codec->u4_size_header_data = size_of_row;
3795
3796 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3797 {
3798 if (i < MAX_PROCESS_CTXT / 2)
3799 {
3800 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf;
3801 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data =
3802 pu1_buf;
3803 }
3804 else
3805 {
3806 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf + size;
3807 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data =
3808 pu1_buf + size;
3809 }
3810 }
3811 }
3812
3813 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK];
3814 {
3815 /* size of buf mgr struct */
3816 WORD32 size = ih264_buf_mgr_size();
3817
3818 /* temp var */
3819 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3820
3821 /* mv buffer mgr */
3822 ps_codec->pv_mv_buf_mgr_base = pu1_buf;
3823
3824 /* mv bank */
3825 ps_codec->pv_mv_bank_buf_base = pu1_buf + size;
3826 ps_codec->i4_total_mv_bank_size = ps_mem_rec->u4_mem_size - size;
3827 }
3828
3829 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS];
3830 {
3831 /* max srch range x */
3832 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x;
3833
3834 /* max srch range y */
3835 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y;
3836
3837 /* max srch range */
3838 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y);
3839
3840 /* temp var */
3841 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3842
3843 /* due to subpel */
3844 u4_max_srch_range <<= 2;
3845
3846// /* due to mv on either direction */
3847// u4_max_srch_range = (u4_max_srch_range << 1);
3848
3849 /* due to pred mv + zero */
3850 u4_max_srch_range = (u4_max_srch_range << 1) + 1;
3851
3852 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3853 {
3854 /* me ctxt */
3855 me_ctxt_t *ps_mem_ctxt = &(ps_codec->as_process[i].s_me_ctxt);
3856
3857 /* init at zero mv */
3858 ps_mem_ctxt->pu1_mv_bits = pu1_buf + u4_max_srch_range;
3859 }
3860 }
3861
3862 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS];
3863 {
3864 ps_codec->ps_sps_base = (sps_t *) ps_mem_rec->pv_base;
3865 }
3866
3867 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS];
3868 {
3869 ps_codec->ps_pps_base = (pps_t *) ps_mem_rec->pv_base;
3870 }
3871
3872 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR];
3873 {
3874 ps_codec->ps_slice_hdr_base = ps_mem_rec->pv_base;
3875
3876 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3877 {
3878 if (i < MAX_PROCESS_CTXT / 2)
3879 {
3880 ps_codec->as_process[i].ps_slice_hdr_base = ps_mem_rec->pv_base;
3881 }
3882 else
3883 {
3884 /* temp var */
3885 WORD32 size = MAX_SLICE_HDR_CNT * sizeof(slice_header_t);
3886 void *pv_buf = (UWORD8 *) ps_mem_rec->pv_base + size;
3887
3888 ps_codec->as_process[i].ps_slice_hdr_base = pv_buf;
3889 }
3890 }
3891 }
3892
3893 ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP];
3894 {
3895 /* temp var */
3896 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3897
3898 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3899 {
3900 if (i < MAX_PROCESS_CTXT / 2)
3901 {
3902 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf;
3903 }
3904 else
3905 {
3906 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf
3907 + max_mb_cnt;
3908 }
3909 }
3910
3911 ps_codec->pu2_intr_rfrsh_map = (UWORD16 *) (pu1_buf + max_mb_cnt * 2);
3912 }
3913
3914 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP];
3915 {
3916 /* pointer to storage space */
3917 UWORD8 *pu1_buf_ping, *pu1_buf_pong;
3918
3919 /* init pointer */
3920 pu1_buf_ping = ps_mem_rec->pv_base;
3921 pu1_buf_pong = pu1_buf_ping + ALIGN64(max_mb_cnt);
3922
3923 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3924 {
3925 if (i < MAX_PROCESS_CTXT / 2)
3926 {
3927 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_ping;
3928 }
3929 else
3930 {
3931 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_pong;
3932 }
3933 }
3934 }
3935
3936 ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE];
3937 {
3938 WORD32 handle_size = ithread_get_handle_size();
3939
3940 for (i = 0; i < MAX_PROCESS_THREADS; i++)
3941 {
3942 ps_codec->apv_proc_thread_handle[i] = (UWORD8 *) ps_mem_rec->pv_base
3943 + (i * handle_size);
3944 }
3945 }
3946
3947 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX];
3948 {
3949 ps_codec->pv_ctl_mutex = ps_mem_rec->pv_base;
3950 }
3951
3952 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX];
3953 {
3954 ps_codec->pv_entropy_mutex = ps_mem_rec->pv_base;
3955 }
3956
3957 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ];
3958 {
3959 ps_codec->pv_proc_jobq_buf = ps_mem_rec->pv_base;
3960 ps_codec->i4_proc_jobq_buf_size = ps_mem_rec->u4_mem_size;
3961 }
3962
3963 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ];
3964 {
3965 ps_codec->pv_entropy_jobq_buf = ps_mem_rec->pv_base;
3966 ps_codec->i4_entropy_jobq_buf_size = ps_mem_rec->u4_mem_size;
3967 }
3968
3969 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP];
3970 {
3971 /* pointer to storage space */
3972 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
3973
3974 /* total size of the mem record */
3975 WORD32 total_size = 0;
3976
3977 /* size in bytes to mb core coding status of an entire frame */
3978 total_size = max_mb_cnt;
3979
3980 /* add an additional 1 row of bytes to evade the special case of row 0 */
3981 total_size += max_mb_cols;
3982
3983 for (i = 0; i < MAX_PROCESS_CTXT; i++)
3984 {
3985 if (i < MAX_PROCESS_CTXT / 2)
3986 {
3987 ps_codec->as_process[i].pu1_proc_map = pu1_buf + max_mb_cols;
3988 }
3989 else
3990 {
3991 ps_codec->as_process[i].pu1_proc_map = pu1_buf + total_size
3992 + max_mb_cols;
3993 }
3994 }
3995 }
3996
3997 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP];
3998 {
3999 /* pointer to storage space */
4000 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4001
4002 /* total size of the mem record */
4003 WORD32 total_size = 0;
4004
4005 /* size in bytes to mb core coding status of an entire frame */
4006 total_size = max_mb_cnt;
4007
4008 /* add an additional 1 row of bytes to evade the special case of row 0 */
4009 total_size += max_mb_cols;
4010
4011 /*Align the memory offsets*/
4012 total_size = ALIGN64(total_size);
4013
4014 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4015 {
4016 if (i < MAX_PROCESS_CTXT / 2)
4017 {
4018 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + max_mb_cols;
4019
4020 }
4021 else
4022 {
4023 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + total_size
4024 + max_mb_cols;
4025
4026 }
4027 }
4028 }
4029
4030 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP];
4031 {
4032 /* pointer to storage space */
4033 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4034
4035 /* total size of the mem record */
4036 WORD32 total_size = 0;
4037
4038 /* size in bytes to mb core coding status of an entire frame */
4039 total_size = max_mb_cnt;
4040
4041 /* add an additional 1 row of bytes to evade the special case of row 0 */
4042 total_size += max_mb_cols;
4043
4044 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4045 {
4046 if (i < MAX_PROCESS_CTXT / 2)
4047 {
4048 ps_codec->as_process[i].pu1_me_map = pu1_buf + max_mb_cols;
4049 }
4050 else
4051 {
4052 ps_codec->as_process[i].pu1_me_map = pu1_buf + total_size
4053 + max_mb_cols;
4054 }
4055 }
4056 }
4057
4058 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR];
4059 {
4060 ps_codec->pv_dpb_mgr = ps_mem_rec->pv_base;
4061 }
4062
4063 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH];
4064 {
4065 /* pointer to storage space */
4066 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4067
4068 /* size of pred buffer, fwd transform output, temp buffer for inv tra */
4069 WORD32 size_pred_luma, size_pred_chroma, size_fwd, size_inv, size_hp;
4070
4071 /* temp var */
4072 WORD32 size = 0;
4073
4074 /* size to hold intra/inter prediction buffer */
4075 size_pred_luma = sizeof(UWORD8) * 16 * 16;
4076 size_pred_chroma = sizeof(UWORD8) * 8 * 16;
4077
4078 /* size to hold fwd transform output */
4079 size_fwd = sizeof(WORD16) * SIZE_TRANS_BUFF;
4080
4081 /* size to hold temporary data during inverse transform */
4082 size_inv = sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS;
4083
4084 /* size to hold half pel plane buffers */
4085 size_hp = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT);
4086
4087 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4088 {
4089 /* prediction buffer */
4090 ps_codec->as_process[i].pu1_pred_mb = (void *) (pu1_buf + size);
4091 ps_codec->as_process[i].i4_pred_strd = 16;
4092 size += size_pred_luma;
4093 size = ALIGN64(size);
4094
4095 /* prediction buffer */
4096 ps_codec->as_process[i].pu1_ref_mb_intra_4x4 = (void *) (pu1_buf
4097 + size);
4098 size += size_pred_luma;
4099 size = ALIGN64(size);
4100
4101 /* prediction buffer intra 16x16 */
4102 ps_codec->as_process[i].pu1_pred_mb_intra_16x16 = (void *) (pu1_buf
4103 + size);
4104 size += size_pred_luma;
4105 size = ALIGN64(size);
4106
4107 /* prediction buffer intra 16x16 plane*/
4108 ps_codec->as_process[i].pu1_pred_mb_intra_16x16_plane =
4109 (void *) (pu1_buf + size);
4110 size += size_pred_luma;
4111 size = ALIGN64(size);
4112
4113 /* prediction buffer intra chroma*/
4114 ps_codec->as_process[i].pu1_pred_mb_intra_chroma = (void *) (pu1_buf
4115 + size);
4116 size += size_pred_chroma;
4117 size = ALIGN64(size);
4118
4119 /* prediction buffer intra chroma plane*/
4120 ps_codec->as_process[i].pu1_pred_mb_intra_chroma_plane =
4121 (void *) (pu1_buf + size);
4122 size += size_pred_chroma;
4123 size = ALIGN64(size);
4124
4125 /* Fwd transform output */
4126 ps_codec->as_process[i].pi2_res_buf = (void *) (pu1_buf + size);
4127 ps_codec->as_process[i].i4_res_strd = 16;
4128 size += size_fwd;
4129 size = ALIGN64(size);
4130
4131 /* Fwd transform output */
4132 ps_codec->as_process[i].pi2_res_buf_intra_4x4 = (void *) (pu1_buf
4133 + size);
4134 size += size_fwd;
4135 size = ALIGN64(size);
4136
4137 /* scratch buffer used during inverse transform */
4138 ps_codec->as_process[i].pv_scratch_buff = (void *) (pu1_buf + size);
4139 size += size_inv;
4140 size = ALIGN64(size);
4141
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]4142 for (j = 0; j < SUBPEL_BUFF_CNT; j++)
4143 {
4144 ps_codec->as_process[i].apu1_subpel_buffs[j] = (pu1_buf + size);
4145 size += ALIGN64(size_hp);
4146 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4147 }
4148 }
4149
4150 ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM];
4151 {
4152 /* pointer to storage space */
4153 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base;
4154
4155 /* size of qp, threshold matrix, fwd scaling list for one plane */
4156 WORD32 size_quant_param, size_thres_mat, size_fwd_weight_mat,
4157 size_satqd_weight_mat;
4158
4159 /* temp var */
4160 WORD32 total_size = 0;
4161
4162 /* size of quantization parameter list of 1 plane */
4163 size_quant_param = ALIGN64(sizeof(quant_params_t));
4164
4165 /* size of threshold matrix for quantization
4166 * (assuming the transform_8x8_flag is disabled).
4167 * for 1 plane */
4168 size_thres_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
4169
4170 /* size of forward weight matrix for quantization
4171 * (assuming the transform_8x8_flag is disabled).
4172 * for 1 plane */
4173 size_fwd_weight_mat = ALIGN64(sizeof(WORD16) * 4 * 4);
4174
4175 /* size of SATQD matrix*/
4176 size_satqd_weight_mat = ALIGN64(sizeof(UWORD16) * 9);
4177
4178 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4179 {
4180 quant_params_t **ps_qp_params = ps_codec->as_process[i].ps_qp_params;
4181
4182 /* quantization param structure */
4183 ps_qp_params[0] = (quant_params_t *) (pu1_buf + total_size);
4184 total_size = total_size + size_quant_param;
4185 ps_qp_params[1] = (quant_params_t *) (pu1_buf + total_size);
4186 total_size = total_size + size_quant_param;
4187 ps_qp_params[2] = (quant_params_t *) (pu1_buf + total_size);
4188 total_size = total_size + size_quant_param;
4189
4190 /* threshold matrix for quantization */
4191 ps_qp_params[0]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4192 total_size = total_size + size_thres_mat;
4193 ps_qp_params[1]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4194 total_size = total_size + size_thres_mat;
4195 ps_qp_params[2]->pu2_thres_mat = (void *) (pu1_buf + total_size);
4196 total_size = total_size + size_thres_mat;
4197
4198 /* fwd weight matrix */
4199 ps_qp_params[0]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4200 total_size = total_size + size_fwd_weight_mat;
4201 ps_qp_params[1]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4202 total_size = total_size + size_fwd_weight_mat;
4203 ps_qp_params[2]->pu2_weigh_mat = (void *) (pu1_buf + total_size);
4204 total_size = total_size + size_fwd_weight_mat;
4205
4206 /* threshold matrix for SATQD */
4207 ps_qp_params[0]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4208 total_size = total_size + size_satqd_weight_mat;
4209 ps_qp_params[1]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4210 total_size = total_size + size_satqd_weight_mat;
4211 ps_qp_params[2]->pu2_sad_thrsh = (void *) (pu1_buf + total_size);
4212 total_size = total_size + size_satqd_weight_mat;
4213
4214 total_size = ALIGN128(total_size);
4215 }
4216 }
4217
4218 ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO];
4219 {
4220 /* total size of the mem record */
4221 WORD32 total_size = 0, size_csbp, size_intra_modes, size_mv;
4222
4223 /* pointer to buffer */
4224 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4225
4226 /* size in bytes to store 1 row of mb_info_t */
4227 /* one additional mb, to avoid checking end of row condition */
4228 size_csbp = (max_mb_cols + 1) * sizeof(mb_info_t);
4229
4230 /* size in bytes to store 1 row of intra macroblock sub modes */
4231 size_intra_modes = max_mb_cols * sizeof(UWORD8) * 16;
4232
4233 /* size in bytes to store 1 row + 1 of enc_pu_t */
4234 /* one additional mb, to avoid checking end of row condition */
4235 size_mv = (max_mb_cols + 1) * sizeof(enc_pu_t);
4236
4237 /* total size per proc ctxt */
4238 total_size = size_csbp + size_intra_modes + size_mv;
4239
4240 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4241 {
4242 if (i < MAX_PROCESS_CTXT / 2)
4243 {
4244 ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base =
4245 (mb_info_t *) pu1_buf;
4246 ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf
4247 + size_csbp;
4248 ps_codec->as_process[i].ps_top_row_pu_base =
4249 (enc_pu_t *) (pu1_buf + size_csbp
4250 + size_intra_modes);
4251 }
4252 else
4253 {
4254 ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base =
4255 (mb_info_t *) (pu1_buf + total_size);
4256 ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf
4257 + total_size + size_csbp;
4258 ps_codec->as_process[i].ps_top_row_pu_base =
4259 (enc_pu_t *) (pu1_buf + total_size + size_csbp
4260 + size_intra_modes);
4261 }
4262 }
4263 }
4264
4265 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP];
4266 {
4267 UWORD8 *pu1_buf_ping, *pu1_buf_pong;
4268
4269 /* total size of the mem record */
4270 WORD32 total_size = 0;
4271
4272 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/
4273 WORD32 vert_bs_size, horz_bs_size, qp_size;
4274
4275 /* vertical edge bs = total number of vertical edges * number of bytes per each edge */
4276 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0),
4277 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
4278 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
4279
4280 /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */
4281 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0),
4282 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */
4283 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4);
4284
4285 /* qp of each mb requires 1 byte */
4286 qp_size = ALIGN64(max_mb_cnt);
4287
4288 /* total size */
4289 total_size = vert_bs_size + horz_bs_size + qp_size;
4290
4291 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4292 {
4293 if (i < MAX_PROCESS_CTXT / 2)
4294 {
4295 pu1_buf_ping = (UWORD8 *) ps_mem_rec->pv_base;
4296
4297 /* vertical edge bs storage space */
4298 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs =
4299 (UWORD32 *) pu1_buf_ping;
4300 pu1_buf_ping += vert_bs_size;
4301
4302 /* horizontal edge bs storage space */
4303 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs =
4304 (UWORD32 *) pu1_buf_ping;
4305 pu1_buf_ping += horz_bs_size;
4306
4307 /* qp */
4308 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp =
4309 (UWORD8 *) pu1_buf_ping;
4310 pu1_buf_ping += qp_size;
4311 }
4312 else
4313 {
4314 pu1_buf_pong = (UWORD8 *) ps_mem_rec->pv_base;
4315 pu1_buf_pong += total_size;
4316
4317 /* vertical edge bs storage space */
4318 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs =
4319 (UWORD32 *) pu1_buf_pong;
4320 pu1_buf_pong += vert_bs_size;
4321
4322 /* horizontal edge bs storage space */
4323 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs =
4324 (UWORD32 *) pu1_buf_pong;
4325 pu1_buf_pong += horz_bs_size;
4326
4327 /* qp */
4328 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp =
4329 (UWORD8 *) pu1_buf_pong;
4330 pu1_buf_pong += qp_size;
4331 }
4332 }
4333 }
4334
4335 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC];
4336 {
4337 ps_codec->pv_inp_buf_mgr_base = ps_mem_rec->pv_base;
4338 }
4339
4340 ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT];
4341 {
4342 ps_codec->pv_out_buf_mgr_base = ps_mem_rec->pv_base;
4343 }
4344
4345 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC];
4346 {
4347 ps_codec->pu1_y_csc_buf_base = ps_mem_rec->pv_base;
4348 ps_codec->pu1_uv_csc_buf_base = (UWORD8 *) ps_mem_rec->pv_base
4349 + (max_ht_luma * max_wd_luma);
4350 }
4351
4352 ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC];
4353 {
4354 /* size of buf mgr struct */
4355 WORD32 size = ih264_buf_mgr_size();
4356
4357 /* temp var */
4358 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4359
4360 /* pic buffer mgr */
4361 ps_codec->pv_ref_buf_mgr_base = pu1_buf;
4362
4363 /* picture bank */
4364 ps_codec->pv_pic_buf_base = pu1_buf + size;
4365 ps_codec->i4_total_pic_buf_size = ps_mem_rec->u4_mem_size - size;
4366 }
4367
4368 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB];
4369 {
4370 /* temp var */
4371 UWORD8 *pu1_buf = ps_mem_rec->pv_base;
4372
4373 /* size of nmb ctxt */
4374 WORD32 size = MAX_NMB * sizeof(mb_info_nmb_t);
4375
4376 UWORD32 nmb_cntr, subpel_buf_size;
4377
4378 /* init nmb info structure pointer in all proc ctxts */
4379 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4380 {
4381 ps_codec->as_process[i].ps_nmb_info = (mb_info_nmb_t *) (pu1_buf);
4382
4383 pu1_buf += size;
4384 }
4385
4386 subpel_buf_size = MB_SIZE * MB_SIZE * sizeof(UWORD8);
4387
4388 /* adjusting pointers for nmb halfpel buffer */
4389 for (i = 0; i < MAX_PROCESS_CTXT; i++)
4390 {
4391 mb_info_nmb_t* ps_mb_info_nmb =
4392 &ps_codec->as_process[i].ps_nmb_info[0];
4393
4394 for (nmb_cntr = 0; nmb_cntr < MAX_NMB; nmb_cntr++)
4395 {
4396 ps_mb_info_nmb[nmb_cntr].pu1_best_sub_pel_buf = pu1_buf;
4397
4398 pu1_buf = pu1_buf + subpel_buf_size;
4399
4400 ps_mb_info_nmb[nmb_cntr].u4_bst_spel_buf_strd = MB_SIZE;
4401 }
4402 }
4403 }
4404
4405 ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC];
4406 {
4407 ih264e_get_rate_control_mem_tab(&ps_codec->s_rate_control, ps_mem_rec,
4408 USE_BASE);
4409 }
4410
4411 /* init codec ctxt */
4412 status = ih264e_init(ps_codec);
4413
4414 return status;
4415}
4416
4417/**
4418*******************************************************************************
4419*
4420* @brief
4421* Retrieves mem records passed to the codec
4422*
4423* @par Description:
4424* Retrieves mem recs passed during init
4425*
4426* @param[in] ps_codec_obj
4427* Pointer to codec object at API level
4428*
4429* @param[in] pv_api_ip
4430* Pointer to input argument structure
4431*
4432* @param[out] pv_api_op
4433* Pointer to output argument structure
4434*
4435* @returns error status
4436*
4437* @remarks none
4438*
4439*******************************************************************************
4440*/
4441static WORD32 ih264e_retrieve_memrec(iv_obj_t *ps_codec_obj,
4442 void *pv_api_ip,
4443 void *pv_api_op)
4444{
4445 /* codec ctxt */
4446 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
4447
4448 /* ctrl call I/O structures */
4449 ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip;
4450 ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op;
4451
4452 if (ps_codec->i4_init_done != 1)
4453 {
4454 ps_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
4455 ps_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
4456 return IV_FAIL;
4457 }
4458
4459 /* join threads upon at end of sequence */
4460 ih264e_join_threads(ps_codec);
4461
4462 /* collect list of memory records used by the encoder library */
4463 memcpy(ps_ip->s_ive_ip.ps_mem_rec, ps_codec->ps_mem_rec_backup,
4464 MEM_REC_CNT * (sizeof(iv_mem_rec_t)));
4465 ps_op->s_ive_op.u4_num_mem_rec_filled = MEM_REC_CNT;
4466
4467 /* clean up mutex memory */
4468 ih264_list_free(ps_codec->pv_entropy_jobq);
4469 ih264_list_free(ps_codec->pv_proc_jobq);
4470 ithread_mutex_destroy(ps_codec->pv_ctl_mutex);
4471 ithread_mutex_destroy(ps_codec->pv_entropy_mutex);
4472
4473
4474 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_mv_buf_mgr);
4475 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_ref_buf_mgr);
4476 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_inp_buf_mgr);
4477 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_out_buf_mgr);
4478
4479 return IV_SUCCESS;
4480}
4481
4482/**
4483*******************************************************************************
4484*
4485* @brief
4486* Sets the encoder in flush mode.
4487*
4488* @par Description:
4489* Sets the encoder in flush mode
4490*
4491* @param[in] ps_codec_obj
4492* Pointer to codec object at API level
4493*
4494* @param[in] pv_api_ip
4495* Pointer to input argument structure
4496*
4497* @param[out] pv_api_op
4498* Pointer to output argument structure
4499*
4500* @returns error status
4501*
4502* @remarks This call has no real effect on encoder
4503*
4504*******************************************************************************
4505*/
4506static WORD32 ih264e_set_flush_mode(iv_obj_t *ps_codec_obj,
4507 void *pv_api_ip,
4508 void *pv_api_op)
4509{
4510 UNUSED(pv_api_ip);
4511 /* codec ctxt */
4512 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
4513
4514 /* ctrl call I/O structures */
4515 ih264e_ctl_flush_op_t *ps_ctl_op = pv_api_op;
4516
4517 ps_ctl_op->s_ive_op.u4_error_code = 0;
4518
4519 /* signal flush frame control call */
4520 ps_codec->i4_flush_mode = 1;
4521
4522 return IV_SUCCESS;
4523}
4524
4525/**
4526*******************************************************************************
4527*
4528* @brief
4529* Gets encoder buffer requirements
4530*
4531* @par Description:
4532* Gets the encoder buffer requirements. Basing on max width and max height
4533* configuration settings, this routine, computes the sizes of necessary input,
4534* output buffers returns this info to callee.
4535*
4536* @param[in] ps_codec_obj
4537* Pointer to codec object at API level
4538*
4539* @param[in] pv_api_ip
4540* Pointer to input argument structure
4541*
4542* @param[out] pv_api_op
4543* Pointer to output argument structure
4544*
4545* @returns error status
4546*
4547* @remarks none
4548*
4549*******************************************************************************
4550*/
4551static WORD32 ih264e_get_buf_info(iv_obj_t *ps_codec_obj,
4552 void *pv_api_ip,
4553 void *pv_api_op)
4554{
4555 UNUSED(ps_codec_obj);
4556 /* ctrl call I/O structures */
4557 ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip;
4558 ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op;
4559
4560 /* temp var */
4561 WORD32 wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd);
4562 WORD32 ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht);
4563 WORD32 i;
4564
4565 ps_op->s_ive_op.u4_error_code = 0;
4566
4567 /* Number of components in input buffers required for codec &
4568 * Minimum sizes of each component in input buffer required */
4569 if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420P)
4570 {
4571 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420_COMP;
4572
4573 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
4574 ps_op->s_ive_op.au4_min_in_buf_size[1] = (wd >> 1) * (ht >> 1);
4575 ps_op->s_ive_op.au4_min_in_buf_size[2] = (wd >> 1) * (ht >> 1);
4576 }
4577 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_422ILE)
4578 {
4579 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_422ILE_COMP;
4580
4581 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
4582 ps_op->s_ive_op.au4_min_in_buf_size[1] =
4583 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4584 }
4585 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGB_565)
4586 {
4587 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGB565_COMP;
4588
4589 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2;
4590 ps_op->s_ive_op.au4_min_in_buf_size[1] =
4591 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4592 }
4593 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGBA_8888)
4594 {
4595 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGBA8888_COMP;
4596
4597 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 4;
4598 ps_op->s_ive_op.au4_min_in_buf_size[1] =
4599 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4600 }
4601 else if ((ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_UV)
4602 || (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_VU))
4603 {
4604 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420SP_COMP;
4605
4606 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht;
4607 ps_op->s_ive_op.au4_min_in_buf_size[1] = wd * (ht >> 1);
4608 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0;
4609 }
4610
4611 /* Number of components in output buffers required for codec &
4612 * Minimum sizes of each component in output buffer required */
4613 ps_op->s_ive_op.u4_out_comp_cnt = MIN_BITS_BUFS_COMP;
4614
4615 for (i = 0; i < (WORD32) ps_op->s_ive_op.u4_out_comp_cnt; i++)
4616 {
4617 ps_op->s_ive_op.au4_min_out_buf_size[i] = (wd * ht * 3) >> 1;
4618 }
4619
4620 ps_op->s_ive_op.u4_min_inp_bufs = MIN_INP_BUFS;
4621 ps_op->s_ive_op.u4_min_out_bufs = MIN_OUT_BUFS;
4622
4623 return IV_SUCCESS;
4624}
4625
4626/**
4627*******************************************************************************
4628*
4629* @brief
4630* Sets the picture dimensions
4631*
4632* @par Description:
4633* Sets width, height, display width, display height and strides
4634*
4635* @param[in] pv_api_ip
4636* Pointer to input argument structure
4637*
4638* @param[out] pv_api_op
4639* Pointer to output argument structure
4640*
4641* @param[out] ps_cfg
4642* Pointer to config structure to be updated
4643*
4644* @returns error status
4645*
4646* @remarks none
4647*
4648*******************************************************************************
4649*/
4650static IV_STATUS_T ih264e_set_dimensions(void *pv_api_ip,
4651 void *pv_api_op,
4652 cfg_params_t *ps_cfg)
4653{
4654 /* ctrl call I/O structures */
4655 ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip;
4656 ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op;
4657
4658 ps_op->s_ive_op.u4_error_code = 0;
4659
4660 ps_cfg->u4_wd = ALIGN16(ps_ip->s_ive_ip.u4_wd);
4661 ps_cfg->u4_ht = ALIGN16(ps_ip->s_ive_ip.u4_ht);
4662 ps_cfg->u4_strd = ps_ip->s_ive_ip.u4_strd;
4663 ps_cfg->i4_wd_mbs = ps_cfg->u4_wd >> 4;
4664 ps_cfg->i4_ht_mbs = ps_cfg->u4_ht >> 4;
4665 ps_cfg->u4_disp_wd = ps_ip->s_ive_ip.u4_wd;
4666 ps_cfg->u4_disp_ht = ps_ip->s_ive_ip.u4_ht;
4667
4668 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4669 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4670
4671 return IV_SUCCESS;
4672}
4673
4674/**
4675*******************************************************************************
4676*
4677* @brief
4678* Sets source and target frame rates
4679*
4680* @par Description:
4681* Sets source and target frame rates
4682*
4683* @param[in] pv_api_ip
4684* Pointer to input argument structure
4685*
4686* @param[out] pv_api_op
4687* Pointer to output argument structure
4688*
4689* @param[out] ps_cfg
4690* Pointer to config structure to be updated
4691*
4692* @returns error status
4693*
4694* @remarks none
4695*
4696*******************************************************************************
4697*/
4698static IV_STATUS_T ih264e_set_frame_rate(void *pv_api_ip,
4699 void *pv_api_op,
4700 cfg_params_t *ps_cfg)
4701{
4702 /* ctrl call I/O structures */
4703 ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip;
4704 ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op;
4705
4706 ps_op->s_ive_op.u4_error_code = 0;
4707
4708 ps_cfg->u4_src_frame_rate = ps_ip->s_ive_ip.u4_src_frame_rate;
4709 ps_cfg->u4_tgt_frame_rate = ps_ip->s_ive_ip.u4_tgt_frame_rate;
4710
4711 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4712 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4713
4714 return IV_SUCCESS;
4715}
4716
4717/**
4718*******************************************************************************
4719*
4720* @brief
4721* Sets target bit rate
4722*
4723* @par Description:
4724* Sets target bit rate
4725*
4726* @param[in] pv_api_ip
4727* Pointer to input argument structure
4728*
4729* @param[out] pv_api_op
4730* Pointer to output argument structure
4731*
4732* @param[out] ps_cfg
4733* Pointer to config structure to be updated
4734*
4735* @returns error status
4736*
4737* @remarks none
4738*
4739*******************************************************************************
4740*/
4741static IV_STATUS_T ih264e_set_bit_rate(void *pv_api_ip,
4742 void *pv_api_op,
4743 cfg_params_t *ps_cfg)
4744{
4745 /* ctrl call I/O structures */
4746 ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip;
4747 ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op;
4748
4749 ps_op->s_ive_op.u4_error_code = 0;
4750
4751 ps_cfg->u4_target_bitrate = ps_ip->s_ive_ip.u4_target_bitrate;
4752
4753 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4754 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4755
4756 return IV_SUCCESS;
4757}
4758
4759/**
4760*******************************************************************************
4761*
4762* @brief
4763* Sets frame type
4764*
4765* @par Description:
4766* Sets frame type
4767*
4768* @param[in] pv_api_ip
4769* Pointer to input argument structure
4770*
4771* @param[out] pv_api_op
4772* Pointer to output argument structure
4773*
4774* @param[out] ps_cfg
4775* Pointer to config structure to be updated
4776*
4777* @returns error status
4778*
4779* @remarks not a sticky tag
4780*
4781*******************************************************************************
4782*/
4783static IV_STATUS_T ih264e_set_frame_type(void *pv_api_ip,
4784 void *pv_api_op,
4785 cfg_params_t *ps_cfg)
4786{
4787 /* ctrl call I/O structures */
4788 ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip;
4789 ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op;
4790
4791 ps_op->s_ive_op.u4_error_code = 0;
4792
4793 ps_cfg->e_frame_type = ps_ip->s_ive_ip.e_frame_type;
4794
4795 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4796 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4797
4798 return IV_SUCCESS;
4799}
4800
4801/**
4802*******************************************************************************
4803*
4804* @brief
4805* Sets quantization params
4806*
4807* @par Description:
4808* Sets the max, min and default qp for I frame, P frame and B frame
4809*
4810* @param[in] pv_api_ip
4811* Pointer to input argument structure
4812*
4813* @param[out] pv_api_op
4814* Pointer to output argument structure
4815*
4816* @param[out] ps_cfg
4817* Pointer to config structure to be updated
4818*
4819* @returns error status
4820*
4821* @remarks none
4822*
4823*******************************************************************************
4824*/
4825static IV_STATUS_T ih264e_set_qp(void *pv_api_ip,
4826 void *pv_api_op,
4827 cfg_params_t *ps_cfg)
4828{
4829 /* ctrl call I/O structures */
4830 ih264e_ctl_set_qp_ip_t *ps_set_qp_ip = pv_api_ip;
4831 ih264e_ctl_set_qp_op_t *ps_set_qp_op = pv_api_op;
4832
4833 ps_set_qp_op->s_ive_op.u4_error_code = 0;
4834
4835 ps_cfg->u4_i_qp_max = ps_set_qp_ip->s_ive_ip.u4_i_qp_max;
4836 ps_cfg->u4_i_qp_min = ps_set_qp_ip->s_ive_ip.u4_i_qp_min;
4837 ps_cfg->u4_i_qp = ps_set_qp_ip->s_ive_ip.u4_i_qp;
4838 ps_cfg->u4_p_qp_max = ps_set_qp_ip->s_ive_ip.u4_p_qp_max;
4839 ps_cfg->u4_p_qp_min = ps_set_qp_ip->s_ive_ip.u4_p_qp_min;
4840 ps_cfg->u4_p_qp = ps_set_qp_ip->s_ive_ip.u4_p_qp;
4841 ps_cfg->u4_b_qp_max = ps_set_qp_ip->s_ive_ip.u4_b_qp_max;
4842 ps_cfg->u4_b_qp_min = ps_set_qp_ip->s_ive_ip.u4_b_qp_min;
4843 ps_cfg->u4_b_qp = ps_set_qp_ip->s_ive_ip.u4_b_qp;
4844
4845 ps_cfg->u4_timestamp_high = ps_set_qp_ip->s_ive_ip.u4_timestamp_high;
4846 ps_cfg->u4_timestamp_low = ps_set_qp_ip->s_ive_ip.u4_timestamp_low;
4847
4848 return IV_SUCCESS;
4849}
4850
4851/**
4852*******************************************************************************
4853*
4854* @brief
4855* Sets encoding mode
4856*
4857* @par Description:
4858* Sets encoding mode
4859*
4860* @param[in] pv_api_ip
4861* Pointer to input argument structure
4862*
4863* @param[out] pv_api_op
4864* Pointer to output argument structure
4865*
4866* @param[out] ps_cfg
4867* Pointer to config structure to be updated
4868*
4869* @returns error status
4870*
4871* @remarks none
4872*
4873*******************************************************************************
4874*/
4875static IV_STATUS_T ih264e_set_enc_mode(void *pv_api_ip,
4876 void *pv_api_op,
4877 cfg_params_t *ps_cfg)
4878{
4879 /* ctrl call I/O structures */
4880 ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip;
4881 ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op;
4882
4883 ps_op->s_ive_op.u4_error_code = 0;
4884
4885 ps_cfg->e_enc_mode = ps_ip->s_ive_ip.e_enc_mode;
4886
4887 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4888 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4889
4890 return IV_SUCCESS;
4891}
4892
4893/**
4894*******************************************************************************
4895*
4896* @brief
4897* Sets vbv parameters
4898*
4899* @par Description:
4900* Sets vbv parameters
4901*
4902* @param[in] pv_api_ip
4903* Pointer to input argument structure
4904*
4905* @param[out] pv_api_op
4906* Pointer to output argument structure
4907*
4908* @param[out] ps_cfg
4909* Pointer to config structure to be updated
4910*
4911* @returns error status
4912*
4913* @remarks none
4914*
4915*******************************************************************************
4916*/
4917static IV_STATUS_T ih264e_set_vbv_params(void *pv_api_ip,
4918 void *pv_api_op,
4919 cfg_params_t *ps_cfg)
4920{
4921 /* ctrl call I/O structures */
4922 ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip;
4923 ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op;
4924
4925 ps_op->s_ive_op.u4_error_code = 0;
4926
4927 ps_cfg->u4_vbv_buf_size = ps_ip->s_ive_ip.u4_vbv_buf_size;
4928 ps_cfg->u4_vbv_buffer_delay = ps_ip->s_ive_ip.u4_vbv_buffer_delay;
4929
4930 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4931 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4932
4933 return IV_SUCCESS;
4934}
4935
4936/**
4937*******************************************************************************
4938*
4939* @brief
4940* Sets AIR parameters
4941*
4942* @par Description:
4943* Sets AIR parameters
4944*
4945* @param[in] pv_api_ip
4946* Pointer to input argument structure
4947*
4948* @param[out] pv_api_op
4949* Pointer to output argument structure
4950*
4951* @param[out] ps_cfg
4952* Pointer to config structure to be updated
4953*
4954* @returns error status
4955*
4956* @remarks none
4957*
4958*******************************************************************************
4959*/
4960static IV_STATUS_T ih264_set_air_params(void *pv_api_ip,
4961 void *pv_api_op,
4962 cfg_params_t *ps_cfg)
4963{
4964 /* ctrl call I/O structures */
4965 ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip;
4966 ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op;
4967
4968 ps_op->s_ive_op.u4_error_code = 0;
4969
4970 ps_cfg->e_air_mode = ps_ip->s_ive_ip.e_air_mode;
4971 ps_cfg->u4_air_refresh_period = ps_ip->s_ive_ip.u4_air_refresh_period;
4972
4973 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
4974 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
4975
4976 return IV_SUCCESS;
4977}
4978
4979/**
4980*******************************************************************************
4981*
4982* @brief
4983* Sets motion estimation parameters
4984*
4985* @par Description:
4986* Sets motion estimation parameters
4987*
4988* @param[in] pv_api_ip
4989* Pointer to input argument structure
4990*
4991* @param[out] pv_api_op
4992* Pointer to output argument structure
4993*
4994* @param[out] ps_cfg
4995* Pointer to config structure to be updated
4996*
4997* @returns error status
4998*
4999* @remarks none
5000*
5001*******************************************************************************
5002*/
5003static IV_STATUS_T ih264_set_me_params(void *pv_api_ip,
5004 void *pv_api_op,
5005 cfg_params_t *ps_cfg)
5006{
5007 /* ctrl call I/O structures */
5008 ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip;
5009 ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op;
5010
5011 ps_op->s_ive_op.u4_error_code = 0;
5012
5013 ps_cfg->u4_enable_hpel = ps_ip->s_ive_ip.u4_enable_hpel;
5014 ps_cfg->u4_enable_qpel = ps_ip->s_ive_ip.u4_enable_qpel;
5015 ps_cfg->u4_enable_fast_sad = ps_ip->s_ive_ip.u4_enable_fast_sad;
5016 ps_cfg->u4_enable_alt_ref = ps_ip->s_ive_ip.u4_enable_alt_ref;
5017 ps_cfg->u4_srch_rng_x = ps_ip->s_ive_ip.u4_srch_rng_x;
5018 ps_cfg->u4_srch_rng_y = ps_ip->s_ive_ip.u4_srch_rng_y;
5019 ps_cfg->u4_me_speed_preset = ps_ip->s_ive_ip.u4_me_speed_preset;
5020
5021 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5022 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5023
5024 return IV_SUCCESS;
5025}
5026
5027/**
5028*******************************************************************************
5029*
5030* @brief
5031* Sets Intra/Inter Prediction estimation parameters
5032*
5033* @par Description:
5034* Sets Intra/Inter Prediction estimation parameters
5035*
5036* @param[in] pv_api_ip
5037* Pointer to input argument structure
5038*
5039* @param[out] pv_api_op
5040* Pointer to output argument structure
5041*
5042* @param[out] ps_cfg
5043* Pointer to config structure to be updated
5044*
5045* @returns error status
5046*
5047* @remarks none
5048*
5049*******************************************************************************
5050*/
5051static IV_STATUS_T ih264_set_ipe_params(void *pv_api_ip,
5052 void *pv_api_op,
5053 cfg_params_t *ps_cfg)
5054{
5055 /* ctrl call I/O structures */
5056 ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip;
5057 ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op;
5058
5059 ps_op->s_ive_op.u4_error_code = 0;
5060
5061 ps_cfg->u4_enable_intra_4x4 = ps_ip->s_ive_ip.u4_enable_intra_4x4;
5062 ps_cfg->u4_enc_speed_preset = ps_ip->s_ive_ip.u4_enc_speed_preset;
5063
5064 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5065 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5066
5067 return IV_SUCCESS;
5068}
5069
5070/**
5071*******************************************************************************
5072*
5073* @brief
5074* Sets GOP parameters
5075*
5076* @par Description:
5077* Sets GOP parameters
5078*
5079* @param[in] pv_api_ip
5080* Pointer to input argument structure
5081*
5082* @param[out] pv_api_op
5083* Pointer to output argument structure
5084*
5085* @param[out] ps_cfg
5086* Pointer to config structure to be updated
5087*
5088* @returns error status
5089*
5090* @remarks none
5091*
5092*******************************************************************************
5093*/
5094static IV_STATUS_T ih264_set_gop_params(void *pv_api_ip,
5095 void *pv_api_op,
5096 cfg_params_t *ps_cfg)
5097{
5098 /* ctrl call I/O structures */
5099 ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip;
5100 ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op;
5101
5102 ps_op->s_ive_op.u4_error_code = 0;
5103
5104 ps_cfg->u4_i_frm_interval = ps_ip->s_ive_ip.u4_i_frm_interval;
5105 ps_cfg->u4_idr_frm_interval = ps_ip->s_ive_ip.u4_idr_frm_interval;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]5106
5107 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5108 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5109
5110 return IV_SUCCESS;
5111}
5112
5113/**
5114*******************************************************************************
5115*
5116* @brief
5117* Sets profile parameters
5118*
5119* @par Description:
5120* Sets profile parameters
5121*
5122* @param[in] pv_api_ip
5123* Pointer to input argument structure
5124*
5125* @param[out] pv_api_op
5126* Pointer to output argument structure
5127*
5128* @param[out] ps_cfg
5129* Pointer to config structure to be updated
5130*
5131* @returns error status
5132*
5133* @remarks none
5134*
5135*******************************************************************************
5136*/
5137static IV_STATUS_T ih264_set_profile_params(void *pv_api_ip,
5138 void *pv_api_op,
5139 cfg_params_t *ps_cfg)
5140{
5141 /* ctrl call I/O structures */
5142 ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip;
5143 ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op;
5144
5145 ps_op->s_ive_op.u4_error_code = 0;
5146
5147 ps_cfg->e_profile = ps_ip->s_ive_ip.e_profile;
5148
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]5149 ps_cfg->u4_entropy_coding_mode = ps_ip->s_ive_ip.u4_entropy_coding_mode;
5150
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]5151 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5152 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5153
5154 return IV_SUCCESS;
5155}
5156
5157/**
5158*******************************************************************************
5159*
5160* @brief
5161* Sets disable deblock level
5162*
5163* @par Description:
5164* Sets disable deblock level. Level 0 means no disabling and level 4 means
5165* disable completely. 1, 2, 3 are intermediate levels that control amount
5166* of deblocking done.
5167*
5168* @param[in] ps_codec_obj
5169* Pointer to codec object at API level
5170*
5171* @param[in] pv_api_ip
5172* Pointer to input argument structure
5173*
5174* @param[out] pv_api_op
5175* Pointer to output argument structure
5176*
5177* @returns error status
5178*
5179* @remarks none
5180*
5181*******************************************************************************
5182*/
5183static WORD32 ih264_set_deblock_params(void *pv_api_ip,
5184 void *pv_api_op,
5185 cfg_params_t *ps_cfg)
5186{
5187 /* ctrl call I/O structures */
5188 ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip;
5189 ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op;
5190
5191 ps_op->s_ive_op.u4_error_code = 0;
5192
5193 ps_cfg->u4_disable_deblock_level = ps_ip->s_ive_ip.u4_disable_deblock_level;
5194
5195 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5196 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5197
5198 return IV_SUCCESS;
5199}
5200
5201/**
5202*******************************************************************************
5203*
5204* @brief
5205* Sets number of cores
5206*
5207* @par Description:
5208* Sets number of cores
5209*
5210* @param[in] ps_codec_obj
5211* Pointer to codec object at API level
5212*
5213* @param[in] pv_api_ip
5214* Pointer to input argument structure
5215*
5216* @param[out] pv_api_op
5217* Pointer to output argument structure
5218*
5219* @returns error status
5220*
5221* @remarks The number of encoder threads is limited to MAX_PROCESS_THREADS
5222*
5223*******************************************************************************
5224*/
5225static WORD32 ih264e_set_num_cores(void *pv_api_ip,
5226 void *pv_api_op,
5227 cfg_params_t *ps_cfg)
5228{
5229 /* ctrl call I/O structures */
5230 ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip;
5231 ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op;
5232
5233 ps_op->s_ive_op.u4_error_code = 0;
5234
5235 ps_cfg->u4_num_cores = MIN(ps_ip->s_ive_ip.u4_num_cores, MAX_PROCESS_THREADS);
5236
5237 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high;
5238 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low;
5239
5240 return IV_SUCCESS;
5241}
5242
5243/**
5244*******************************************************************************
5245*
5246* @brief
5247* Resets encoder state
5248*
5249* @par Description:
5250* Resets encoder state by calling ih264e_init()
5251*
5252* @param[in] ps_codec_obj
5253* Pointer to codec object at API level
5254*
5255* @param[in] pv_api_ip
5256* Pointer to input argument structure
5257*
5258* @param[out] pv_api_op
5259* Pointer to output argument structure
5260*
5261* @returns error status
5262*
5263* @remarks none
5264*
5265*******************************************************************************
5266*/
5267static WORD32 ih264e_reset(iv_obj_t *ps_codec_obj,
5268 void *pv_api_ip,
5269 void *pv_api_op)
5270{
5271 UNUSED(pv_api_ip);
5272 /* codec ctxt */
5273 codec_t * ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle);
5274
5275 /* ctrl call I/O structures */
5276 ih264e_ctl_reset_op_t *ps_op = pv_api_op;
5277
5278 ps_op->s_ive_op.u4_error_code = 0;
5279
5280 if (ps_codec != NULL)
5281 {
5282 ih264e_init(ps_codec);
5283 }
5284 else
5285 {
5286 ps_op->s_ive_op.u4_error_code = IH264E_INIT_NOT_DONE;
5287 }
5288
5289 return IV_SUCCESS;
5290}
5291
5292/**
5293*******************************************************************************
5294*
5295* @brief
5296* Codec control call
5297*
5298* @par Description:
5299* Codec control call which in turn calls appropriate calls based on sub-command
5300*
5301* @param[in] ps_codec_obj
5302* Pointer to codec object at API level
5303*
5304* @param[in] pv_api_ip
5305* Pointer to input argument structure
5306*
5307* @param[out] pv_api_op
5308* Pointer to output argument structure
5309*
5310* @returns error status
5311*
5312* @remarks none
5313*
5314*******************************************************************************
5315*/
5316static WORD32 ih264e_ctl(iv_obj_t *ps_codec_obj,
5317 void *pv_api_ip,
5318 void *pv_api_op)
5319{
5320 /* codec ctxt */
5321 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle;
5322
5323 /* ctrl call I/O structures */
5324 ih264e_ctl_setdefault_ip_t *ps_ctl_ip = pv_api_ip;
5325 ih264e_ctl_setdefault_op_t *ps_ctl_op = pv_api_op;
5326
5327 /* ctrl call sub cmd */
5328 IVE_CONTROL_API_COMMAND_TYPE_T sub_cmd = ps_ctl_ip->s_ive_ip.e_sub_cmd;
5329
5330 /* error status */
Harinarayanan K K134291e2015-06-18 16:03:38 +0530[diff] [blame^]5331 IV_STATUS_T ret = IV_SUCCESS;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]5332
5333 /* temp var */
5334 WORD32 i;
5335 cfg_params_t *ps_cfg = NULL;
5336
5337 /* control call is for configuring encoding params, this is not to be called
5338 * before a successful init call */
5339 if (ps_codec->i4_init_done != 1)
5340 {
5341 ps_ctl_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR;
5342 ps_ctl_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE;
5343 return IV_FAIL;
5344 }
5345
5346 /* make it thread safe */
5347 ithread_mutex_lock(ps_codec->pv_ctl_mutex);
5348
5349 /* find a free config param set to hold current parameters */
5350 for (i = 0; i < MAX_ACTIVE_CONFIG_PARAMS; i++)
5351 {
5352 if (0 == ps_codec->as_cfg[i].u4_is_valid)
5353 {
5354 ps_cfg = &ps_codec->as_cfg[i];
5355 break;
5356 }
5357 }
5358
5359 /* If all are invalid, then start overwriting from the head config params */
5360 if (NULL == ps_cfg)
5361 {
5362 ps_cfg = &ps_codec->as_cfg[0];
5363 }
5364
5365 ps_cfg->u4_is_valid = 1;
5366
5367 ps_cfg->e_cmd = sub_cmd;
5368
5369 switch (sub_cmd)
5370 {
5371 case IVE_CMD_CTL_SET_DIMENSIONS:
5372 ret = ih264e_set_dimensions(pv_api_ip, pv_api_op, ps_cfg);
5373 break;
5374
5375 case IVE_CMD_CTL_SET_FRAMERATE:
5376 ret = ih264e_set_frame_rate(pv_api_ip, pv_api_op, ps_cfg);
5377 break;
5378
5379 case IVE_CMD_CTL_SET_BITRATE:
5380 ret = ih264e_set_bit_rate(pv_api_ip, pv_api_op, ps_cfg);
5381 break;
5382
5383 case IVE_CMD_CTL_SET_FRAMETYPE:
5384 ret = ih264e_set_frame_type(pv_api_ip, pv_api_op, ps_cfg);
5385 break;
5386
5387 case IVE_CMD_CTL_SET_QP:
5388 ret = ih264e_set_qp(pv_api_ip, pv_api_op, ps_cfg);
5389 break;
5390
5391 case IVE_CMD_CTL_SET_ENC_MODE:
5392 ret = ih264e_set_enc_mode(pv_api_ip, pv_api_op, ps_cfg);
5393 break;
5394
5395 case IVE_CMD_CTL_SET_VBV_PARAMS:
5396 ret = ih264e_set_vbv_params(pv_api_ip, pv_api_op, ps_cfg);
5397 break;
5398
5399 case IVE_CMD_CTL_SET_AIR_PARAMS:
5400 ret = ih264_set_air_params(pv_api_ip, pv_api_op, ps_cfg);
5401 break;
5402
5403 case IVE_CMD_CTL_SET_ME_PARAMS:
5404 ret = ih264_set_me_params(pv_api_ip, pv_api_op, ps_cfg);
5405 break;
5406
5407 case IVE_CMD_CTL_SET_IPE_PARAMS:
5408 ret = ih264_set_ipe_params(pv_api_ip, pv_api_op, ps_cfg);
5409 break;
5410
5411 case IVE_CMD_CTL_SET_GOP_PARAMS:
5412 ret = ih264_set_gop_params(pv_api_ip, pv_api_op, ps_cfg);
5413 break;
5414
5415 case IVE_CMD_CTL_SET_PROFILE_PARAMS:
5416 ret = ih264_set_profile_params(pv_api_ip, pv_api_op, ps_cfg);
5417 break;
5418
5419 case IVE_CMD_CTL_SET_DEBLOCK_PARAMS:
5420 ret = ih264_set_deblock_params(pv_api_ip, pv_api_op, ps_cfg);
5421 break;
5422
5423 case IVE_CMD_CTL_RESET:
5424
5425 /* invalidate config param struct as it is being served right away */
5426 ps_codec->as_cfg[i].u4_is_valid = 0;
5427
5428 ret = ih264e_reset(ps_codec_obj, pv_api_ip, pv_api_op);
5429 break;
5430
5431 case IVE_CMD_CTL_SETDEFAULT:
5432 {
5433 /* ctrl call I/O structures */
5434 ih264e_ctl_setdefault_op_t *ps_op = pv_api_op;
5435
5436 /* invalidate config param struct as it is being served right away */
5437 ps_codec->as_cfg[i].u4_is_valid = 0;
5438
5439 /* error status */
5440 ret = ih264e_set_default_params(ps_cfg);
5441
5442 ps_op->s_ive_op.u4_error_code = ret;
5443
5444 break;
5445 }
5446
5447 case IVE_CMD_CTL_FLUSH:
5448
5449 /* invalidate config param struct as it is being served right away */
5450 ps_codec->as_cfg[i].u4_is_valid = 0;
5451
5452 ret = ih264e_set_flush_mode(ps_codec_obj, pv_api_ip, pv_api_op);
5453 break;
5454
5455 case IVE_CMD_CTL_GETBUFINFO:
5456
5457 /* invalidate config param struct as it is being served right away */
5458 ps_codec->as_cfg[i].u4_is_valid = 0;
5459
5460 ret = ih264e_get_buf_info(ps_codec_obj, pv_api_ip, pv_api_op);
5461 break;
5462
5463 case IVE_CMD_CTL_GETVERSION:
5464 {
5465 /* ctrl call I/O structures */
5466 ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip;
5467 ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op;
5468
5469 /* invalidate config param struct as it is being served right away */
5470 ps_codec->as_cfg[i].u4_is_valid = 0;
5471
5472 /* error status */
5473 ps_op->s_ive_op.u4_error_code = IV_SUCCESS;
5474
5475 if (ps_ip->s_ive_ip.u4_version_bufsize <= 0)
5476 {
5477 ps_op->s_ive_op.u4_error_code =
5478 IH264E_CXA_VERS_BUF_INSUFFICIENT;
5479 ret = IV_FAIL;
5480 }
5481 else
5482 {
5483 ret = ih264e_get_version((CHAR *) ps_ip->s_ive_ip.pu1_version,
5484 ps_ip->s_ive_ip.u4_version_bufsize);
5485
5486 if (ret != IV_SUCCESS)
5487 {
5488 ps_op->s_ive_op.u4_error_code =
5489 IH264E_CXA_VERS_BUF_INSUFFICIENT;
5490 ret = IV_FAIL;
5491 }
5492 }
5493 break;
5494 }
5495
5496 case IVE_CMD_CTL_SET_NUM_CORES:
5497 ret = ih264e_set_num_cores(pv_api_ip, pv_api_op, ps_cfg);
5498 break;
5499
5500 default:
5501 /* invalidate config param struct as it is being served right away */
5502 ps_codec->as_cfg[i].u4_is_valid = 0;
5503
5504 DEBUG("Warning !! unrecognized control api command \n");
5505 break;
5506 }
5507
5508 ithread_mutex_unlock(ps_codec->pv_ctl_mutex);
5509
5510 return ret;
5511}
5512
5513/**
5514*******************************************************************************
5515*
5516* @brief
5517* Codec entry point function. All the function calls to the codec are done
5518* using this function with different values specified in command
5519*
5520* @par Description:
5521* Arguments are tested for validity and then based on the command
5522* appropriate function is called
5523*
5524* @param[in] ps_handle
5525* API level handle for codec
5526*
5527* @param[in] pv_api_ip
5528* Input argument structure
5529*
5530* @param[out] pv_api_op
5531* Output argument structure
5532*
5533* @returns error_status
5534*
5535* @remarks
5536*
5537*******************************************************************************
5538*/
5539IV_STATUS_T ih264e_api_function(iv_obj_t *ps_handle,
5540 void *pv_api_ip,
5541 void *pv_api_op)
5542{
5543 /* api command */
5544 WORD32 command = IV_CMD_NA;
5545
5546 /* error status */
5547 IV_STATUS_T e_status;
5548 WORD32 ret;
5549
5550 /* tmp var */
5551 WORD32 *pu4_ptr_cmd = (WORD32 *) pv_api_ip;
5552
5553 /* validate input / output structures */
5554 e_status = api_check_struct_sanity(ps_handle, pv_api_ip, pv_api_op);
5555
5556 if (e_status != IV_SUCCESS)
5557 {
5558 DEBUG("error code = %d\n", *((UWORD32 *)pv_api_op + 1));
5559 return IV_FAIL;
5560 }
5561
5562 pu4_ptr_cmd++;
5563
5564 command = *pu4_ptr_cmd;
5565
5566 switch (command)
5567 {
5568 case IV_CMD_GET_NUM_MEM_REC:
5569 ret = ih264e_get_num_rec(pv_api_ip, pv_api_op);
5570 break;
5571
5572 case IV_CMD_FILL_NUM_MEM_REC:
5573 ret = ih264e_fill_num_mem_rec(pv_api_ip, pv_api_op);
5574 break;
5575
5576 case IV_CMD_INIT:
5577 ret = ih264e_init_mem_rec(ps_handle, pv_api_ip, pv_api_op);
5578 break;
5579
5580 case IV_CMD_RETRIEVE_MEMREC:
5581 ret = ih264e_retrieve_memrec(ps_handle, pv_api_ip, pv_api_op);
5582 break;
5583
5584 case IVE_CMD_VIDEO_CTL:
5585 ret = ih264e_ctl(ps_handle, pv_api_ip, pv_api_op);
5586 break;
5587
5588 case IVE_CMD_VIDEO_ENCODE:
5589 ret = ih264e_encode(ps_handle, pv_api_ip, pv_api_op);
5590 break;
5591
5592 default:
5593 ret = IV_FAIL;
5594 break;
5595 }
5596
5597 return (IV_STATUS_T) ret;
5598}