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gerrit-public.fairphone.software / platform / external / libavc / fe18375850fe04b8c4ff2f1b20069e161f718e53 / . / decoder / ih264d_api.c
blob: 61a91a628418bd23f6186fcff40a0ed238f81dd6 [file] [log] [blame]
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1/******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19*/
20
21/*****************************************************************************/
22/* */
23/* File Name : ih264d_api.c */
24/* */
25/* Description : Has all API related functions */
26/* */
27/* */
28/* List of Functions : api_check_struct_sanity */
29/* ih264d_set_processor */
30/* ih264d_get_num_rec */
31/* ih264d_init_decoder */
32/* ih264d_init_video_decoder */
33/* ih264d_fill_num_mem_rec */
34/* ih264d_clr */
35/* ih264d_init */
36/* ih264d_map_error */
37/* ih264d_video_decode */
38/* ih264d_get_version */
39/* ih264d_get_display_frame */
40/* ih264d_set_display_frame */
41/* ih264d_set_flush_mode */
42/* ih264d_get_status */
43/* ih264d_get_buf_info */
44/* ih264d_set_params */
45/* ih264d_set_default_params */
46/* ih264d_reset */
47/* ih264d_ctl */
48/* ih264d_rel_display_frame */
49/* ih264d_set_degrade */
50/* ih264d_get_frame_dimensions */
51/* ih264d_set_num_cores */
52/* ih264d_fill_output_struct_from_context */
53/* ih264d_api_function */
54/* */
55/* Issues / Problems : None */
56/* */
57/* Revision History : */
58/* */
59/* DD MM YYYY Author(s) Changes (Describe the changes made) */
60/* 14 10 2008 100356(SKV) Draft */
61/* */
62/*****************************************************************************/
63#include "ih264_typedefs.h"
64#include "ih264_macros.h"
65#include "ih264_platform_macros.h"
66#include "ih264d_tables.h"
67#include "iv.h"
68#include "ivd.h"
69#include "ih264d.h"
70#include "ih264d_defs.h"
71
72#include <string.h>
73#include <limits.h>
74#include <stddef.h>
75
76#include "ih264d_inter_pred.h"
77
78#include "ih264d_structs.h"
79#include "ih264d_nal.h"
80#include "ih264d_error_handler.h"
81
82#include "ih264d_defs.h"
83
84#include "ithread.h"
85#include "ih264d_parse_slice.h"
86#include "ih264d_function_selector.h"
87#include "ih264_error.h"
88#include "ih264_disp_mgr.h"
89#include "ih264_buf_mgr.h"
90#include "ih264d_deblocking.h"
91#include "ih264d_parse_cavlc.h"
92#include "ih264d_parse_cabac.h"
93#include "ih264d_utils.h"
94#include "ih264d_format_conv.h"
95#include "ih264d_parse_headers.h"
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]96#include "ih264d_thread_compute_bs.h"
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]97#include <assert.h>
98
99
100/*********************/
101/* Codec Versioning */
102/*********************/
103//Move this to where it is used
104#define CODEC_NAME "H264VDEC"
105#define CODEC_RELEASE_TYPE "production"
106#define CODEC_RELEASE_VER "04.00"
107#define CODEC_VENDOR "ITTIAM"
108#define MAXVERSION_STRLEN 511
109#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
Martin Storsjo85a43d22015-05-20 00:12:28 +0300[diff] [blame]110 snprintf(version_string, MAXVERSION_STRLEN, \
111 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \
112 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]113
114#define MAX_NAL_UNIT_SIZE MAX((H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_HEIGHT),MIN_NALUNIT_SIZE)
115#define MIN_NALUNIT_SIZE 200000
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]116
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]117
118#define MIN_IN_BUFS 1
119#define MIN_OUT_BUFS_420 3
120#define MIN_OUT_BUFS_422ILE 1
121#define MIN_OUT_BUFS_RGB565 1
122#define MIN_OUT_BUFS_420SP 2
123#define MIN_IN_BUF_SIZE (2*1024*1024) // Currently, i4_size set to 500kb, CHECK LATER
124
125#define NUM_FRAMES_LIMIT_ENABLED 0
126
127#if NUM_FRAMES_LIMIT_ENABLED
128#define NUM_FRAMES_LIMIT 10000
129#else
130#define NUM_FRAMES_LIMIT 0x7FFFFFFF
131#endif
132
133
134UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height);
135WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
136 void *pv_api_ip,
137 void *pv_api_op);
138WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
139
140WORD32 ih264d_deblock_display(dec_struct_t *ps_dec);
141
142void ih264d_signal_decode_thread(dec_struct_t *ps_dec);
143
144void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec);
145void ih264d_decode_picture_thread(dec_struct_t *ps_dec);
146
147WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
148 void *pv_api_ip,
149 void *pv_api_op);
150
151void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
152 ivd_video_decode_op_t *ps_dec_op);
153
154static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
155 void *pv_api_ip,
156 void *pv_api_op)
157{
158 IVD_API_COMMAND_TYPE_T e_cmd;
159 UWORD32 *pu4_api_ip;
160 UWORD32 *pu4_api_op;
161 UWORD32 i, j;
162
163 if(NULL == pv_api_op)
164 return (IV_FAIL);
165
166 if(NULL == pv_api_ip)
167 return (IV_FAIL);
168
169 pu4_api_ip = (UWORD32 *)pv_api_ip;
170 pu4_api_op = (UWORD32 *)pv_api_op;
171 e_cmd = *(pu4_api_ip + 1);
172
173 /* error checks on handle */
174 switch((WORD32)e_cmd)
175 {
176 case IV_CMD_GET_NUM_MEM_REC:
177 case IV_CMD_FILL_NUM_MEM_REC:
178 break;
179 case IV_CMD_INIT:
180 if(ps_handle == NULL)
181 {
182 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
183 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
184 return IV_FAIL;
185 }
186
187 if(ps_handle->u4_size != sizeof(iv_obj_t))
188 {
189 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
190 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
191 H264_DEC_DEBUG_PRINT(
192 "Sizes do not match. Expected: %d, Got: %d",
193 sizeof(iv_obj_t), ps_handle->u4_size);
194 return IV_FAIL;
195 }
196 break;
197 case IVD_CMD_REL_DISPLAY_FRAME:
198 case IVD_CMD_SET_DISPLAY_FRAME:
199 case IVD_CMD_GET_DISPLAY_FRAME:
200 case IVD_CMD_VIDEO_DECODE:
201 case IV_CMD_RETRIEVE_MEMREC:
202 case IVD_CMD_VIDEO_CTL:
203 if(ps_handle == NULL)
204 {
205 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
206 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
207 return IV_FAIL;
208 }
209
210 if(ps_handle->u4_size != sizeof(iv_obj_t))
211 {
212 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
213 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
214 return IV_FAIL;
215 }
216
217 if(ps_handle->pv_fxns != ih264d_api_function)
218 {
219 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
220 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
221 return IV_FAIL;
222 }
223
224 if(ps_handle->pv_codec_handle == NULL)
225 {
226 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
227 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
228 return IV_FAIL;
229 }
230 break;
231 default:
232 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
233 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
234 return IV_FAIL;
235 }
236
237 switch((WORD32)e_cmd)
238 {
239 case IV_CMD_GET_NUM_MEM_REC:
240 {
241 ih264d_num_mem_rec_ip_t *ps_ip =
242 (ih264d_num_mem_rec_ip_t *)pv_api_ip;
243 ih264d_num_mem_rec_op_t *ps_op =
244 (ih264d_num_mem_rec_op_t *)pv_api_op;
245 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0;
246
247 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size
248 != sizeof(ih264d_num_mem_rec_ip_t))
249 {
250 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1
251 << IVD_UNSUPPORTEDPARAM;
252 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |=
253 IVD_IP_API_STRUCT_SIZE_INCORRECT;
254 return (IV_FAIL);
255 }
256
257 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size
258 != sizeof(ih264d_num_mem_rec_op_t))
259 {
260 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1
261 << IVD_UNSUPPORTEDPARAM;
262 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |=
263 IVD_OP_API_STRUCT_SIZE_INCORRECT;
264 return (IV_FAIL);
265 }
266 }
267 break;
268 case IV_CMD_FILL_NUM_MEM_REC:
269 {
270 ih264d_fill_mem_rec_ip_t *ps_ip =
271 (ih264d_fill_mem_rec_ip_t *)pv_api_ip;
272 ih264d_fill_mem_rec_op_t *ps_op =
273 (ih264d_fill_mem_rec_op_t *)pv_api_op;
274 iv_mem_rec_t *ps_mem_rec;
275 WORD32 max_wd = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd;
276 WORD32 max_ht = ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht;
277
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]278 max_wd = ALIGN16(max_wd);
279 max_ht = ALIGN32(max_ht);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]280
281 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
282
283 if((ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size
284 > sizeof(ih264d_fill_mem_rec_ip_t))
285 || (ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size
286 < sizeof(iv_fill_mem_rec_ip_t)))
287 {
288 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
289 << IVD_UNSUPPORTEDPARAM;
290 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
291 IVD_IP_API_STRUCT_SIZE_INCORRECT;
292 return (IV_FAIL);
293 }
294
295 if((ps_op->s_ivd_fill_mem_rec_op_t.u4_size
296 != sizeof(ih264d_fill_mem_rec_op_t))
297 && (ps_op->s_ivd_fill_mem_rec_op_t.u4_size
298 != sizeof(iv_fill_mem_rec_op_t)))
299 {
300 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
301 << IVD_UNSUPPORTEDPARAM;
302 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
303 IVD_OP_API_STRUCT_SIZE_INCORRECT;
304 return (IV_FAIL);
305 }
306
307 if(max_wd < H264_MIN_FRAME_WIDTH)
308 {
309 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
310 << IVD_UNSUPPORTEDPARAM;
311 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
312 IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
313 return (IV_FAIL);
314 }
315
316 if(max_wd > H264_MAX_FRAME_WIDTH)
317 {
318 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
319 << IVD_UNSUPPORTEDPARAM;
320 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
321 IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
322 return (IV_FAIL);
323 }
324
325 if(max_ht < H264_MIN_FRAME_HEIGHT)
326 {
327 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
328 << IVD_UNSUPPORTEDPARAM;
329 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
330 IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
331 return (IV_FAIL);
332 }
333
334 if((max_ht * max_wd)
335 > (H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_WIDTH))
336
337 {
338 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
339 << IVD_UNSUPPORTEDPARAM;
340 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
341 IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
342 return (IV_FAIL);
343 }
344
345 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location)
346 {
347 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
348 << IVD_UNSUPPORTEDPARAM;
349 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
350 IVD_NUM_REC_NOT_SUFFICIENT;
351 return (IV_FAIL);
352 }
353
354 /* check memrecords sizes are correct */
355 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
356 for(i = 0; i < MEM_REC_CNT; i++)
357 {
358 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
359 {
360 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1
361 << IVD_UNSUPPORTEDPARAM;
362 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
363 IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
364 return IV_FAIL;
365 }
366 }
367 }
368 break;
369
370 case IV_CMD_INIT:
371 {
372 ih264d_init_ip_t *ps_ip = (ih264d_init_ip_t *)pv_api_ip;
373 ih264d_init_op_t *ps_op = (ih264d_init_op_t *)pv_api_op;
374 iv_mem_rec_t *ps_mem_rec;
375 WORD32 max_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd;
376 WORD32 max_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht;
377
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]378 max_wd = ALIGN16(max_wd);
379 max_ht = ALIGN32(max_ht);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]380
381 ps_op->s_ivd_init_op_t.u4_error_code = 0;
382
383 if((ps_ip->s_ivd_init_ip_t.u4_size > sizeof(ih264d_init_ip_t))
384 || (ps_ip->s_ivd_init_ip_t.u4_size
385 < sizeof(ivd_init_ip_t)))
386 {
387 ps_op->s_ivd_init_op_t.u4_error_code |= 1
388 << IVD_UNSUPPORTEDPARAM;
389 ps_op->s_ivd_init_op_t.u4_error_code |=
390 IVD_IP_API_STRUCT_SIZE_INCORRECT;
391 H264_DEC_DEBUG_PRINT("\n");
392 return (IV_FAIL);
393 }
394
395 if((ps_op->s_ivd_init_op_t.u4_size != sizeof(ih264d_init_op_t))
396 && (ps_op->s_ivd_init_op_t.u4_size
397 != sizeof(ivd_init_op_t)))
398 {
399 ps_op->s_ivd_init_op_t.u4_error_code |= 1
400 << IVD_UNSUPPORTEDPARAM;
401 ps_op->s_ivd_init_op_t.u4_error_code |=
402 IVD_OP_API_STRUCT_SIZE_INCORRECT;
403 H264_DEC_DEBUG_PRINT("\n");
404 return (IV_FAIL);
405 }
406
407 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec != MEM_REC_CNT)
408 {
409 ps_op->s_ivd_init_op_t.u4_error_code |= 1
410 << IVD_UNSUPPORTEDPARAM;
411 ps_op->s_ivd_init_op_t.u4_error_code |=
412 IVD_INIT_DEC_NOT_SUFFICIENT;
413 H264_DEC_DEBUG_PRINT("\n");
414 return (IV_FAIL);
415 }
416
417 if(max_wd < H264_MIN_FRAME_WIDTH)
418 {
419 ps_op->s_ivd_init_op_t.u4_error_code |= 1
420 << IVD_UNSUPPORTEDPARAM;
421 ps_op->s_ivd_init_op_t.u4_error_code |=
422 IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
423 H264_DEC_DEBUG_PRINT("\n");
424 return (IV_FAIL);
425 }
426
427 if(max_wd > H264_MAX_FRAME_WIDTH)
428 {
429 ps_op->s_ivd_init_op_t.u4_error_code |= 1
430 << IVD_UNSUPPORTEDPARAM;
431 ps_op->s_ivd_init_op_t.u4_error_code |=
432 IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
433 H264_DEC_DEBUG_PRINT("\n");
434 return (IV_FAIL);
435 }
436
437 if(max_ht < H264_MIN_FRAME_HEIGHT)
438 {
439 ps_op->s_ivd_init_op_t.u4_error_code |= 1
440 << IVD_UNSUPPORTEDPARAM;
441 ps_op->s_ivd_init_op_t.u4_error_code |=
442 IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
443 H264_DEC_DEBUG_PRINT("\n");
444 return (IV_FAIL);
445 }
446
447 if((max_ht * max_wd)
448 > (H264_MAX_FRAME_HEIGHT * H264_MAX_FRAME_WIDTH))
449
450 {
451 ps_op->s_ivd_init_op_t.u4_error_code |= 1
452 << IVD_UNSUPPORTEDPARAM;
453 ps_op->s_ivd_init_op_t.u4_error_code |=
454 IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
455 H264_DEC_DEBUG_PRINT("\n");
456 return (IV_FAIL);
457 }
458
459 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location)
460 {
461 ps_op->s_ivd_init_op_t.u4_error_code |= 1
462 << IVD_UNSUPPORTEDPARAM;
463 ps_op->s_ivd_init_op_t.u4_error_code |=
464 IVD_NUM_REC_NOT_SUFFICIENT;
465 H264_DEC_DEBUG_PRINT("\n");
466 return (IV_FAIL);
467 }
468
469 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P)
470 && (ps_ip->s_ivd_init_ip_t.e_output_format
471 != IV_YUV_422ILE)
472 && (ps_ip->s_ivd_init_ip_t.e_output_format
473 != IV_RGB_565)
474 && (ps_ip->s_ivd_init_ip_t.e_output_format
475 != IV_YUV_420SP_UV)
476 && (ps_ip->s_ivd_init_ip_t.e_output_format
477 != IV_YUV_420SP_VU))
478 {
479 ps_op->s_ivd_init_op_t.u4_error_code |= 1
480 << IVD_UNSUPPORTEDPARAM;
481 ps_op->s_ivd_init_op_t.u4_error_code |=
482 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
483 H264_DEC_DEBUG_PRINT("\n");
484 return (IV_FAIL);
485 }
486
487 /* verify number of mem records */
488 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < MEM_REC_CNT)
489 {
490 ps_op->s_ivd_init_op_t.u4_error_code |= 1
491 << IVD_UNSUPPORTEDPARAM;
492 ps_op->s_ivd_init_op_t.u4_error_code |=
493 IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT;
494 H264_DEC_DEBUG_PRINT("\n");
495 return IV_FAIL;
496 }
497
498 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location;
499 /* check memrecords sizes are correct */
500 for(i = 0; i < ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
501 {
502 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
503 {
504 ps_op->s_ivd_init_op_t.u4_error_code |= 1
505 << IVD_UNSUPPORTEDPARAM;
506 ps_op->s_ivd_init_op_t.u4_error_code |=
507 IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
508 H264_DEC_DEBUG_PRINT("i: %d\n", i);
509 return IV_FAIL;
510 }
511 /* check memrecords pointers are not NULL */
512
513 if(ps_mem_rec[i].pv_base == NULL)
514 {
515
516 ps_op->s_ivd_init_op_t.u4_error_code |= 1
517 << IVD_UNSUPPORTEDPARAM;
518 ps_op->s_ivd_init_op_t.u4_error_code |=
519 IVD_INIT_DEC_MEM_REC_BASE_NULL;
520 H264_DEC_DEBUG_PRINT("i: %d\n", i);
521 return IV_FAIL;
522
523 }
524
525 }
526
527 /* verify memtabs for overlapping regions */
528 {
529 void *start[MEM_REC_CNT];
530 void *end[MEM_REC_CNT];
531
532 start[0] = (void *)(ps_mem_rec[0].pv_base);
533 end[0] = (void *)((UWORD8 *)ps_mem_rec[0].pv_base
534 + ps_mem_rec[0].u4_mem_size - 1);
535 for(i = 1; i < MEM_REC_CNT; i++)
536 {
537 /* This array is populated to check memtab overlapp */
538 start[i] = (void *)(ps_mem_rec[i].pv_base);
539 end[i] = (void *)((UWORD8 *)ps_mem_rec[i].pv_base
540 + ps_mem_rec[i].u4_mem_size - 1);
541
542 for(j = 0; j < i; j++)
543 {
544 if((start[i] >= start[j]) && (start[i] <= end[j]))
545 {
546 ps_op->s_ivd_init_op_t.u4_error_code |= 1
547 << IVD_UNSUPPORTEDPARAM;
548 ps_op->s_ivd_init_op_t.u4_error_code |=
549 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
550 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j);
551 return IV_FAIL;
552 }
553
554 if((end[i] >= start[j]) && (end[i] <= end[j]))
555 {
556 ps_op->s_ivd_init_op_t.u4_error_code |= 1
557 << IVD_UNSUPPORTEDPARAM;
558 ps_op->s_ivd_init_op_t.u4_error_code |=
559 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
560 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j);
561 return IV_FAIL;
562 }
563
564 if((start[i] < start[j]) && (end[i] > end[j]))
565 {
566 ps_op->s_ivd_init_op_t.u4_error_code |= 1
567 << IVD_UNSUPPORTEDPARAM;
568 ps_op->s_ivd_init_op_t.u4_error_code |=
569 IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
570 H264_DEC_DEBUG_PRINT("i: %d, j: %d\n", i, j);
571 return IV_FAIL;
572 }
573 }
574
575 }
576 }
577
578 {
579 iv_mem_rec_t mem_rec_ittiam_api[MEM_REC_CNT];
580 ih264d_fill_mem_rec_ip_t s_fill_mem_rec_ip;
581 ih264d_fill_mem_rec_op_t s_fill_mem_rec_op;
582 IV_API_CALL_STATUS_T e_status;
583
584 UWORD32 i;
585 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd =
586 IV_CMD_FILL_NUM_MEM_REC;
587 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location =
588 mem_rec_ittiam_api;
589 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd =
590 max_wd;
591 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht =
592 max_ht;
593
594 if(ps_ip->s_ivd_init_ip_t.u4_size
595 > offsetof(ih264d_init_ip_t, i4_level))
596 {
597 s_fill_mem_rec_ip.i4_level = ps_ip->i4_level;
598 }
599 else
600 {
601 s_fill_mem_rec_ip.i4_level = H264_LEVEL_3_1;
602 }
603
604 if(ps_ip->s_ivd_init_ip_t.u4_size
605 > offsetof(ih264d_init_ip_t, u4_num_ref_frames))
606 {
607 s_fill_mem_rec_ip.u4_num_ref_frames =
608 ps_ip->u4_num_ref_frames;
609 }
610 else
611 {
612 s_fill_mem_rec_ip.u4_num_ref_frames =
613 (H264_MAX_REF_PICS + 1);
614 }
615
616 if(ps_ip->s_ivd_init_ip_t.u4_size
617 > offsetof(ih264d_init_ip_t,
618 u4_num_reorder_frames))
619 {
620 s_fill_mem_rec_ip.u4_num_reorder_frames =
621 ps_ip->u4_num_reorder_frames;
622 }
623 else
624 {
625 s_fill_mem_rec_ip.u4_num_reorder_frames = (H264_MAX_REF_PICS
626 + 1);
627 }
628
629 if(ps_ip->s_ivd_init_ip_t.u4_size
630 > offsetof(ih264d_init_ip_t,
631 u4_num_extra_disp_buf))
632 {
633 s_fill_mem_rec_ip.u4_num_extra_disp_buf =
634 ps_ip->u4_num_extra_disp_buf;
635 }
636 else
637 {
638 s_fill_mem_rec_ip.u4_num_extra_disp_buf = 0;
639 }
640
641 if(ps_ip->s_ivd_init_ip_t.u4_size
642 > offsetof(ih264d_init_ip_t, u4_share_disp_buf))
643 {
644#ifndef LOGO_EN
645 s_fill_mem_rec_ip.u4_share_disp_buf =
646 ps_ip->u4_share_disp_buf;
647#else
648 s_fill_mem_rec_ip.u4_share_disp_buf = 0;
649#endif
650 }
651 else
652 {
653 s_fill_mem_rec_ip.u4_share_disp_buf = 0;
654 }
655
656 s_fill_mem_rec_ip.e_output_format =
657 ps_ip->s_ivd_init_ip_t.e_output_format;
658
659 if((s_fill_mem_rec_ip.e_output_format != IV_YUV_420P)
660 && (s_fill_mem_rec_ip.e_output_format
661 != IV_YUV_420SP_UV)
662 && (s_fill_mem_rec_ip.e_output_format
663 != IV_YUV_420SP_VU))
664 {
665 s_fill_mem_rec_ip.u4_share_disp_buf = 0;
666 }
667
668 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size =
669 sizeof(ih264d_fill_mem_rec_ip_t);
670 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size =
671 sizeof(ih264d_fill_mem_rec_op_t);
672
673 for(i = 0; i < MEM_REC_CNT; i++)
674 mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
675
676 e_status = ih264d_api_function(NULL,
677 (void *)&s_fill_mem_rec_ip,
678 (void *)&s_fill_mem_rec_op);
679 if(IV_FAIL == e_status)
680 {
681 ps_op->s_ivd_init_op_t.u4_error_code =
682 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code;
683 H264_DEC_DEBUG_PRINT("Fail\n");
684 return (IV_FAIL);
685 }
686
687 for(i = 0; i < MEM_REC_CNT; i++)
688 {
689 if(ps_mem_rec[i].u4_mem_size
690 < mem_rec_ittiam_api[i].u4_mem_size)
691 {
692 ps_op->s_ivd_init_op_t.u4_error_code |= 1
693 << IVD_UNSUPPORTEDPARAM;
694 ps_op->s_ivd_init_op_t.u4_error_code |=
695 IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE;
696 H264_DEC_DEBUG_PRINT("i: %d \n", i);
697 return IV_FAIL;
698 }
699 if(ps_mem_rec[i].u4_mem_alignment
700 != mem_rec_ittiam_api[i].u4_mem_alignment)
701 {
702 ps_op->s_ivd_init_op_t.u4_error_code |= 1
703 << IVD_UNSUPPORTEDPARAM;
704 ps_op->s_ivd_init_op_t.u4_error_code |=
705 IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
706 H264_DEC_DEBUG_PRINT("i: %d \n", i);
707 return IV_FAIL;
708 }
709 if(ps_mem_rec[i].e_mem_type
710 != mem_rec_ittiam_api[i].e_mem_type)
711 {
712 UWORD32 check = IV_SUCCESS;
713 UWORD32 diff = mem_rec_ittiam_api[i].e_mem_type
714 - ps_mem_rec[i].e_mem_type;
715
716 if((ps_mem_rec[i].e_mem_type
717 <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM)
718 && (mem_rec_ittiam_api[i].e_mem_type
719 >= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM))
720 {
721 check = IV_FAIL;
722 }
723 if(3 != MOD(mem_rec_ittiam_api[i].e_mem_type, 4))
724 {
725 /*
726 * It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM
727 */
728 if((diff < 1) || (diff > 3))
729 {
730 // Difference between 1 and 3 is okay for all cases other than the two filtered
731 // with the MOD condition above
732 check = IV_FAIL;
733 }
734 }
735 else
736 {
737 if(diff == 1)
738 {
739 /*
740 * This particular case is when codec asked for External Persistent, but got
741 * Internal Scratch.
742 */
743 check = IV_FAIL;
744 }
745 if((diff != 2) && (diff != 3))
746 {
747 check = IV_FAIL;
748 }
749 }
750 if(check == IV_FAIL)
751 {
752 ps_op->s_ivd_init_op_t.u4_error_code |= 1
753 << IVD_UNSUPPORTEDPARAM;
754 ps_op->s_ivd_init_op_t.u4_error_code |=
755 IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE;
756 H264_DEC_DEBUG_PRINT("i: %d \n", i);
757 return IV_FAIL;
758 }
759 }
760 }
761 }
762
763 }
764 break;
765
766 case IVD_CMD_GET_DISPLAY_FRAME:
767 {
768 ih264d_get_display_frame_ip_t *ps_ip =
769 (ih264d_get_display_frame_ip_t *)pv_api_ip;
770 ih264d_get_display_frame_op_t *ps_op =
771 (ih264d_get_display_frame_op_t *)pv_api_op;
772
773 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
774
775 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size
776 != sizeof(ih264d_get_display_frame_ip_t))
777 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size
778 != sizeof(ivd_get_display_frame_ip_t)))
779 {
780 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
781 << IVD_UNSUPPORTEDPARAM;
782 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
783 IVD_IP_API_STRUCT_SIZE_INCORRECT;
784 return (IV_FAIL);
785 }
786
787 if((ps_op->s_ivd_get_display_frame_op_t.u4_size
788 != sizeof(ih264d_get_display_frame_op_t))
789 && (ps_op->s_ivd_get_display_frame_op_t.u4_size
790 != sizeof(ivd_get_display_frame_op_t)))
791 {
792 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
793 << IVD_UNSUPPORTEDPARAM;
794 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
795 IVD_OP_API_STRUCT_SIZE_INCORRECT;
796 return (IV_FAIL);
797 }
798 }
799 break;
800
801 case IVD_CMD_REL_DISPLAY_FRAME:
802 {
803 ih264d_rel_display_frame_ip_t *ps_ip =
804 (ih264d_rel_display_frame_ip_t *)pv_api_ip;
805 ih264d_rel_display_frame_op_t *ps_op =
806 (ih264d_rel_display_frame_op_t *)pv_api_op;
807
808 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
809
810 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
811 != sizeof(ih264d_rel_display_frame_ip_t))
812 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
813 != sizeof(ivd_rel_display_frame_ip_t)))
814 {
815 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
816 << IVD_UNSUPPORTEDPARAM;
817 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
818 IVD_IP_API_STRUCT_SIZE_INCORRECT;
819 return (IV_FAIL);
820 }
821
822 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size
823 != sizeof(ih264d_rel_display_frame_op_t))
824 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size
825 != sizeof(ivd_rel_display_frame_op_t)))
826 {
827 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
828 << IVD_UNSUPPORTEDPARAM;
829 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
830 IVD_OP_API_STRUCT_SIZE_INCORRECT;
831 return (IV_FAIL);
832 }
833
834 }
835 break;
836
837 case IVD_CMD_SET_DISPLAY_FRAME:
838 {
839 ih264d_set_display_frame_ip_t *ps_ip =
840 (ih264d_set_display_frame_ip_t *)pv_api_ip;
841 ih264d_set_display_frame_op_t *ps_op =
842 (ih264d_set_display_frame_op_t *)pv_api_op;
843 UWORD32 j;
844
845 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
846
847 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size
848 != sizeof(ih264d_set_display_frame_ip_t))
849 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size
850 != sizeof(ivd_set_display_frame_ip_t)))
851 {
852 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
853 << IVD_UNSUPPORTEDPARAM;
854 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
855 IVD_IP_API_STRUCT_SIZE_INCORRECT;
856 return (IV_FAIL);
857 }
858
859 if((ps_op->s_ivd_set_display_frame_op_t.u4_size
860 != sizeof(ih264d_set_display_frame_op_t))
861 && (ps_op->s_ivd_set_display_frame_op_t.u4_size
862 != sizeof(ivd_set_display_frame_op_t)))
863 {
864 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
865 << IVD_UNSUPPORTEDPARAM;
866 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
867 IVD_OP_API_STRUCT_SIZE_INCORRECT;
868 return (IV_FAIL);
869 }
870
871 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
872 {
873 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
874 << IVD_UNSUPPORTEDPARAM;
875 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
876 IVD_DISP_FRM_ZERO_OP_BUFS;
877 return IV_FAIL;
878 }
879
880 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs;
881 j++)
882 {
883 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs
884 == 0)
885 {
886 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
887 << IVD_UNSUPPORTEDPARAM;
888 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
889 IVD_DISP_FRM_ZERO_OP_BUFS;
890 return IV_FAIL;
891 }
892
893 for(i = 0;
894 i
895 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;
896 i++)
897 {
898 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i]
899 == NULL)
900 {
901 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
902 << IVD_UNSUPPORTEDPARAM;
903 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
904 IVD_DISP_FRM_OP_BUF_NULL;
905 return IV_FAIL;
906 }
907
908 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i]
909 == 0)
910 {
911 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
912 << IVD_UNSUPPORTEDPARAM;
913 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
914 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
915 return IV_FAIL;
916 }
917 }
918 }
919 }
920 break;
921
922 case IVD_CMD_VIDEO_DECODE:
923 {
924 ih264d_video_decode_ip_t *ps_ip =
925 (ih264d_video_decode_ip_t *)pv_api_ip;
926 ih264d_video_decode_op_t *ps_op =
927 (ih264d_video_decode_op_t *)pv_api_op;
928
929 H264_DEC_DEBUG_PRINT("The input bytes is: %d",
930 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes);
931 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
932
933 if(ps_ip->s_ivd_video_decode_ip_t.u4_size
934 != sizeof(ih264d_video_decode_ip_t)&&
935 ps_ip->s_ivd_video_decode_ip_t.u4_size != offsetof(ivd_video_decode_ip_t, s_out_buffer))
936 {
937 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
938 << IVD_UNSUPPORTEDPARAM;
939 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
940 IVD_IP_API_STRUCT_SIZE_INCORRECT;
941 return (IV_FAIL);
942 }
943
944 if(ps_op->s_ivd_video_decode_op_t.u4_size
945 != sizeof(ih264d_video_decode_op_t)&&
946 ps_op->s_ivd_video_decode_op_t.u4_size != offsetof(ivd_video_decode_op_t, u4_output_present))
947 {
948 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
949 << IVD_UNSUPPORTEDPARAM;
950 ps_op->s_ivd_video_decode_op_t.u4_error_code |=
951 IVD_OP_API_STRUCT_SIZE_INCORRECT;
952 return (IV_FAIL);
953 }
954
955 }
956 break;
957
958 case IV_CMD_RETRIEVE_MEMREC:
959 {
960 ih264d_retrieve_mem_rec_ip_t *ps_ip =
961 (ih264d_retrieve_mem_rec_ip_t *)pv_api_ip;
962 ih264d_retrieve_mem_rec_op_t *ps_op =
963 (ih264d_retrieve_mem_rec_op_t *)pv_api_op;
964 iv_mem_rec_t *ps_mem_rec;
965
966 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0;
967
968 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size
969 != sizeof(ih264d_retrieve_mem_rec_ip_t))
970 {
971 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1
972 << IVD_UNSUPPORTEDPARAM;
973 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |=
974 IVD_IP_API_STRUCT_SIZE_INCORRECT;
975 return (IV_FAIL);
976 }
977
978 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size
979 != sizeof(ih264d_retrieve_mem_rec_op_t))
980 {
981 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1
982 << IVD_UNSUPPORTEDPARAM;
983 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |=
984 IVD_OP_API_STRUCT_SIZE_INCORRECT;
985 return (IV_FAIL);
986 }
987
988 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
989 /* check memrecords sizes are correct */
990 for(i = 0; i < MEM_REC_CNT; i++)
991 {
992 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
993 {
994 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1
995 << IVD_UNSUPPORTEDPARAM;
996 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |=
997 IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
998 return IV_FAIL;
999 }
1000 }
1001 }
1002 break;
1003
1004 case IVD_CMD_VIDEO_CTL:
1005 {
1006 UWORD32 *pu4_ptr_cmd;
1007 UWORD32 sub_command;
1008
1009 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
1010 pu4_ptr_cmd += 2;
1011 sub_command = *pu4_ptr_cmd;
1012
1013 switch(sub_command)
1014 {
1015 case IVD_CMD_CTL_SETPARAMS:
1016 {
1017 ih264d_ctl_set_config_ip_t *ps_ip;
1018 ih264d_ctl_set_config_op_t *ps_op;
1019 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip;
1020 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
1021
1022 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size
1023 != sizeof(ih264d_ctl_set_config_ip_t))
1024 {
1025 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
1026 << IVD_UNSUPPORTEDPARAM;
1027 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
1028 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1029 return IV_FAIL;
1030 }
1031 }
1032 //no break; is needed here
1033 case IVD_CMD_CTL_SETDEFAULT:
1034 {
1035 ih264d_ctl_set_config_op_t *ps_op;
1036 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
1037 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size
1038 != sizeof(ih264d_ctl_set_config_op_t))
1039 {
1040 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
1041 << IVD_UNSUPPORTEDPARAM;
1042 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
1043 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1044 return IV_FAIL;
1045 }
1046 }
1047 break;
1048
1049 case IVD_CMD_CTL_GETPARAMS:
1050 {
1051 ih264d_ctl_getstatus_ip_t *ps_ip;
1052 ih264d_ctl_getstatus_op_t *ps_op;
1053
1054 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip;
1055 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op;
1056 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size
1057 != sizeof(ih264d_ctl_getstatus_ip_t))
1058 {
1059 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
1060 << IVD_UNSUPPORTEDPARAM;
1061 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
1062 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1063 return IV_FAIL;
1064 }
1065 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size
1066 != sizeof(ih264d_ctl_getstatus_op_t))
1067 {
1068 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
1069 << IVD_UNSUPPORTEDPARAM;
1070 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
1071 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1072 return IV_FAIL;
1073 }
1074 }
1075 break;
1076
1077 case IVD_CMD_CTL_GETBUFINFO:
1078 {
1079 ih264d_ctl_getbufinfo_ip_t *ps_ip;
1080 ih264d_ctl_getbufinfo_op_t *ps_op;
1081 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip;
1082 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op;
1083
1084 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size
1085 != sizeof(ih264d_ctl_getbufinfo_ip_t))
1086 {
1087 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
1088 << IVD_UNSUPPORTEDPARAM;
1089 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
1090 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1091 return IV_FAIL;
1092 }
1093 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size
1094 != sizeof(ih264d_ctl_getbufinfo_op_t))
1095 {
1096 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
1097 << IVD_UNSUPPORTEDPARAM;
1098 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
1099 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1100 return IV_FAIL;
1101 }
1102 }
1103 break;
1104
1105 case IVD_CMD_CTL_GETVERSION:
1106 {
1107 ih264d_ctl_getversioninfo_ip_t *ps_ip;
1108 ih264d_ctl_getversioninfo_op_t *ps_op;
1109 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip;
1110 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op;
1111 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size
1112 != sizeof(ih264d_ctl_getversioninfo_ip_t))
1113 {
1114 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
1115 << IVD_UNSUPPORTEDPARAM;
1116 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
1117 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1118 return IV_FAIL;
1119 }
1120 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size
1121 != sizeof(ih264d_ctl_getversioninfo_op_t))
1122 {
1123 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
1124 << IVD_UNSUPPORTEDPARAM;
1125 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
1126 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1127 return IV_FAIL;
1128 }
1129 }
1130 break;
1131
1132 case IVD_CMD_CTL_FLUSH:
1133 {
1134 ih264d_ctl_flush_ip_t *ps_ip;
1135 ih264d_ctl_flush_op_t *ps_op;
1136 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip;
1137 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op;
1138 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size
1139 != sizeof(ih264d_ctl_flush_ip_t))
1140 {
1141 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
1142 << IVD_UNSUPPORTEDPARAM;
1143 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
1144 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1145 return IV_FAIL;
1146 }
1147 if(ps_op->s_ivd_ctl_flush_op_t.u4_size
1148 != sizeof(ih264d_ctl_flush_op_t))
1149 {
1150 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
1151 << IVD_UNSUPPORTEDPARAM;
1152 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
1153 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1154 return IV_FAIL;
1155 }
1156 }
1157 break;
1158
1159 case IVD_CMD_CTL_RESET:
1160 {
1161 ih264d_ctl_reset_ip_t *ps_ip;
1162 ih264d_ctl_reset_op_t *ps_op;
1163 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip;
1164 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op;
1165 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size
1166 != sizeof(ih264d_ctl_reset_ip_t))
1167 {
1168 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
1169 << IVD_UNSUPPORTEDPARAM;
1170 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
1171 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1172 return IV_FAIL;
1173 }
1174 if(ps_op->s_ivd_ctl_reset_op_t.u4_size
1175 != sizeof(ih264d_ctl_reset_op_t))
1176 {
1177 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
1178 << IVD_UNSUPPORTEDPARAM;
1179 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
1180 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1181 return IV_FAIL;
1182 }
1183 }
1184 break;
1185
1186 case IH264D_CMD_CTL_DEGRADE:
1187 {
1188 ih264d_ctl_degrade_ip_t *ps_ip;
1189 ih264d_ctl_degrade_op_t *ps_op;
1190
1191 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
1192 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
1193
1194 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t))
1195 {
1196 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1197 ps_op->u4_error_code |=
1198 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1199 return IV_FAIL;
1200 }
1201
1202 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t))
1203 {
1204 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1205 ps_op->u4_error_code |=
1206 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1207 return IV_FAIL;
1208 }
1209
1210 if((ps_ip->i4_degrade_pics < 0)
1211 || (ps_ip->i4_degrade_pics > 4)
1212 || (ps_ip->i4_nondegrade_interval < 0)
1213 || (ps_ip->i4_degrade_type < 0)
1214 || (ps_ip->i4_degrade_type > 15))
1215 {
1216 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1217 return IV_FAIL;
1218 }
1219
1220 break;
1221 }
1222
1223 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
1224 {
1225 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
1226 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
1227
1228 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
1229 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
1230
1231 if(ps_ip->u4_size
1232 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t))
1233 {
1234 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1235 ps_op->u4_error_code |=
1236 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1237 return IV_FAIL;
1238 }
1239
1240 if(ps_op->u4_size
1241 != sizeof(ih264d_ctl_get_frame_dimensions_op_t))
1242 {
1243 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1244 ps_op->u4_error_code |=
1245 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1246 return IV_FAIL;
1247 }
1248
1249 break;
1250 }
1251
1252 case IH264D_CMD_CTL_SET_NUM_CORES:
1253 {
1254 ih264d_ctl_set_num_cores_ip_t *ps_ip;
1255 ih264d_ctl_set_num_cores_op_t *ps_op;
1256
1257 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
1258 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
1259
1260 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t))
1261 {
1262 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1263 ps_op->u4_error_code |=
1264 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1265 return IV_FAIL;
1266 }
1267
1268 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t))
1269 {
1270 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1271 ps_op->u4_error_code |=
1272 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1273 return IV_FAIL;
1274 }
1275
1276 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2)
1277 && (ps_ip->u4_num_cores != 3)
1278 && (ps_ip->u4_num_cores != 4))
1279 {
1280 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1281 return IV_FAIL;
1282 }
1283 break;
1284 }
1285 case IH264D_CMD_CTL_SET_PROCESSOR:
1286 {
1287 ih264d_ctl_set_processor_ip_t *ps_ip;
1288 ih264d_ctl_set_processor_op_t *ps_op;
1289
1290 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1291 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1292
1293 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t))
1294 {
1295 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1296 ps_op->u4_error_code |=
1297 IVD_IP_API_STRUCT_SIZE_INCORRECT;
1298 return IV_FAIL;
1299 }
1300
1301 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t))
1302 {
1303 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1304 ps_op->u4_error_code |=
1305 IVD_OP_API_STRUCT_SIZE_INCORRECT;
1306 return IV_FAIL;
1307 }
1308
1309 break;
1310 }
1311 default:
1312 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
1313 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
1314 return IV_FAIL;
1315 break;
1316 }
1317 }
1318 break;
1319 }
1320
1321 return IV_SUCCESS;
1322}
1323
1324
1325/**
1326 *******************************************************************************
1327 *
1328 * @brief
1329 * Sets Processor type
1330 *
1331 * @par Description:
1332 * Sets Processor type
1333 *
1334 * @param[in] ps_codec_obj
1335 * Pointer to codec object at API level
1336 *
1337 * @param[in] pv_api_ip
1338 * Pointer to input argument structure
1339 *
1340 * @param[out] pv_api_op
1341 * Pointer to output argument structure
1342 *
1343 * @returns Status
1344 *
1345 * @remarks
1346 *
1347 *
1348 *******************************************************************************
1349 */
1350
1351WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1352{
1353 ih264d_ctl_set_processor_ip_t *ps_ip;
1354 ih264d_ctl_set_processor_op_t *ps_op;
1355 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1356
1357 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1358 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1359
1360 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
1361 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
1362
1363 ih264d_init_function_ptr(ps_codec);
1364
1365 ps_op->u4_error_code = 0;
1366 return IV_SUCCESS;
1367}
1368/*****************************************************************************/
1369/* */
1370/* Function Name : ih264d_get_num_rec */
1371/* */
1372/* Description : returns number of mem records required */
1373/* */
1374/* Inputs : pv_api_ip input api structure */
1375/* : pv_api_op output api structure */
1376/* Outputs : */
1377/* Outputs : */
1378/* Returns : void */
1379/* */
1380/* Issues : none */
1381/* */
1382/* Revision History: */
1383/* */
1384/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1385/* 22 10 2008 100356 Draft */
1386/* */
1387/*****************************************************************************/
1388WORD32 ih264d_get_num_rec(void *pv_api_ip, void *pv_api_op)
1389{
1390 iv_num_mem_rec_ip_t *ps_mem_q_ip;
1391 iv_num_mem_rec_op_t *ps_mem_q_op;
1392 ps_mem_q_ip = (iv_num_mem_rec_ip_t *)pv_api_ip;
1393 ps_mem_q_op = (iv_num_mem_rec_op_t *)pv_api_op;
1394 UNUSED(ps_mem_q_ip);
1395 ps_mem_q_op->u4_num_mem_rec = MEM_REC_CNT;
1396
1397 return IV_SUCCESS;
1398
1399}
1400
1401
1402/**************************************************************************
1403 * \if Function name : ih264d_init_decoder \endif
1404 *
1405 *
1406 * \brief
1407 * Initializes the decoder
1408 *
1409 * \param apiVersion : Version of the api being used.
1410 * \param errorHandlingMechanism : Mechanism to be used for errror handling.
1411 * \param postFilteringType: Type of post filtering operation to be used.
1412 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0].
1413 * \param uc_dispBufs: Number of Display Buffers.
1414 * \param p_NALBufAPI: Pointer to NAL Buffer API.
1415 * \param p_DispBufAPI: Pointer to Display Buffer API.
1416 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder
1417 * for memory allocation and freeing.
1418 *
1419 * \return
1420 * 0 on Success and -1 on error
1421 *
1422 **************************************************************************
1423 */
1424void ih264d_init_decoder(void * ps_dec_params)
1425{
1426 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params;
1427 dec_slice_params_t *ps_cur_slice;
1428 pocstruct_t *ps_prev_poc, *ps_cur_poc;
Harish Mahendrakar43a1cf62016-05-11 15:26:19 +0530[diff] [blame]1429 WORD32 size;
1430
1431 size = sizeof(dec_err_status_t);
1432 memset(ps_dec->ps_dec_err_status, 0, size);
1433
1434 size = sizeof(sei);
1435 memset(ps_dec->ps_sei, 0, size);
1436
1437 size = sizeof(dpb_commands_t);
1438 memset(ps_dec->ps_dpb_cmds, 0, size);
1439
1440 size = sizeof(dec_bit_stream_t);
1441 memset(ps_dec->ps_bitstrm, 0, size);
1442
1443 size = sizeof(dec_slice_params_t);
1444 memset(ps_dec->ps_cur_slice, 0, size);
1445
1446 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1447 memset(ps_dec->pv_scratch_sps_pps, 0, size);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1448
1449
1450
1451 /* Set pic_parameter_set_id to -1 */
1452
1453
1454
1455 ps_cur_slice = ps_dec->ps_cur_slice;
1456 ps_dec->init_done = 0;
1457
1458 ps_dec->u4_num_cores = 1;
1459
1460 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0;
1461
1462 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE;
1463 ps_dec->u4_app_disable_deblk_frm = 0;
1464 ps_dec->i4_degrade_type = 0;
1465 ps_dec->i4_degrade_pics = 0;
1466
1467 ps_dec->i4_app_skip_mode = IVD_SKIP_NONE;
1468 ps_dec->i4_dec_skip_mode = IVD_SKIP_NONE;
1469
1470 memset(ps_dec->ps_pps, 0,
1471 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS));
1472 memset(ps_dec->ps_sps, 0,
1473 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS));
1474
1475 /* Initialization of function pointers ih264d_deblock_picture function*/
1476
1477 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff;
1478 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff;
1479
1480 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec;
1481
1482 ps_dec->u4_num_fld_in_frm = 0;
1483
1484 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec;
1485
1486 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/
1487 ps_dec->ps_sei->u1_is_valid = 0;
1488
1489 /* decParams Initializations */
1490 ps_dec->ps_cur_pps = NULL;
1491 ps_dec->ps_cur_sps = NULL;
1492 ps_dec->u1_init_dec_flag = 0;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]1493 ps_dec->u1_first_slice_in_stream = 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1494 ps_dec->u1_first_pb_nal_in_pic = 1;
1495 ps_dec->u1_last_pic_not_decoded = 0;
1496 ps_dec->u4_app_disp_width = 0;
1497 ps_dec->i4_header_decoded = 0;
1498 ps_dec->u4_total_frames_decoded = 0;
1499
1500 ps_dec->i4_error_code = 0;
1501 ps_dec->i4_content_type = -1;
1502 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0;
1503
1504 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS;
1505 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN;
1506 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT;
1507 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME;
1508 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN;
1509
1510 ps_dec->u1_pr_sl_type = 0xFF;
1511 ps_dec->u2_mbx = 0xffff;
1512 ps_dec->u2_mby = 0;
1513 ps_dec->u2_total_mbs_coded = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1514
1515 /* POC initializations */
1516 ps_prev_poc = &ps_dec->s_prev_pic_poc;
1517 ps_cur_poc = &ps_dec->s_cur_pic_poc;
1518 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0;
1519 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0;
1520 ps_prev_poc->i4_delta_pic_order_cnt_bottom =
1521 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0;
1522 ps_prev_poc->i4_delta_pic_order_cnt[0] =
1523 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
1524 ps_prev_poc->i4_delta_pic_order_cnt[1] =
1525 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
1526 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1527 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count =
1528 0;
1529 ps_prev_poc->i4_bottom_field_order_count =
1530 ps_cur_poc->i4_bottom_field_order_count = 0;
1531 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0;
1532 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1533 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0;
1534 ps_cur_slice->u1_mmco_equalto5 = 0;
1535 ps_cur_slice->u2_frame_num = 0;
1536
1537 ps_dec->i4_max_poc = 0;
1538 ps_dec->i4_prev_max_display_seq = 0;
1539 ps_dec->u1_recon_mb_grp = 4;
1540
1541 /* Field PIC initializations */
1542 ps_dec->u1_second_field = 0;
1543 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0;
1544
1545 /* Set the cropping parameters as zero */
1546 ps_dec->u2_crop_offset_y = 0;
1547 ps_dec->u2_crop_offset_uv = 0;
1548
1549 /* The Initial Frame Rate Info is not Present */
1550 ps_dec->i4_vui_frame_rate = -1;
1551 ps_dec->i4_pic_type = -1;
1552 ps_dec->i4_frametype = -1;
1553 ps_dec->i4_content_type = -1;
1554
1555 ps_dec->u1_res_changed = 0;
1556
1557
1558 ps_dec->u1_frame_decoded_flag = 0;
1559
1560 /* Set the default frame seek mask mode */
1561 ps_dec->u4_skip_frm_mask = SKIP_NONE;
1562
1563 /********************************************************/
1564 /* Initialize CAVLC residual decoding function pointers */
1565 /********************************************************/
1566 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1;
1567 ps_dec->pf_cavlc_4x4res_block[1] =
1568 ih264d_cavlc_4x4res_block_totalcoeff_2to10;
1569 ps_dec->pf_cavlc_4x4res_block[2] =
1570 ih264d_cavlc_4x4res_block_totalcoeff_11to16;
1571
1572 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7;
1573 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8;
1574
1575 ps_dec->pf_cavlc_parse_8x8block[0] =
1576 ih264d_cavlc_parse_8x8block_none_available;
1577 ps_dec->pf_cavlc_parse_8x8block[1] =
1578 ih264d_cavlc_parse_8x8block_left_available;
1579 ps_dec->pf_cavlc_parse_8x8block[2] =
1580 ih264d_cavlc_parse_8x8block_top_available;
1581 ps_dec->pf_cavlc_parse_8x8block[3] =
1582 ih264d_cavlc_parse_8x8block_both_available;
1583
1584 /***************************************************************************/
1585 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */
1586 /***************************************************************************/
1587 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice;
1588 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice;
1589
1590 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice;
1591 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice;
1592
1593 ps_dec->pf_fill_bs_xtra_left_edge[0] =
1594 ih264d_fill_bs_xtra_left_edge_cur_frm;
1595 ps_dec->pf_fill_bs_xtra_left_edge[1] =
1596 ih264d_fill_bs_xtra_left_edge_cur_fld;
1597
1598 /* Initialize Reference Pic Buffers */
1599 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr);
1600
1601#if VERT_SCALE_UP_AND_422
1602 ps_dec->u1_vert_up_scale_flag = 1;
1603#else
1604 ps_dec->u1_vert_up_scale_flag = 0;
1605#endif
1606
1607 ps_dec->u2_prv_frame_num = 0;
1608 ps_dec->u1_top_bottom_decoded = 0;
1609 ps_dec->u1_dangling_field = 0;
1610
1611 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table;
1612
1613 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0];
1614 ps_dec->pi1_left_ref_idx_ctxt_inc =
1615 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0];
1616 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb;
1617
1618 /* ! */
1619 /* Initializing flush frame u4_flag */
1620 ps_dec->u1_flushfrm = 0;
1621
1622 {
1623 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec;
1624 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec;
1625 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec;
1626 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec;
1627 }
1628
1629 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
1630 memset(ps_dec->u4_disp_buf_mapping, 0,
1631 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1632 memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1633 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
Harish Mahendrakarcdfd7572016-05-24 13:11:51 -0700[diff] [blame]1634 memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t));
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1635
1636 ih264d_init_arch(ps_dec);
1637 ih264d_init_function_ptr(ps_dec);
1638
1639 ps_dec->init_done = 1;
1640 ps_dec->process_called = 1;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]1641
1642 ps_dec->pv_pic_buf_mgr = NULL;
1643 ps_dec->pv_mv_buf_mgr = NULL;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1644}
1645
1646/**************************************************************************
1647 * \if Function name : ih264d_init_video_decoder \endif
1648 *
1649 * \brief
1650 * Wrapper for the decoder init
1651 *
1652 * \param p_NALBufAPI: Pointer to NAL Buffer API.
1653 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder
1654 * for memory allocation and freeing.
1655 *
1656 * \return
1657 * pointer to the decparams
1658 *
1659 **************************************************************************
1660 */
1661
1662WORD32 ih264d_init_video_decoder(iv_obj_t *dec_hdl,
1663 ih264d_init_ip_t *ps_init_ip,
1664 ih264d_init_op_t *ps_init_op)
1665{
1666 dec_struct_t * ps_dec;
1667 iv_mem_rec_t *memtab;
1668 UWORD8 *pu1_extra_mem_base,*pu1_mem_base;
1669
1670 memtab = ps_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1671
1672 dec_hdl->pv_codec_handle = memtab[MEM_REC_CODEC].pv_base;
1673 ps_dec = dec_hdl->pv_codec_handle;
1674
1675 memset(ps_dec, 0, sizeof(dec_struct_t));
1676
1677 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1678 > offsetof(ih264d_init_ip_t, i4_level))
1679 {
1680 ps_dec->u4_level_at_init = ps_init_ip->i4_level;
1681 }
1682 else
1683 {
1684 ps_dec->u4_level_at_init = H264_LEVEL_3_1;
1685 }
1686
1687 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1688 > offsetof(ih264d_init_ip_t, u4_num_ref_frames))
1689 {
1690 ps_dec->u4_num_ref_frames_at_init = ps_init_ip->u4_num_ref_frames;
1691 }
1692 else
1693 {
1694 ps_dec->u4_num_ref_frames_at_init = H264_MAX_REF_PICS;
1695 }
1696
1697 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1698 > offsetof(ih264d_init_ip_t, u4_num_reorder_frames))
1699 {
1700 ps_dec->u4_num_reorder_frames_at_init =
1701 ps_init_ip->u4_num_reorder_frames;
1702 }
1703 else
1704 {
1705 ps_dec->u4_num_reorder_frames_at_init = H264_MAX_REF_PICS;
1706 }
1707
1708 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1709 > offsetof(ih264d_init_ip_t, u4_num_extra_disp_buf))
1710 {
1711 ps_dec->u4_num_extra_disp_bufs_at_init =
1712 ps_init_ip->u4_num_extra_disp_buf;
1713 }
1714 else
1715 {
1716 ps_dec->u4_num_extra_disp_bufs_at_init = 0;
1717 }
1718
1719 if(ps_init_ip->s_ivd_init_ip_t.u4_size
1720 > offsetof(ih264d_init_ip_t, u4_share_disp_buf))
1721 {
1722#ifndef LOGO_EN
1723 ps_dec->u4_share_disp_buf = ps_init_ip->u4_share_disp_buf;
1724#else
1725 ps_dec->u4_share_disp_buf = 0;
1726#endif
1727 }
1728 else
1729 {
1730 ps_dec->u4_share_disp_buf = 0;
1731 }
1732
1733 if((ps_init_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P)
1734 && (ps_init_ip->s_ivd_init_ip_t.e_output_format
1735 != IV_YUV_420SP_UV)
1736 && (ps_init_ip->s_ivd_init_ip_t.e_output_format
1737 != IV_YUV_420SP_VU))
1738 {
1739 ps_dec->u4_share_disp_buf = 0;
1740 }
1741
1742 if((ps_dec->u4_level_at_init < MIN_LEVEL_SUPPORTED)
1743 || (ps_dec->u4_level_at_init > MAX_LEVEL_SUPPORTED))
1744 {
1745 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_LEVEL_UNSUPPORTED;
1746 return (IV_FAIL);
1747 }
1748
1749 if(ps_dec->u4_num_ref_frames_at_init > H264_MAX_REF_PICS)
1750 {
1751 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF;
1752 ps_dec->u4_num_ref_frames_at_init = H264_MAX_REF_PICS;
1753 }
1754
1755 if(ps_dec->u4_num_reorder_frames_at_init > H264_MAX_REF_PICS)
1756 {
1757 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF;
1758 ps_dec->u4_num_reorder_frames_at_init = H264_MAX_REF_PICS;
1759 }
1760
1761 if(ps_dec->u4_num_extra_disp_bufs_at_init > H264_MAX_REF_PICS)
1762 {
1763 ps_init_op->s_ivd_init_op_t.u4_error_code |= ERROR_NUM_REF;
1764 ps_dec->u4_num_extra_disp_bufs_at_init = 0;
1765 }
1766
1767 if(0 == ps_dec->u4_share_disp_buf)
1768 ps_dec->u4_num_extra_disp_bufs_at_init = 0;
1769
1770 ps_dec->u4_num_disp_bufs_requested = 1;
1771
1772 ps_dec->u4_width_at_init = ps_init_ip->s_ivd_init_ip_t.u4_frm_max_wd;
1773 ps_dec->u4_height_at_init = ps_init_ip->s_ivd_init_ip_t.u4_frm_max_ht;
1774
1775 ps_dec->u4_width_at_init = ALIGN16(ps_dec->u4_width_at_init);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]1776 ps_dec->u4_height_at_init = ALIGN32(ps_dec->u4_height_at_init);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1777
1778 ps_dec->pv_dec_thread_handle = memtab[MEM_REC_THREAD_HANDLE].pv_base;
1779
1780 pu1_mem_base = memtab[MEM_REC_THREAD_HANDLE].pv_base;
1781 ps_dec->pv_bs_deblk_thread_handle = pu1_mem_base
1782 + ithread_get_handle_size();
1783
1784 ps_dec->u4_extra_mem_used = 0;
1785
1786 pu1_extra_mem_base = memtab[MEM_REC_EXTRA_MEM].pv_base;
1787
1788 ps_dec->ps_dec_err_status = (dec_err_status_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1789 ps_dec->u4_extra_mem_used += (((sizeof(dec_err_status_t) + 127) >> 7) << 7);
1790
1791 ps_dec->ps_mem_tab = memtab[MEM_REC_BACKUP].pv_base;
1792
1793 memcpy(ps_dec->ps_mem_tab, memtab, sizeof(iv_mem_rec_t) * MEM_REC_CNT);
1794
1795 ps_dec->ps_pps = memtab[MEM_REC_PPS].pv_base;
1796
1797 ps_dec->ps_sps = memtab[MEM_REC_SPS].pv_base;
1798
1799 ps_dec->ps_sei = (sei *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1800 ps_dec->u4_extra_mem_used += sizeof(sei);
1801
1802 ps_dec->ps_dpb_mgr = memtab[MEM_REC_DPB_MGR].pv_base;
1803
1804 ps_dec->ps_dpb_cmds = (dpb_commands_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1805 ps_dec->u4_extra_mem_used += sizeof(dpb_commands_t);
1806
1807 ps_dec->ps_bitstrm = (dec_bit_stream_t *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1808 ps_dec->u4_extra_mem_used += sizeof(dec_bit_stream_t);
1809
1810 ps_dec->ps_cur_slice =(dec_slice_params_t *) (pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1811 ps_dec->u4_extra_mem_used += sizeof(dec_slice_params_t);
1812
1813 ps_dec->pv_scratch_sps_pps = (void *)(pu1_extra_mem_base + ps_dec->u4_extra_mem_used);
1814
1815
1816 ps_dec->u4_extra_mem_used += MAX(sizeof(dec_seq_params_t),
1817 sizeof(dec_pic_params_t));
1818 ps_dec->ps_pred_pkd = memtab[MEM_REC_PRED_INFO_PKD].pv_base;
1819
1820
1821 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec;
1822
1823 ps_dec->pv_dec_out = (void *)ps_init_op;
1824 ps_dec->pv_dec_in = (void *)ps_init_ip;
1825
1826 ps_dec->u1_chroma_format =
1827 (UWORD8)(ps_init_ip->s_ivd_init_ip_t.e_output_format);
1828
1829
1830
1831 ih264d_init_decoder(ps_dec);
1832
1833 return (IV_SUCCESS);
1834
1835}
1836
1837
1838/*****************************************************************************/
1839/* */
1840/* Function Name : ih264d_fill_num_mem_rec */
1841/* */
1842/* Description : fills memory records */
1843/* */
1844/* Inputs : pv_api_ip input api structure */
1845/* : pv_api_op output api structure */
1846/* Outputs : */
1847/* Returns : void */
1848/* */
1849/* Issues : none */
1850/* */
1851/* Revision History: */
1852/* */
1853/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1854/* 22 10 2008 100356 Draft */
1855/* */
1856/*****************************************************************************/
1857WORD32 ih264d_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op)
1858{
1859
1860 ih264d_fill_mem_rec_ip_t *ps_mem_q_ip;
1861 ih264d_fill_mem_rec_op_t *ps_mem_q_op;
1862 WORD32 level;
1863 UWORD32 num_reorder_frames;
1864 UWORD32 num_ref_frames;
1865 UWORD32 num_extra_disp_bufs;
1866 UWORD32 u4_dpb_size_num_frames;
1867 iv_mem_rec_t *memTab;
1868
1869 UWORD32 chroma_format, u4_share_disp_buf;
1870 UWORD32 u4_total_num_mbs;
1871 UWORD32 luma_width, luma_width_in_mbs;
1872 UWORD32 luma_height, luma_height_in_mbs;
1873 UWORD32 max_dpb_size;
1874
1875 ps_mem_q_ip = (ih264d_fill_mem_rec_ip_t *)pv_api_ip;
1876 ps_mem_q_op = (ih264d_fill_mem_rec_op_t *)pv_api_op;
1877
1878 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1879 > offsetof(ih264d_fill_mem_rec_ip_t, i4_level))
1880 {
1881 level = ps_mem_q_ip->i4_level;
1882 }
1883 else
1884 {
1885 level = H264_LEVEL_3_1;
1886 }
1887
1888 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1889 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_reorder_frames))
1890 {
1891 num_reorder_frames = ps_mem_q_ip->u4_num_reorder_frames;
1892 }
1893 else
1894 {
1895 num_reorder_frames = H264_MAX_REF_PICS;
1896 }
1897
1898 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1899 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_ref_frames))
1900 {
1901 num_ref_frames = ps_mem_q_ip->u4_num_ref_frames;
1902 }
1903 else
1904 {
1905 num_ref_frames = H264_MAX_REF_PICS;
1906 }
1907
1908 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1909 > offsetof(ih264d_fill_mem_rec_ip_t, u4_num_extra_disp_buf))
1910 {
1911 num_extra_disp_bufs = ps_mem_q_ip->u4_num_extra_disp_buf;
1912 }
1913 else
1914 {
1915 num_extra_disp_bufs = 0;
1916 }
1917
1918 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1919 > offsetof(ih264d_fill_mem_rec_ip_t, u4_share_disp_buf))
1920 {
1921#ifndef LOGO_EN
1922 u4_share_disp_buf = ps_mem_q_ip->u4_share_disp_buf;
1923#else
1924 u4_share_disp_buf = 0;
1925#endif
1926 }
1927 else
1928 {
1929 u4_share_disp_buf = 0;
1930 }
1931
1932 if(ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_size
1933 > offsetof(ih264d_fill_mem_rec_ip_t, e_output_format))
1934 {
1935 chroma_format = ps_mem_q_ip->e_output_format;
1936 }
1937 else
1938 {
1939 chroma_format = -1;
1940 }
1941
1942 if((chroma_format != IV_YUV_420P) && (chroma_format != IV_YUV_420SP_UV)
1943 && (chroma_format != IV_YUV_420SP_VU))
1944 {
1945 u4_share_disp_buf = 0;
1946 }
1947 if(0 == u4_share_disp_buf)
1948 num_extra_disp_bufs = 0;
1949
1950 {
1951
1952 luma_height = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht;
1953 luma_width = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd;
1954
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]1955 luma_height = ALIGN32(luma_height);
1956 luma_width = ALIGN16(luma_width);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1957 luma_width_in_mbs = luma_width >> 4;
1958 luma_height_in_mbs = luma_height >> 4;
1959 u4_total_num_mbs = (luma_height * luma_width) >> 8;
1960 }
1961 /*
1962 * If level is lesser than 31 and the resolution required is higher,
1963 * then make the level at least 31.
1964 */
1965 if(u4_total_num_mbs > MAX_MBS_LEVEL_30 && level < H264_LEVEL_3_1)
1966 {
1967 level = H264_LEVEL_3_1;
1968 }
1969
1970 if((level < MIN_LEVEL_SUPPORTED) || (level > MAX_LEVEL_SUPPORTED))
1971 {
1972 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |=
1973 ERROR_LEVEL_UNSUPPORTED;
1974 return (IV_FAIL);
1975 }
1976
1977 if(num_ref_frames > H264_MAX_REF_PICS)
1978 {
1979 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= ERROR_NUM_REF;
1980 num_ref_frames = H264_MAX_REF_PICS;
1981 }
1982
1983 if(num_reorder_frames > H264_MAX_REF_PICS)
1984 {
1985 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= ERROR_NUM_REF;
1986 num_reorder_frames = H264_MAX_REF_PICS;
1987 }
1988 memTab = ps_mem_q_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
1989
1990 memTab[MEM_REC_IV_OBJ].u4_mem_size = sizeof(iv_obj_t);
1991 memTab[MEM_REC_IV_OBJ].u4_mem_alignment = (128 * 8) / CHAR_BIT;
1992 memTab[MEM_REC_IV_OBJ].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
1993 H264_DEC_DEBUG_PRINT("MEM_REC_IV_OBJ MEM Size = %d\n",
1994 memTab[MEM_REC_IV_OBJ].u4_mem_size);
1995
1996 memTab[MEM_REC_CODEC].u4_mem_alignment = (128 * 8) / CHAR_BIT;
1997 memTab[MEM_REC_CODEC].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
1998 memTab[MEM_REC_CODEC].u4_mem_size = sizeof(dec_struct_t);
1999
2000 {
2001 UWORD32 mvinfo_size, mv_info_size_pad;
2002 UWORD32 MVbank, MVbank_pad;
2003 UWORD32 Ysize;
2004 UWORD32 UVsize;
2005 UWORD32 one_frm_size;
2006
2007 UWORD32 extra_mem = 0;
2008
2009 UWORD32 pad_len_h, pad_len_v;
2010
2011 /*
2012 * For low_delay, use num_buf as 2 -
2013 * num_buf = (num_buf_ref) + 1;
2014 * where num_buf_ref is 1.
2015 */
2016 UWORD32 num_buf;
2017
2018 {
2019 UWORD32 num_bufs_app, num_bufs_level;
2020
2021 num_bufs_app = num_ref_frames + num_reorder_frames + 1;
2022
2023 if(num_bufs_app <= 1)
2024 num_bufs_app = 2;
2025
2026 num_bufs_level = ih264d_get_dpb_size_new(level, (luma_width >> 4),
2027 (luma_height >> 4));
2028
2029 max_dpb_size = num_bufs_level;
2030
2031 num_bufs_level = num_bufs_level * 2 + 1;
2032
2033 num_buf = MIN(num_bufs_level, num_bufs_app);
2034
2035 num_buf += num_extra_disp_bufs;
2036
2037 }
2038
2039 mvinfo_size = ((luma_width * (luma_height)) >> 4);
2040
2041 mv_info_size_pad = ((luma_width * (PAD_MV_BANK_ROW)) >> 4);
2042
2043 Ysize = ALIGN32((luma_width + (PAD_LEN_Y_H << 1)))
2044 * (luma_height + (PAD_LEN_Y_V << 2));
2045
2046
2047 UVsize = Ysize >> 2;
2048 if(u4_share_disp_buf == 1)
2049 {
2050 /* In case of buffers getting shared between application and library
2051 there is no need of reference memtabs. Instead of setting the i4_size
2052 to zero, it is reduced to a small i4_size to ensure that changes
2053 in the code are minimal */
2054
2055 if((chroma_format == IV_YUV_420P)
2056 || (chroma_format == IV_YUV_420SP_UV)
2057 || (chroma_format == IV_YUV_420SP_VU))
2058 {
2059 Ysize = 64;
2060 }
2061 if(chroma_format == IV_YUV_420SP_UV)
2062 {
2063 UVsize = 64;
2064 }
2065 }
2066
2067 one_frm_size = (((Ysize + 127) >> 7) << 7)
2068 + ((((UVsize << 1) + 127) >> 7) << 7);
2069
2070 //Note that for ARM RVDS WS the sizeof(mv_pred_t) is 16
2071
2072 /*Add memory for colocated MB*/
2073 MVbank = sizeof(mv_pred_t) * mvinfo_size;
2074 MVbank_pad = sizeof(mv_pred_t) * mv_info_size_pad;
2075
2076 MVbank = (((MVbank + 127) >> 7) << 7);
2077
2078 MVbank_pad = (((MVbank_pad + 127) >> 7) << 7);
2079
2080 memTab[MEM_REC_MVBANK].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2081 memTab[MEM_REC_MVBANK].e_mem_type =
2082 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2083 memTab[MEM_REC_MVBANK].u4_mem_size = (MVbank + MVbank_pad)
2084 * (MIN(max_dpb_size, num_ref_frames) + 1);
2085
2086
2087 memTab[MEM_REC_REF_PIC].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2088 memTab[MEM_REC_REF_PIC].e_mem_type =
2089 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2090 memTab[MEM_REC_REF_PIC].u4_mem_size = one_frm_size * num_buf;
2091
2092 }
2093
2094 memTab[MEM_REC_DEBLK_MB_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2095 memTab[MEM_REC_DEBLK_MB_INFO].e_mem_type =
2096 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2097 memTab[MEM_REC_DEBLK_MB_INFO].u4_mem_size = (((((u4_total_num_mbs
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2098 + (luma_width >> 4)) * sizeof(deblk_mb_t)) + 127) >> 7) << 7);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2099
2100 memTab[MEM_REC_NEIGHBOR_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2101 memTab[MEM_REC_NEIGHBOR_INFO].e_mem_type =
2102 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2103 memTab[MEM_REC_NEIGHBOR_INFO].u4_mem_size = sizeof(mb_neigbour_params_t)
2104 * ((luma_width + 16) >> 4) * 2 * 2;
2105 {
2106 WORD32 size;
2107 WORD32 num_entries;
2108
2109 num_entries = MIN(MAX_FRAMES, num_ref_frames);
2110 num_entries = 2 * ((2 * num_entries) + 1);
2111
2112 size = num_entries * sizeof(void *);
2113 size += PAD_MAP_IDX_POC * sizeof(void *);
2114 size *= u4_total_num_mbs;
2115 size += sizeof(dec_slice_struct_t) * u4_total_num_mbs;
2116 memTab[MEM_REC_SLICE_HDR].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2117 memTab[MEM_REC_SLICE_HDR].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2118 memTab[MEM_REC_SLICE_HDR].u4_mem_size = size;
2119 }
2120 {
2121
2122 UWORD32 u4_num_entries;
2123
2124 u4_num_entries = u4_total_num_mbs;
2125
2126 memTab[MEM_REC_MB_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2127 memTab[MEM_REC_MB_INFO].e_mem_type =
2128 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2129 memTab[MEM_REC_MB_INFO].u4_mem_size = sizeof(dec_mb_info_t)
2130 * u4_num_entries;
2131
2132 memTab[MEM_REC_PRED_INFO].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2133 memTab[MEM_REC_PRED_INFO].e_mem_type =
2134 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2135
2136 memTab[MEM_REC_PRED_INFO].u4_mem_size = sizeof(pred_info_t) * 2*32;
2137
2138 memTab[MEM_REC_COEFF_DATA].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2139 memTab[MEM_REC_COEFF_DATA].e_mem_type =
2140 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2141 memTab[MEM_REC_COEFF_DATA].u4_mem_size = MB_LUM_SIZE * sizeof(WORD16);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2142 /*For I16x16 MBs, 16 4x4 AC coeffs and 1 4x4 DC coeff TU blocks will be sent
2143 For all MBs along with 8 4x4 AC coeffs 2 2x2 DC coeff TU blocks will be sent
2144 So use 17 4x4 TU blocks for luma and 9 4x4 TU blocks for chroma */
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2145 memTab[MEM_REC_COEFF_DATA].u4_mem_size += u4_num_entries
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2146 * (MAX(17 * sizeof(tu_sblk4x4_coeff_data_t),4 * sizeof(tu_blk8x8_coeff_data_t))
2147 + 9 * sizeof(tu_sblk4x4_coeff_data_t));
2148 //32 bytes for each mb to store u1_prev_intra4x4_pred_mode and u1_rem_intra4x4_pred_mode data
2149 memTab[MEM_REC_COEFF_DATA].u4_mem_size += u4_num_entries * 32;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2150
2151 }
2152
2153 memTab[MEM_REC_SPS].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2154 memTab[MEM_REC_SPS].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2155 memTab[MEM_REC_SPS].u4_mem_size = ((sizeof(dec_seq_params_t))
2156 * MAX_NUM_SEQ_PARAMS);
2157
2158 memTab[MEM_REC_PPS].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2159 memTab[MEM_REC_PPS].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2160 memTab[MEM_REC_PPS].u4_mem_size = (sizeof(dec_pic_params_t))
2161 * MAX_NUM_PIC_PARAMS;
2162
2163 {
2164 UWORD32 u4_mem_size;
2165
2166 u4_mem_size = 0;
2167 u4_mem_size += (((sizeof(dec_err_status_t) + 127) >> 7) << 7);
2168 u4_mem_size += sizeof(sei);
2169 u4_mem_size += sizeof(dpb_commands_t);
2170 u4_mem_size += sizeof(dec_bit_stream_t);
2171 u4_mem_size += sizeof(dec_slice_params_t);
2172 u4_mem_size += MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
2173
2174 memTab[MEM_REC_EXTRA_MEM].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2175 memTab[MEM_REC_EXTRA_MEM].e_mem_type =
2176 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2177 memTab[MEM_REC_EXTRA_MEM].u4_mem_size = u4_mem_size;
2178 }
2179
2180 {
2181
2182 UWORD32 u4_mem_size;
2183
2184 u4_mem_size = 0;
2185 u4_mem_size += ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) * sizeof(void *));
2186 u4_mem_size = ALIGN64(u4_mem_size);
2187 u4_mem_size += (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS);
2188 u4_mem_size = ALIGN64(u4_mem_size);
2189 u4_mem_size += sizeof(ctxt_inc_mb_info_t);
2190 u4_mem_size = ALIGN64(u4_mem_size);
2191 u4_mem_size += sizeof(UWORD32) * (MAX_REF_BUFS * MAX_REF_BUFS);
2192 u4_mem_size = ALIGN64(u4_mem_size);
2193
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2194 u4_mem_size += MAX_REF_BUF_SIZE * 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2195 u4_mem_size = ALIGN64(u4_mem_size);
2196 u4_mem_size += ((sizeof(WORD16)) * PRED_BUFFER_WIDTH
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2197 * PRED_BUFFER_HEIGHT * 2);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2198 u4_mem_size = ALIGN64(u4_mem_size);
2199 u4_mem_size += sizeof(UWORD8) * (MB_LUM_SIZE);
2200 u4_mem_size = ALIGN64(u4_mem_size);
2201 u4_mem_size += sizeof(parse_pmbarams_t) * luma_width_in_mbs; //Max recon mb group*/
2202 u4_mem_size = ALIGN64(u4_mem_size);
2203 u4_mem_size += (sizeof(parse_part_params_t) * luma_width_in_mbs) << 4; //Max recon mb group*/
2204 u4_mem_size = ALIGN64(u4_mem_size);
2205
2206 u4_mem_size += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t);
2207 u4_mem_size = ALIGN64(u4_mem_size);
2208 u4_mem_size += 2 * MAX_REF_BUFS * sizeof(struct pic_buffer_t);
2209 u4_mem_size = ALIGN64(u4_mem_size);
2210 u4_mem_size += (sizeof(UWORD32) * 3 * (MAX_REF_BUFS * MAX_REF_BUFS)) << 3;
2211 u4_mem_size = ALIGN64(u4_mem_size);
2212
Harish Mahendrakar74f03b62017-01-13 14:56:49 +0530[diff] [blame]2213 u4_mem_size += sizeof(UWORD32) * 2 * 3
2214 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1));
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2215 u4_mem_size = ALIGN64(u4_mem_size);
2216
2217 memTab[MEM_REC_INTERNAL_SCRATCH].u4_mem_alignment =
2218 (128 * 8) / CHAR_BIT;
2219 memTab[MEM_REC_INTERNAL_SCRATCH].e_mem_type =
2220 IV_EXTERNAL_CACHEABLE_SCRATCH_MEM;
2221 memTab[MEM_REC_INTERNAL_SCRATCH].u4_mem_size = u4_mem_size;
2222 }
2223
2224 {
2225
2226 UWORD32 u4_mem_used;
2227 UWORD32 u4_numRows = MB_SIZE << 1;
2228 UWORD32 u4_blk_wd = ((luma_width_in_mbs << 4) >> 1) + 8;
2229
2230 u4_mem_used = 0;
2231 u4_mem_used += ((luma_width_in_mbs * sizeof(deblkmb_neighbour_t)) << 1);
2232 u4_mem_used = ALIGN64(u4_mem_used);
2233 u4_mem_used += (sizeof(neighbouradd_t) << 2);
2234 u4_mem_used = ALIGN64(u4_mem_used);
2235 u4_mem_used += ((sizeof(ctxt_inc_mb_info_t))
2236 * (((luma_width_in_mbs + 1) << 1) + 1));
2237 u4_mem_used = ALIGN64(u4_mem_used);
2238
2239 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 16);
2240 u4_mem_used = ALIGN64(u4_mem_used);
2241 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 16);
2242 u4_mem_used = ALIGN64(u4_mem_used);
2243 u4_mem_used += (sizeof(mv_pred_t) * luma_width_in_mbs * 4
2244 * MV_SCRATCH_BUFS);
2245 u4_mem_used = ALIGN64(u4_mem_used);
2246 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2247 u4_mem_used = ALIGN64(u4_mem_used);
2248 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2249 u4_mem_used = ALIGN64(u4_mem_used);
2250 u4_numRows = BLK8x8SIZE << 1;
2251
2252 u4_blk_wd = ((luma_width_in_mbs << 3) >> 1) + 8;
2253
2254 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2255 u4_mem_used = ALIGN64(u4_mem_used);
2256 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2257 u4_mem_used = ALIGN64(u4_mem_used);
2258 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2259 u4_mem_used = ALIGN64(u4_mem_used);
2260 u4_mem_used += sizeof(UWORD8) * u4_numRows * u4_blk_wd;
2261 u4_mem_used += 32;
2262 u4_mem_used = ALIGN64(u4_mem_used);
2263 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2;
2264 u4_mem_used = ALIGN64(u4_mem_used);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2265 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2266 u4_mem_used = ALIGN64(u4_mem_used);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2267 u4_mem_used += sizeof(UWORD8) * (luma_width + 16) * 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2268 u4_mem_used = ALIGN64(u4_mem_used);
2269 u4_mem_used += sizeof(mb_neigbour_params_t) * (luma_width_in_mbs + 1)
2270 * luma_height_in_mbs;
2271 u4_mem_used += luma_width;
2272 u4_mem_used = ALIGN64(u4_mem_used);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2273 u4_mem_used += luma_width;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2274 u4_mem_used = ALIGN64(u4_mem_used);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2275 u4_mem_used += luma_width;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2276 u4_mem_used = ALIGN64(u4_mem_used);
2277
2278 u4_mem_used += ((MB_SIZE + 4) << 1) * PAD_LEN_Y_H;
2279 u4_mem_used = ALIGN64(u4_mem_used);
2280 u4_mem_used += ((BLK8x8SIZE + 2) << 1) * PAD_LEN_UV_H;
2281 u4_mem_used = ALIGN64(u4_mem_used);
2282 u4_mem_used += ((BLK8x8SIZE + 2) << 1) * PAD_LEN_UV_H;
2283 u4_mem_used = ALIGN64(u4_mem_used);
2284 memTab[MEM_REC_INTERNAL_PERSIST].u4_mem_alignment =
2285 (128 * 8) / CHAR_BIT;
2286 memTab[MEM_REC_INTERNAL_PERSIST].e_mem_type =
2287 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2288 memTab[MEM_REC_INTERNAL_PERSIST].u4_mem_size = u4_mem_used;
2289 }
2290
2291 memTab[MEM_REC_BITSBUF].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2292 memTab[MEM_REC_BITSBUF].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2293 memTab[MEM_REC_BITSBUF].u4_mem_size = MAX(256000, (luma_width * luma_height * 3 / 2));
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2294
2295 {
2296
2297 UWORD32 u4_thread_struct_size = ithread_get_handle_size();
2298
2299 memTab[MEM_REC_THREAD_HANDLE].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2300 memTab[MEM_REC_THREAD_HANDLE].e_mem_type =
2301 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2302 memTab[MEM_REC_THREAD_HANDLE].u4_mem_size = u4_thread_struct_size * 2;
2303
2304 }
2305
2306 memTab[MEM_REC_PARSE_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2307 memTab[MEM_REC_PARSE_MAP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2308 memTab[MEM_REC_PARSE_MAP].u4_mem_size = u4_total_num_mbs;
2309
2310 memTab[MEM_REC_PROC_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2311 memTab[MEM_REC_PROC_MAP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2312 memTab[MEM_REC_PROC_MAP].u4_mem_size = u4_total_num_mbs;
2313
2314 memTab[MEM_REC_SLICE_NUM_MAP].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2315 memTab[MEM_REC_SLICE_NUM_MAP].e_mem_type =
2316 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2317 memTab[MEM_REC_SLICE_NUM_MAP].u4_mem_size = u4_total_num_mbs
2318 * sizeof(UWORD16);
2319
2320 memTab[MEM_REC_DPB_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2321 memTab[MEM_REC_DPB_MGR].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2322 memTab[MEM_REC_DPB_MGR].u4_mem_size = sizeof(dpb_manager_t);
2323
2324 memTab[MEM_REC_BACKUP].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2325 memTab[MEM_REC_BACKUP].e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2326 memTab[MEM_REC_BACKUP].u4_mem_size = sizeof(iv_mem_rec_t) * MEM_REC_CNT;
2327
2328 {
2329
2330 UWORD32 u4_mem_size;
2331
2332 u4_mem_size = sizeof(disp_mgr_t);
2333 u4_mem_size += sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
2334 u4_mem_size += sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2);
2335
2336 memTab[MEM_REC_PIC_BUF_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2337 memTab[MEM_REC_PIC_BUF_MGR].e_mem_type =
2338 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2339 memTab[MEM_REC_PIC_BUF_MGR].u4_mem_size = u4_mem_size;
2340 }
2341
2342 {
2343 UWORD32 u4_mem_size;
2344
2345 u4_mem_size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
2346 u4_mem_size += sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2);
2347 u4_mem_size = ALIGN128(u4_mem_size);
2348 u4_mem_size += ((luma_width * luma_height) >> 4)
2349 * (MIN(max_dpb_size, num_ref_frames) + 1);
2350 memTab[MEM_REC_MV_BUF_MGR].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2351 memTab[MEM_REC_MV_BUF_MGR].e_mem_type =
2352 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2353 memTab[MEM_REC_MV_BUF_MGR].u4_mem_size = u4_mem_size;
2354 }
2355
2356 memTab[MEM_REC_PRED_INFO_PKD].u4_mem_alignment = (128 * 8) / CHAR_BIT;
2357 memTab[MEM_REC_PRED_INFO_PKD].e_mem_type =
2358 IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
2359
2360 {
2361 UWORD32 u4_num_entries;
2362 u4_num_entries = u4_total_num_mbs;
2363
2364 if(1 == num_ref_frames)
2365 u4_num_entries *= 16;
2366 else
2367 u4_num_entries *= 16 * 2;
2368
2369 memTab[MEM_REC_PRED_INFO_PKD].u4_mem_size = sizeof(pred_info_pkd_t)
2370 * u4_num_entries;
2371 }
2372
2373 ps_mem_q_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = MEM_REC_CNT;
2374
2375
2376 return IV_SUCCESS;
2377}
2378/*****************************************************************************/
2379/* */
2380/* Function Name : ih264d_clr */
2381/* */
2382/* Description : returns memory records to app */
2383/* */
2384/* Inputs :iv_obj_t decoder handle */
2385/* :pv_api_ip pointer to input structure */
2386/* :pv_api_op pointer to output structure */
2387/* Outputs : */
2388/* Returns : void */
2389/* */
2390/* Issues : none */
2391/* */
2392/* Revision History: */
2393/* */
2394/* DD MM YYYY Author(s) Changes (Describe the changes made) */
2395/* 22 10 2008 100356 Draft */
2396/* */
2397/*****************************************************************************/
2398WORD32 ih264d_clr(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2399{
2400
2401 dec_struct_t * ps_dec;
2402 iv_retrieve_mem_rec_ip_t *dec_clr_ip;
2403 iv_retrieve_mem_rec_op_t *dec_clr_op;
2404
2405 dec_clr_ip = (iv_retrieve_mem_rec_ip_t *)pv_api_ip;
2406 dec_clr_op = (iv_retrieve_mem_rec_op_t *)pv_api_op;
2407 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2408
2409 if(ps_dec->init_done != 1)
2410 {
2411 //return a proper Error Code
2412 return IV_FAIL;
2413 }
2414
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2415 if(ps_dec->pv_pic_buf_mgr)
2416 ih264_buf_mgr_free((buf_mgr_t *)ps_dec->pv_pic_buf_mgr);
2417 if(ps_dec->pv_mv_buf_mgr)
2418 ih264_buf_mgr_free((buf_mgr_t *)ps_dec->pv_mv_buf_mgr);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2419
2420 memcpy(dec_clr_ip->pv_mem_rec_location, ps_dec->ps_mem_tab,
2421 MEM_REC_CNT * (sizeof(iv_mem_rec_t)));
2422 dec_clr_op->u4_num_mem_rec_filled = MEM_REC_CNT;
2423
2424 H264_DEC_DEBUG_PRINT("The clear non-conceal num mem recs: %d\n",
2425 dec_clr_op->u4_num_mem_rec_filled);
2426
2427 return IV_SUCCESS;
2428
2429}
2430
2431/*****************************************************************************/
2432/* */
2433/* Function Name : ih264d_init */
2434/* */
2435/* Description : initializes decoder */
2436/* */
2437/* Inputs :iv_obj_t decoder handle */
2438/* :pv_api_ip pointer to input structure */
2439/* :pv_api_op pointer to output structure */
2440/* Outputs : */
2441/* Returns : void */
2442/* */
2443/* Issues : none */
2444/* */
2445/* Revision History: */
2446/* */
2447/* DD MM YYYY Author(s) Changes (Describe the changes made) */
2448/* 22 10 2008 100356 Draft */
2449/* */
2450/*****************************************************************************/
2451WORD32 ih264d_init(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2452{
2453 ih264d_init_ip_t *ps_init_ip;
2454 ih264d_init_op_t *ps_init_op;
Martin Storsjo086dd8e2015-06-13 00:35:01 +0300[diff] [blame]2455 WORD32 init_status = IV_SUCCESS;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2456 ps_init_ip = (ih264d_init_ip_t *)pv_api_ip;
2457 ps_init_op = (ih264d_init_op_t *)pv_api_op;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2458
2459 init_status = ih264d_init_video_decoder(dec_hdl, ps_init_ip, ps_init_op);
2460
2461 if(IV_SUCCESS != init_status)
2462 {
2463 return init_status;
2464 }
2465
2466 return init_status;
2467}
2468/*****************************************************************************/
2469/* */
2470/* Function Name : ih264d_map_error */
2471/* */
2472/* Description : Maps error codes to IVD error groups */
2473/* */
2474/* Inputs : */
2475/* Globals : <Does it use any global variables?> */
2476/* Outputs : */
2477/* Returns : void */
2478/* */
2479/* Issues : none */
2480/* */
2481/* Revision History: */
2482/* */
2483/* DD MM YYYY Author(s) Changes (Describe the changes made) */
2484/* 22 10 2008 100356 Draft */
2485/* */
2486/*****************************************************************************/
2487UWORD32 ih264d_map_error(UWORD32 i4_err_status)
2488{
2489 UWORD32 temp = 0;
2490
2491 switch(i4_err_status)
2492 {
2493 case ERROR_MEM_ALLOC_ISRAM_T:
2494 case ERROR_MEM_ALLOC_SDRAM_T:
2495 case ERROR_BUF_MGR:
2496 case ERROR_MB_GROUP_ASSGN_T:
2497 case ERROR_FRAME_LIMIT_OVER:
2498 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT:
2499 case ERROR_PROFILE_NOT_SUPPORTED:
2500 case ERROR_INIT_NOT_DONE:
2501 temp = 1 << IVD_FATALERROR;
2502 H264_DEC_DEBUG_PRINT("\nFatal Error\n");
2503 break;
2504
2505 case ERROR_DBP_MANAGER_T:
2506 case ERROR_GAPS_IN_FRM_NUM:
2507 case ERROR_UNKNOWN_NAL:
2508 case ERROR_INV_MB_SLC_GRP_T:
2509 case ERROR_MULTIPLE_SLC_GRP_T:
2510 case ERROR_UNKNOWN_LEVEL:
2511 case ERROR_UNAVAIL_PICBUF_T:
2512 case ERROR_UNAVAIL_MVBUF_T:
2513 case ERROR_UNAVAIL_DISPBUF_T:
2514 case ERROR_NUM_REF:
2515 case ERROR_REFIDX_ORDER_T:
2516 case ERROR_PIC0_NOT_FOUND_T:
2517 case ERROR_MB_TYPE:
2518 case ERROR_SUB_MB_TYPE:
2519 case ERROR_CBP:
2520 case ERROR_REF_IDX:
2521 case ERROR_NUM_MV:
2522 case ERROR_CHROMA_PRED_MODE:
2523 case ERROR_INTRAPRED:
2524 case ERROR_NEXT_MB_ADDRESS_T:
2525 case ERROR_MB_ADDRESS_T:
2526 case ERROR_PIC1_NOT_FOUND_T:
2527 case ERROR_CAVLC_NUM_COEFF_T:
2528 case ERROR_CAVLC_SCAN_POS_T:
2529 case ERROR_PRED_WEIGHT_TABLE_T:
2530 case ERROR_CORRUPTED_SLICE:
2531 temp = 1 << IVD_CORRUPTEDDATA;
2532 break;
2533
2534 case ERROR_NOT_SUPP_RESOLUTION:
2535 case ERROR_FEATURE_UNAVAIL:
2536 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT:
2537 temp = 1 << IVD_UNSUPPORTEDINPUT;
2538 break;
2539
2540 case ERROR_INVALID_PIC_PARAM:
2541 case ERROR_INVALID_SEQ_PARAM:
2542 case ERROR_EGC_EXCEED_32_1_T:
2543 case ERROR_EGC_EXCEED_32_2_T:
2544 case ERROR_INV_RANGE_TEV_T:
2545 case ERROR_INV_SLC_TYPE_T:
2546 case ERROR_INV_POC_TYPE_T:
2547 case ERROR_INV_RANGE_QP_T:
2548 case ERROR_INV_SPS_PPS_T:
2549 case ERROR_INV_SLICE_HDR_T:
2550 temp = 1 << IVD_CORRUPTEDHEADER;
2551 break;
2552
2553 case ERROR_EOB_FLUSHBITS_T:
2554 case ERROR_EOB_GETBITS_T:
2555 case ERROR_EOB_GETBIT_T:
2556 case ERROR_EOB_BYPASS_T:
2557 case ERROR_EOB_DECISION_T:
2558 case ERROR_EOB_TERMINATE_T:
2559 case ERROR_EOB_READCOEFF4X4CAB_T:
2560 temp = 1 << IVD_INSUFFICIENTDATA;
2561 break;
2562 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED:
2563 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH:
2564 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR;
2565 break;
2566
2567 case ERROR_DANGLING_FIELD_IN_PIC:
2568 temp = 1 << IVD_APPLIEDCONCEALMENT;
2569 break;
2570
2571 }
2572
2573 return temp;
2574
2575}
2576
2577/*****************************************************************************/
2578/* */
2579/* Function Name : ih264d_video_decode */
2580/* */
2581/* Description : handle video decode API command */
2582/* */
2583/* Inputs :iv_obj_t decoder handle */
2584/* :pv_api_ip pointer to input structure */
2585/* :pv_api_op pointer to output structure */
2586/* Outputs : */
2587/* Returns : void */
2588/* */
2589/* Issues : none */
2590/* */
2591/* Revision History: */
2592/* */
2593/* DD MM YYYY Author(s) Changes (Describe the changes made) */
2594/* 22 10 2008 100356 Draft */
2595/* */
2596/*****************************************************************************/
2597
2598WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2599{
2600 /* ! */
2601
2602 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2603
2604 WORD32 i4_err_status = 0;
2605 UWORD8 *pu1_buf = NULL;
2606 WORD32 buflen;
2607 UWORD32 u4_max_ofst, u4_length_of_start_code = 0;
2608
2609 UWORD32 bytes_consumed = 0;
2610 UWORD32 cur_slice_is_nonref = 0;
2611 UWORD32 u4_next_is_aud;
2612 UWORD32 u4_first_start_code_found = 0;
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]2613 WORD32 ret = 0,api_ret_value = IV_SUCCESS;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2614 WORD32 header_data_left = 0,frame_data_left = 0;
2615 UWORD8 *pu1_bitstrm_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2616 ivd_video_decode_ip_t *ps_dec_ip;
2617 ivd_video_decode_op_t *ps_dec_op;
Martin Storsjo086dd8e2015-06-13 00:35:01 +0300[diff] [blame]2618
2619 ithread_set_name((void*)"Parse_thread");
2620
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2621 ps_dec_ip = (ivd_video_decode_ip_t *)pv_api_ip;
2622 ps_dec_op = (ivd_video_decode_op_t *)pv_api_op;
Harish Mahendrakar33db7a02016-04-20 16:13:52 +0530[diff] [blame]2623
2624 {
2625 UWORD32 u4_size;
2626 u4_size = ps_dec_op->u4_size;
2627 memset(ps_dec_op, 0, sizeof(ivd_video_decode_op_t));
2628 ps_dec_op->u4_size = u4_size;
2629 }
2630
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2631 ps_dec->pv_dec_out = ps_dec_op;
2632 ps_dec->process_called = 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2633 if(ps_dec->init_done != 1)
2634 {
2635 return IV_FAIL;
2636 }
2637
2638 /*Data memory barries instruction,so that bitstream write by the application is complete*/
2639 DATA_SYNC();
2640
2641 if(0 == ps_dec->u1_flushfrm)
2642 {
2643 if(ps_dec_ip->pv_stream_buffer == NULL)
2644 {
2645 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2646 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
2647 return IV_FAIL;
2648 }
2649 if(ps_dec_ip->u4_num_Bytes <= 0)
2650 {
2651 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2652 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV;
2653 return IV_FAIL;
2654
2655 }
2656 }
2657 ps_dec->u1_pic_decode_done = 0;
2658
2659 ps_dec_op->u4_num_bytes_consumed = 0;
2660
2661 ps_dec->ps_out_buffer = NULL;
2662
2663 if(ps_dec_ip->u4_size
2664 >= offsetof(ivd_video_decode_ip_t, s_out_buffer))
2665 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer;
2666
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2667 ps_dec->u4_fmt_conv_cur_row = 0;
2668
2669 ps_dec->u4_output_present = 0;
2670 ps_dec->s_disp_op.u4_error_code = 1;
2671 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS;
2672 ps_dec->u4_stop_threads = 0;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2673 if(0 == ps_dec->u4_share_disp_buf
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2674 && ps_dec->i4_decode_header == 0)
2675 {
2676 UWORD32 i;
2677 if(ps_dec->ps_out_buffer->u4_num_bufs == 0)
2678 {
2679 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2680 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2681 return IV_FAIL;
2682 }
2683
2684 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++)
2685 {
2686 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL)
2687 {
2688 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2689 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2690 return IV_FAIL;
2691 }
2692
2693 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0)
2694 {
2695 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2696 ps_dec_op->u4_error_code |=
2697 IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2698 return IV_FAIL;
2699 }
2700 }
2701 }
2702
2703 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT)
2704 {
2705 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER;
2706 return IV_FAIL;
2707 }
2708
2709 /* ! */
2710 ps_dec->u4_ts = ps_dec_ip->u4_ts;
2711
2712 ps_dec_op->u4_error_code = 0;
2713 ps_dec_op->e_pic_type = -1;
2714 ps_dec_op->u4_output_present = 0;
2715 ps_dec_op->u4_frame_decoded_flag = 0;
2716
2717 ps_dec->i4_frametype = -1;
2718 ps_dec->i4_content_type = -1;
Harish Mahendrakar49456122017-01-05 12:10:47 +0530[diff] [blame]2719
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2720 ps_dec->u4_slice_start_code_found = 0;
2721
2722 /* In case the deocder is not in flush mode(in shared mode),
2723 then decoder has to pick up a buffer to write current frame.
2724 Check if a frame is available in such cases */
2725
2726 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1
2727 && ps_dec->u1_flushfrm == 0)
2728 {
2729 UWORD32 i;
2730
2731 WORD32 disp_avail = 0, free_id;
2732
2733 /* Check if at least one buffer is available with the codec */
2734 /* If not then return to application with error */
2735 for(i = 0; i < ps_dec->u1_pic_bufs; i++)
2736 {
2737 if(0 == ps_dec->u4_disp_buf_mapping[i]
2738 || 1 == ps_dec->u4_disp_buf_to_be_freed[i])
2739 {
2740 disp_avail = 1;
2741 break;
2742 }
2743
2744 }
2745
2746 if(0 == disp_avail)
2747 {
2748 /* If something is queued for display wait for that buffer to be returned */
2749
2750 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2751 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
2752 return (IV_FAIL);
2753 }
2754
2755 while(1)
2756 {
2757 pic_buffer_t *ps_pic_buf;
2758 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free(
2759 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id);
2760
2761 if(ps_pic_buf == NULL)
2762 {
2763 UWORD32 i, display_queued = 0;
2764
2765 /* check if any buffer was given for display which is not returned yet */
2766 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
2767 {
2768 if(0 != ps_dec->u4_disp_buf_mapping[i])
2769 {
2770 display_queued = 1;
2771 break;
2772 }
2773 }
2774 /* If some buffer is queued for display, then codec has to singal an error and wait
2775 for that buffer to be returned.
2776 If nothing is queued for display then codec has ownership of all display buffers
2777 and it can reuse any of the existing buffers and continue decoding */
2778
2779 if(1 == display_queued)
2780 {
2781 /* If something is queued for display wait for that buffer to be returned */
2782 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2783 ps_dec_op->u4_error_code |= (1
2784 << IVD_UNSUPPORTEDPARAM);
2785 return (IV_FAIL);
2786 }
2787 }
2788 else
2789 {
2790 /* If the buffer is with display, then mark it as in use and then look for a buffer again */
2791 if(1 == ps_dec->u4_disp_buf_mapping[free_id])
2792 {
2793 ih264_buf_mgr_set_status(
2794 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2795 free_id,
2796 BUF_MGR_IO);
2797 }
2798 else
2799 {
2800 /**
2801 * Found a free buffer for present call. Release it now.
2802 * Will be again obtained later.
2803 */
2804 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2805 free_id,
2806 BUF_MGR_IO);
2807 break;
2808 }
2809 }
2810 }
2811
2812 }
2813
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2814 if(ps_dec->u1_flushfrm && ps_dec->u1_init_dec_flag)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2815 {
2816
2817 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2818 &(ps_dec->s_disp_op));
2819 if(0 == ps_dec->s_disp_op.u4_error_code)
2820 {
2821 ps_dec->u4_fmt_conv_cur_row = 0;
2822 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht;
2823 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2824 ps_dec->u4_fmt_conv_cur_row,
2825 ps_dec->u4_fmt_conv_num_rows);
2826 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2827 ps_dec->u4_output_present = 1;
2828
2829 }
2830 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2831
2832 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2833 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2834
2835 ps_dec_op->u4_new_seq = 0;
2836
2837 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
2838 ps_dec_op->u4_progressive_frame_flag =
2839 ps_dec->s_disp_op.u4_progressive_frame_flag;
2840 ps_dec_op->e_output_format =
2841 ps_dec->s_disp_op.e_output_format;
2842 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
2843 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
2844 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
2845 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2846
2847 /*In the case of flush ,since no frame is decoded set pic type as invalid*/
2848 ps_dec_op->u4_is_ref_flag = -1;
2849 ps_dec_op->e_pic_type = IV_NA_FRAME;
2850 ps_dec_op->u4_frame_decoded_flag = 0;
2851
2852 if(0 == ps_dec->s_disp_op.u4_error_code)
2853 {
2854 return (IV_SUCCESS);
2855 }
2856 else
2857 return (IV_FAIL);
2858
2859 }
2860 if(ps_dec->u1_res_changed == 1)
2861 {
2862 /*if resolution has changed and all buffers have been flushed, reset decoder*/
2863 ih264d_init_decoder(ps_dec);
2864 }
2865
2866 ps_dec->u4_prev_nal_skipped = 0;
2867
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2868 ps_dec->u2_cur_mb_addr = 0;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2869 ps_dec->u2_total_mbs_coded = 0;
2870 ps_dec->u2_cur_slice_num = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2871 ps_dec->cur_dec_mb_num = 0;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2872 ps_dec->cur_recon_mb_num = 0;
Harish Mahendrakar0b23c812017-01-16 14:43:42 +0530[diff] [blame]2873 ps_dec->u4_first_slice_in_pic = 1;
Harish Mahendrakar7a544682016-06-13 11:58:50 +0530[diff] [blame]2874 ps_dec->u1_first_pb_nal_in_pic = 1;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2875 ps_dec->u1_slice_header_done = 0;
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]2876 ps_dec->u1_dangling_field = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2877
2878 ps_dec->u4_dec_thread_created = 0;
2879 ps_dec->u4_bs_deblk_thread_created = 0;
2880 ps_dec->u4_cur_bs_mb_num = 0;
Harish Mahendrakar5e4f64c2016-06-01 13:31:45 +0530[diff] [blame]2881 ps_dec->u4_start_recon_deblk = 0;
Hamsalekha Sfe183752017-05-22 14:10:15 +0530[diff] [blame^]2882 ps_dec->u4_sps_cnt_in_process = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2883
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2884 DEBUG_THREADS_PRINTF(" Starting process call\n");
2885
2886 ps_dec->u4_pic_buf_got = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2887
2888 do
2889 {
2890
2891 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer
2892 + ps_dec_op->u4_num_bytes_consumed;
2893
2894 u4_max_ofst = ps_dec_ip->u4_num_Bytes
2895 - ps_dec_op->u4_num_bytes_consumed;
2896 pu1_bitstrm_buf = ps_dec->ps_mem_tab[MEM_REC_BITSBUF].pv_base;
2897
2898 u4_next_is_aud = 0;
2899
2900 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst,
2901 &u4_length_of_start_code,
2902 &u4_next_is_aud);
2903
2904 if(buflen == -1)
2905 buflen = 0;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]2906 /* Ignore bytes beyond the allocated size of intermediate buffer */
Harish Mahendrakar1f0ab0b2016-12-23 15:29:14 +0530[diff] [blame]2907 /* Since 8 bytes are read ahead, ensure 8 bytes are free at the
2908 end of the buffer, which will be memset to 0 after emulation prevention */
2909 buflen = MIN(buflen, (WORD32)(ps_dec->ps_mem_tab[MEM_REC_BITSBUF].u4_mem_size - 8));
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2910
2911 bytes_consumed = buflen + u4_length_of_start_code;
2912 ps_dec_op->u4_num_bytes_consumed += bytes_consumed;
2913
2914 if(buflen >= MAX_NAL_UNIT_SIZE)
2915 {
2916
2917 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op);
2918 H264_DEC_DEBUG_PRINT(
2919 "\nNal Size exceeded %d, Processing Stopped..\n",
2920 MAX_NAL_UNIT_SIZE);
2921 ps_dec->i4_error_code = 1 << IVD_CORRUPTEDDATA;
2922
2923 ps_dec_op->e_pic_type = -1;
2924 /*signal the decode thread*/
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2925 ih264d_signal_decode_thread(ps_dec);
2926 /*signal end of frame decode for curren frame*/
2927
2928 if(ps_dec->u4_pic_buf_got == 0)
2929 {
2930 if(ps_dec->i4_header_decoded == 3)
2931 {
2932 ps_dec->u2_total_mbs_coded =
2933 ps_dec->ps_cur_sps->u2_max_mb_addr + 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2934 }
2935
2936 /* close deblock thread if it is not closed yet*/
2937 if(ps_dec->u4_num_cores == 3)
2938 {
2939 ih264d_signal_bs_deblk_thread(ps_dec);
2940 }
2941 return IV_FAIL;
2942 }
2943 else
2944 {
2945 ps_dec->u1_pic_decode_done = 1;
2946 continue;
2947 }
2948 }
2949
2950 {
2951 UWORD8 u1_firstbyte, u1_nal_ref_idc;
2952
2953 if(ps_dec->i4_app_skip_mode == IVD_SKIP_B)
2954 {
2955 u1_firstbyte = *(pu1_buf + u4_length_of_start_code);
2956 u1_nal_ref_idc = (UWORD8)(NAL_REF_IDC(u1_firstbyte));
2957 if(u1_nal_ref_idc == 0)
2958 {
2959 /*skip non reference frames*/
2960 cur_slice_is_nonref = 1;
2961 continue;
2962 }
2963 else
2964 {
2965 if(1 == cur_slice_is_nonref)
2966 {
2967 /*We have encountered a referenced frame,return to app*/
2968 ps_dec_op->u4_num_bytes_consumed -=
2969 bytes_consumed;
2970 ps_dec_op->e_pic_type = IV_B_FRAME;
2971 ps_dec_op->u4_error_code =
2972 IVD_DEC_FRM_SKIPPED;
2973 ps_dec_op->u4_error_code |= (1
2974 << IVD_UNSUPPORTEDPARAM);
2975 ps_dec_op->u4_frame_decoded_flag = 0;
2976 ps_dec_op->u4_size =
2977 sizeof(ivd_video_decode_op_t);
2978 /*signal the decode thread*/
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2979 ih264d_signal_decode_thread(ps_dec);
2980 /* close deblock thread if it is not closed yet*/
2981 if(ps_dec->u4_num_cores == 3)
2982 {
2983 ih264d_signal_bs_deblk_thread(ps_dec);
2984 }
2985
2986 return (IV_FAIL);
2987 }
2988 }
2989
2990 }
2991
2992 }
2993
2994
2995 if(buflen)
2996 {
2997 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code,
2998 buflen);
2999 u4_first_start_code_found = 1;
3000
3001 }
3002 else
3003 {
3004 /*start code not found*/
3005
3006 if(u4_first_start_code_found == 0)
3007 {
3008 /*no start codes found in current process call*/
3009
3010 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND;
3011 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA;
3012
3013 if(ps_dec->u4_pic_buf_got == 0)
3014 {
3015
3016 ih264d_fill_output_struct_from_context(ps_dec,
3017 ps_dec_op);
3018
3019 ps_dec_op->u4_error_code = ps_dec->i4_error_code;
3020 ps_dec_op->u4_frame_decoded_flag = 0;
3021
3022 return (IV_FAIL);
3023 }
3024 else
3025 {
3026 ps_dec->u1_pic_decode_done = 1;
3027 continue;
3028 }
3029 }
3030 else
3031 {
3032 /* a start code has already been found earlier in the same process call*/
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3033 frame_data_left = 0;
Harish Mahendrakar2cd2f7a2017-01-16 11:26:26 +0530[diff] [blame]3034 header_data_left = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3035 continue;
3036 }
3037
3038 }
3039
3040 ps_dec->u4_return_to_app = 0;
3041 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op,
3042 pu1_bitstrm_buf, buflen);
3043 if(ret != OK)
3044 {
3045 UWORD32 error = ih264d_map_error(ret);
3046 ps_dec_op->u4_error_code = error | ret;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3047 api_ret_value = IV_FAIL;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3048
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3049 if((ret == IVD_RES_CHANGED)
3050 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED)
3051 || (ret == ERROR_UNAVAIL_PICBUF_T)
Harish Mahendrakar3a419ea2016-05-26 10:46:21 +0530[diff] [blame]3052 || (ret == ERROR_UNAVAIL_MVBUF_T)
3053 || (ret == ERROR_INV_SPS_PPS_T))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3054 {
Harish Mahendrakar3a419ea2016-05-26 10:46:21 +0530[diff] [blame]3055 ps_dec->u4_slice_start_code_found = 0;
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3056 break;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3057 }
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3058
3059 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC))
3060 {
3061 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
3062 api_ret_value = IV_FAIL;
3063 break;
3064 }
3065
3066 if(ret == ERROR_IN_LAST_SLICE_OF_PIC)
3067 {
3068 api_ret_value = IV_FAIL;
3069 break;
3070 }
3071
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3072 }
3073
3074 if(ps_dec->u4_return_to_app)
3075 {
3076 /*We have encountered a referenced frame,return to app*/
3077 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
3078 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED;
3079 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3080 ps_dec_op->u4_frame_decoded_flag = 0;
3081 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t);
3082 /*signal the decode thread*/
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3083 ih264d_signal_decode_thread(ps_dec);
3084 /* close deblock thread if it is not closed yet*/
3085 if(ps_dec->u4_num_cores == 3)
3086 {
3087 ih264d_signal_bs_deblk_thread(ps_dec);
3088 }
3089 return (IV_FAIL);
3090
3091 }
3092
3093
3094
3095 header_data_left = ((ps_dec->i4_decode_header == 1)
3096 && (ps_dec->i4_header_decoded != 3)
3097 && (ps_dec_op->u4_num_bytes_consumed
3098 < ps_dec_ip->u4_num_Bytes));
3099 frame_data_left = (((ps_dec->i4_decode_header == 0)
3100 && ((ps_dec->u1_pic_decode_done == 0)
3101 || (u4_next_is_aud == 1)))
3102 && (ps_dec_op->u4_num_bytes_consumed
3103 < ps_dec_ip->u4_num_Bytes));
3104 }
3105 while(( header_data_left == 1)||(frame_data_left == 1));
3106
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3107 if((ps_dec->u4_slice_start_code_found == 1)
3108 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3109 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3110 // last slice - missing/corruption
3111 WORD32 num_mb_skipped;
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3112 WORD32 prev_slice_err;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3113 pocstruct_t temp_poc;
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3114 WORD32 ret1;
Harish Mahendrakare1cf7ea2016-12-26 11:21:07 +0530[diff] [blame]3115 WORD32 ht_in_mbs;
3116 ht_in_mbs = ps_dec->u2_pic_ht >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag);
3117 num_mb_skipped = (ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3118 - ps_dec->u2_total_mbs_coded;
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3119
Harish Mahendrakarc7a1cf42016-02-01 15:08:19 +0530[diff] [blame]3120 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0))
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3121 prev_slice_err = 1;
3122 else
3123 prev_slice_err = 2;
3124
Harish Mahendrakarb9269052016-07-12 10:37:28 +0530[diff] [blame]3125 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u2_total_mbs_coded == 0))
3126 prev_slice_err = 1;
3127
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3128 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num,
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3129 &temp_poc, prev_slice_err);
3130
Harish Mahendrakarc2e8ffe2016-09-17 14:04:29 +0530[diff] [blame]3131 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T) ||
3132 (ret1 == ERROR_INV_SPS_PPS_T))
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3133 {
Harish Mahendrakarc2e8ffe2016-09-17 14:04:29 +0530[diff] [blame]3134 ret = ret1;
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3135 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3136 }
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3137
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3138 if((ret == IVD_RES_CHANGED)
3139 || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED)
3140 || (ret == ERROR_UNAVAIL_PICBUF_T)
Harish Mahendrakar3a419ea2016-05-26 10:46:21 +0530[diff] [blame]3141 || (ret == ERROR_UNAVAIL_MVBUF_T)
3142 || (ret == ERROR_INV_SPS_PPS_T))
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3143 {
3144
3145 /* signal the decode thread */
3146 ih264d_signal_decode_thread(ps_dec);
3147 /* close deblock thread if it is not closed yet */
3148 if(ps_dec->u4_num_cores == 3)
3149 {
3150 ih264d_signal_bs_deblk_thread(ps_dec);
3151 }
Harish Mahendrakarc7a1cf42016-02-01 15:08:19 +0530[diff] [blame]3152 /* dont consume bitstream for change in resolution case */
3153 if(ret == IVD_RES_CHANGED)
3154 {
3155 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
3156 }
Hamsalekha Se789d1d2015-07-10 13:41:00 +0530[diff] [blame]3157 return IV_FAIL;
3158 }
3159
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3160
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3161 if(ps_dec->u1_separate_parse)
3162 {
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3163 /* If Format conversion is not complete,
3164 complete it here */
3165 if(ps_dec->u4_num_cores == 2)
3166 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3167
3168 /*do deblocking of all mbs*/
3169 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3170 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3171 UWORD32 u4_num_mbs,u4_max_addr;
3172 tfr_ctxt_t s_tfr_ctxt;
3173 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt;
3174 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3175
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3176 /*BS is done for all mbs while parsing*/
3177 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1;
3178 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3179
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3180
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3181 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt,
3182 ps_dec->u2_frm_wd_in_mbs, 0);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3183
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3184
3185 u4_num_mbs = u4_max_addr
3186 - ps_dec->u4_cur_deblk_mb_num + 1;
3187
3188 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs);
3189
3190 if(u4_num_mbs != 0)
3191 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs,
3192 ps_tfr_cxt,1);
3193
3194 ps_dec->u4_start_recon_deblk = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3195
3196 }
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3197
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3198 }
3199
3200 /*signal the decode thread*/
3201 ih264d_signal_decode_thread(ps_dec);
3202 /* close deblock thread if it is not closed yet*/
3203 if(ps_dec->u4_num_cores == 3)
3204 {
3205 ih264d_signal_bs_deblk_thread(ps_dec);
3206 }
3207 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3208
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3209
3210 DATA_SYNC();
3211
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3212
3213 if((ps_dec_op->u4_error_code & 0xff)
3214 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
3215 {
3216 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
3217 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
3218 }
3219
3220//Report if header (sps and pps) has not been decoded yet
3221 if(ps_dec->i4_header_decoded != 3)
3222 {
3223 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
3224
3225 }
3226
3227 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3)
3228 {
3229 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
3230
3231 }
3232 if(ps_dec->u4_prev_nal_skipped)
3233 {
3234 /*We have encountered a referenced frame,return to app*/
3235 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED;
3236 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3237 ps_dec_op->u4_frame_decoded_flag = 0;
3238 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t);
3239 /* close deblock thread if it is not closed yet*/
3240 if(ps_dec->u4_num_cores == 3)
3241 {
3242 ih264d_signal_bs_deblk_thread(ps_dec);
3243 }
3244 return (IV_FAIL);
3245
3246 }
3247
3248 if((ps_dec->u4_slice_start_code_found == 1)
3249 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status))
3250 {
3251 /*
3252 * For field pictures, set the bottom and top picture decoded u4_flag correctly.
3253 */
3254
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3255 if(ps_dec->ps_cur_slice->u1_field_pic_flag)
3256 {
3257 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag)
3258 {
3259 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY;
3260 }
3261 else
3262 {
3263 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY;
3264 }
3265 }
Hamsalekha S77038222017-05-08 17:03:06 +0530[diff] [blame]3266 else
3267 {
3268 ps_dec->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY;
3269 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3270
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3271 /* if new frame in not found (if we are still getting slices from previous frame)
3272 * ih264d_deblock_display is not called. Such frames will not be added to reference /display
3273 */
Harish Mahendrakar31836842016-12-26 11:02:13 +0530[diff] [blame]3274 if (((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0)
3275 && (ps_dec->u4_pic_buf_got == 1))
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3276 {
3277 /* Calling Function to deblock Picture and Display */
3278 ret = ih264d_deblock_display(ps_dec);
Hamsalekha S9f0dcba2015-06-09 15:54:31 +0530[diff] [blame]3279 }
3280
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3281
3282 /*set to complete ,as we dont support partial frame decode*/
3283 if(ps_dec->i4_header_decoded == 3)
3284 {
3285 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1;
3286 }
3287
3288 /*Update the i4_frametype at the end of picture*/
3289 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
3290 {
3291 ps_dec->i4_frametype = IV_IDR_FRAME;
3292 }
3293 else if(ps_dec->i4_pic_type == B_SLICE)
3294 {
3295 ps_dec->i4_frametype = IV_B_FRAME;
3296 }
3297 else if(ps_dec->i4_pic_type == P_SLICE)
3298 {
3299 ps_dec->i4_frametype = IV_P_FRAME;
3300 }
3301 else if(ps_dec->i4_pic_type == I_SLICE)
3302 {
3303 ps_dec->i4_frametype = IV_I_FRAME;
3304 }
3305 else
3306 {
3307 H264_DEC_DEBUG_PRINT("Shouldn't come here\n");
3308 }
3309
3310 //Update the content type
3311 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag;
3312
3313 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2;
3314 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded
3315 - ps_dec->ps_cur_slice->u1_field_pic_flag;
3316
3317 }
3318
3319 /* close deblock thread if it is not closed yet*/
3320 if(ps_dec->u4_num_cores == 3)
3321 {
3322 ih264d_signal_bs_deblk_thread(ps_dec);
3323 }
3324
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3325
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3326 {
3327 /* In case the decoder is configured to run in low delay mode,
3328 * then get display buffer and then format convert.
3329 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles
3330 */
3331
3332 if((0 == ps_dec->u4_num_reorder_frames_at_init)
3333 && ps_dec->u1_init_dec_flag)
3334 {
3335
3336 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
3337 &(ps_dec->s_disp_op));
3338 if(0 == ps_dec->s_disp_op.u4_error_code)
3339 {
3340 ps_dec->u4_fmt_conv_cur_row = 0;
3341 ps_dec->u4_output_present = 1;
3342 }
3343 }
3344
3345 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op);
3346
3347 /* If Format conversion is not complete,
3348 complete it here */
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3349 if(ps_dec->u4_output_present &&
3350 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3351 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3352 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht
3353 - ps_dec->u4_fmt_conv_cur_row;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3354 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
3355 ps_dec->u4_fmt_conv_cur_row,
3356 ps_dec->u4_fmt_conv_num_rows);
3357 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
3358 }
3359
3360 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
3361 }
3362
3363 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1)
3364 {
3365 ps_dec_op->u4_progressive_frame_flag = 1;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3366 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3367 {
3368 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag)
3369 && (0 == ps_dec->ps_sps->u1_mb_aff_flag))
3370 ps_dec_op->u4_progressive_frame_flag = 0;
3371
3372 }
3373 }
3374
Harish Mahendrakar49456122017-01-05 12:10:47 +0530[diff] [blame]3375 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded)
3376 {
3377 ps_dec->u1_top_bottom_decoded = 0;
3378 }
3379 /*--------------------------------------------------------------------*/
3380 /* Do End of Pic processing. */
3381 /* Should be called only if frame was decoded in previous process call*/
3382 /*--------------------------------------------------------------------*/
3383 if(ps_dec->u4_pic_buf_got == 1)
3384 {
3385 if(1 == ps_dec->u1_last_pic_not_decoded)
3386 {
3387 ret = ih264d_end_of_pic_dispbuf_mgr(ps_dec);
3388
3389 if(ret != OK)
3390 return ret;
3391
3392 ret = ih264d_end_of_pic(ps_dec);
3393 if(ret != OK)
3394 return ret;
3395 }
3396 else
3397 {
3398 ret = ih264d_end_of_pic(ps_dec);
3399 if(ret != OK)
3400 return ret;
3401 }
3402
3403 }
3404
3405
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3406 /*Data memory barrier instruction,so that yuv write by the library is complete*/
3407 DATA_SYNC();
3408
3409 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n",
3410 ps_dec_op->u4_num_bytes_consumed);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3411 return api_ret_value;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3412}
3413
3414WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3415{
3416 char version_string[MAXVERSION_STRLEN + 1];
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3417 UWORD32 version_string_len;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3418
3419 ivd_ctl_getversioninfo_ip_t *ps_ip;
3420 ivd_ctl_getversioninfo_op_t *ps_op;
3421
3422 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip;
3423 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op;
3424 UNUSED(dec_hdl);
3425 ps_op->u4_error_code = IV_SUCCESS;
3426
3427 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
3428 CODEC_VENDOR);
3429
3430 if((WORD32)ps_ip->u4_version_buffer_size <= 0)
3431 {
3432 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
3433 return (IV_FAIL);
3434 }
3435
Martin Storsjo85a43d22015-05-20 00:12:28 +0300[diff] [blame]3436 version_string_len = strlen(version_string) + 1;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3437
3438 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3439 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3440 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3441 ps_op->u4_error_code = IV_SUCCESS;
3442 }
3443 else
3444 {
3445 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
3446 return IV_FAIL;
3447 }
3448 return (IV_SUCCESS);
3449}
3450
3451/*****************************************************************************/
3452/* */
3453/* Function Name : ih264d_get_display_frame */
3454/* */
3455/* Description : */
3456/* Inputs :iv_obj_t decoder handle */
3457/* :pv_api_ip pointer to input structure */
3458/* :pv_api_op pointer to output structure */
3459/* Outputs : */
3460/* Returns : void */
3461/* */
3462/* Issues : none */
3463/* */
3464/* Revision History: */
3465/* */
3466/* DD MM YYYY Author(s) Changes (Describe the changes made) */
3467/* 22 10 2008 100356 Draft */
3468/* */
3469/*****************************************************************************/
3470WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl,
3471 void *pv_api_ip,
3472 void *pv_api_op)
3473{
3474
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3475 UNUSED(dec_hdl);
3476 UNUSED(pv_api_ip);
3477 UNUSED(pv_api_op);
3478 // This function is no longer needed, output is returned in the process()
3479 return IV_FAIL;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3480}
3481
3482/*****************************************************************************/
3483/* */
3484/* Function Name : ih264d_set_display_frame */
3485/* */
3486/* Description : */
3487/* */
3488/* Inputs :iv_obj_t decoder handle */
3489/* :pv_api_ip pointer to input structure */
3490/* :pv_api_op pointer to output structure */
3491/* Outputs : */
3492/* Returns : void */
3493/* */
3494/* Issues : none */
3495/* */
3496/* Revision History: */
3497/* */
3498/* DD MM YYYY Author(s) Changes (Describe the changes made) */
3499/* 22 10 2008 100356 Draft */
3500/* */
3501/*****************************************************************************/
3502WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl,
3503 void *pv_api_ip,
3504 void *pv_api_op)
3505{
3506
3507 ivd_set_display_frame_ip_t *dec_disp_ip;
3508 ivd_set_display_frame_op_t *dec_disp_op;
3509
3510 UWORD32 i, num_mvbank_req;
3511 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3512
3513 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
3514 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
3515 dec_disp_op->u4_error_code = 0;
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3516 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3517 {
3518 UWORD32 level, width_mbs, height_mbs;
3519
3520 level = ps_dec->u4_level_at_init;
3521 width_mbs = ps_dec->u2_frm_wd_in_mbs;
3522 height_mbs = ps_dec->u2_frm_ht_in_mbs;
3523
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3524 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1)
3525 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames != 64))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3526 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3527 num_mvbank_req = ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3528 }
3529 else
3530 {
3531 /*if VUI is not present assume maximum possible refrence frames for the level,
3532 * as max reorder frames*/
3533 num_mvbank_req = ih264d_get_dpb_size_new(level, width_mbs,
3534 height_mbs);
3535 }
3536
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3537 num_mvbank_req += ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3538 }
3539 else
3540 {
3541 UWORD32 num_bufs_app, num_bufs_level;
3542 UWORD32 num_ref_frames, num_reorder_frames, luma_width;
3543 UWORD32 luma_height, level;
3544
3545 num_ref_frames = ps_dec->u4_num_ref_frames_at_init;
3546 num_reorder_frames = ps_dec->u4_num_reorder_frames_at_init;
3547 level = ps_dec->u4_level_at_init;
3548 luma_width = ps_dec->u4_width_at_init;
3549 luma_height = ps_dec->u4_height_at_init;
3550
3551 num_bufs_app = num_ref_frames + num_reorder_frames + 1;
3552
3553 if(num_bufs_app <= 1)
3554 num_bufs_app = 2;
3555
3556 num_bufs_level = ih264d_get_dpb_size_new(level, (luma_width >> 4),
3557 (luma_height >> 4));
3558
3559 num_bufs_level = num_bufs_level * 2 + 1;
3560
3561 num_mvbank_req = MIN(num_bufs_level, num_bufs_app);
3562
3563 num_mvbank_req += ps_dec->u4_num_extra_disp_bufs_at_init;
3564
3565 }
3566
3567 ps_dec->u4_num_disp_bufs = 0;
3568 if(ps_dec->u4_share_disp_buf)
3569 {
3570 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs;
3571 if(u4_num_bufs > MAX_DISP_BUFS_NEW)
3572 u4_num_bufs = MAX_DISP_BUFS_NEW;
3573
3574 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW);
3575 u4_num_bufs = MIN(u4_num_bufs, num_mvbank_req);
3576
3577 ps_dec->u4_num_disp_bufs = u4_num_bufs;
3578 for(i = 0; i < u4_num_bufs; i++)
3579 {
3580 ps_dec->disp_bufs[i].u4_num_bufs =
3581 dec_disp_ip->s_disp_buffer[i].u4_num_bufs;
3582
3583 ps_dec->disp_bufs[i].buf[0] =
3584 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
3585 ps_dec->disp_bufs[i].buf[1] =
3586 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
3587 ps_dec->disp_bufs[i].buf[2] =
3588 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
3589
3590 ps_dec->disp_bufs[i].u4_bufsize[0] =
3591 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0];
3592 ps_dec->disp_bufs[i].u4_bufsize[1] =
3593 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1];
3594 ps_dec->disp_bufs[i].u4_bufsize[2] =
3595 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2];
3596
3597 }
3598 }
3599 return IV_SUCCESS;
3600
3601}
3602
3603/*****************************************************************************/
3604/* */
3605/* Function Name : ih264d_set_flush_mode */
3606/* */
3607/* Description : */
3608/* */
3609/* Inputs :iv_obj_t decoder handle */
3610/* :pv_api_ip pointer to input structure */
3611/* :pv_api_op pointer to output structure */
3612/* Globals : <Does it use any global variables?> */
3613/* Outputs : */
3614/* Returns : void */
3615/* */
3616/* Issues : none */
3617/* */
3618/* Revision History: */
3619/* */
3620/* DD MM YYYY Author(s) Changes (Describe the changes made) */
3621/* 22 10 2008 100356 Draft */
3622/* */
3623/*****************************************************************************/
3624WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3625{
3626
3627 dec_struct_t * ps_dec;
3628 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op;
3629 ps_ctl_op->u4_error_code = 0;
3630
3631 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3632 UNUSED(pv_api_ip);
3633 /* ! */
3634 /* Signal flush frame control call */
3635 ps_dec->u1_flushfrm = 1;
3636
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3637 if( ps_dec->u1_init_dec_flag == 1)
3638 {
3639
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3640 ih264d_release_pics_in_dpb((void *)ps_dec,
3641 ps_dec->u1_pic_bufs);
3642 ih264d_release_display_bufs(ps_dec);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3643 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3644
3645 ps_ctl_op->u4_error_code =
3646 ((ivd_ctl_flush_op_t*)ps_dec->pv_dec_out)->u4_error_code; //verify the value
3647
3648 return IV_SUCCESS;
3649
3650}
3651
3652/*****************************************************************************/
3653/* */
3654/* Function Name : ih264d_get_status */
3655/* */
3656/* Description : */
3657/* */
3658/* Inputs :iv_obj_t decoder handle */
3659/* :pv_api_ip pointer to input structure */
3660/* :pv_api_op pointer to output structure */
3661/* Globals : <Does it use any global variables?> */
3662/* Outputs : */
3663/* Returns : void */
3664/* */
3665/* Issues : none */
3666/* */
3667/* Revision History: */
3668/* */
3669/* DD MM YYYY Author(s) Changes (Describe the changes made) */
3670/* 22 10 2008 100356 Draft */
3671/* */
3672/*****************************************************************************/
3673
3674WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3675{
3676
3677 UWORD32 i;
3678 dec_struct_t * ps_dec;
3679 UWORD32 pic_wd, pic_ht;
3680 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op;
3681 UNUSED(pv_api_ip);
3682 ps_ctl_op->u4_error_code = 0;
3683
3684 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3685
3686 pic_wd = ps_dec->u4_width_at_init;
3687 pic_ht = ps_dec->u4_height_at_init;
3688
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3689 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3690 {
3691 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height;
3692 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width;
3693
3694 if(0 == ps_dec->u4_share_disp_buf)
3695 {
3696 pic_wd = ps_dec->u2_disp_width;
3697 pic_ht = ps_dec->u2_disp_height;
3698
3699 }
3700 else
3701 {
3702 pic_wd = ps_dec->u2_frm_wd_y;
3703 pic_ht = ps_dec->u2_frm_ht_y;
3704 }
3705 }
3706 else
3707 {
3708 ps_ctl_op->u4_pic_ht = pic_wd;
3709 ps_ctl_op->u4_pic_wd = pic_ht;
3710
3711 if(1 == ps_dec->u4_share_disp_buf)
3712 {
3713 pic_wd += (PAD_LEN_Y_H << 1);
3714 pic_ht += (PAD_LEN_Y_V << 2);
3715
3716 }
3717
3718 }
3719
3720 if(ps_dec->u4_app_disp_width > pic_wd)
3721 pic_wd = ps_dec->u4_app_disp_width;
3722 if(0 == ps_dec->u4_share_disp_buf)
3723 ps_ctl_op->u4_num_disp_bufs = 1;
3724 else
3725 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3726 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3727 {
3728 UWORD32 level, width_mbs, height_mbs;
3729
3730 level = ps_dec->u4_level_at_init;
3731 width_mbs = ps_dec->u2_frm_wd_in_mbs;
3732 height_mbs = ps_dec->u2_frm_ht_in_mbs;
3733
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3734 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1)
3735 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3736 != 64))
3737 {
3738 ps_ctl_op->u4_num_disp_bufs =
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3739 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3740 }
3741 else
3742 {
3743 /*if VUI is not present assume maximum possible refrence frames for the level,
3744 * as max reorder frames*/
3745 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new(
3746 level, width_mbs, height_mbs);
3747 }
3748
3749 ps_ctl_op->u4_num_disp_bufs +=
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3750 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3751 }
3752 else
3753 {
3754 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new(
3755 ps_dec->u4_level_at_init,
3756 (ps_dec->u4_width_at_init >> 4),
3757 (ps_dec->u4_height_at_init >> 4));
3758
3759 ps_ctl_op->u4_num_disp_bufs +=
3760 ps_ctl_op->u4_num_disp_bufs;
3761
3762 ps_ctl_op->u4_num_disp_bufs =
3763 MIN(ps_ctl_op->u4_num_disp_bufs,
3764 (ps_dec->u4_num_ref_frames_at_init
3765 + ps_dec->u4_num_reorder_frames_at_init));
3766
3767 }
3768
3769 ps_ctl_op->u4_num_disp_bufs = MAX(
3770 ps_ctl_op->u4_num_disp_bufs, 6);
3771 ps_ctl_op->u4_num_disp_bufs = MIN(
3772 ps_ctl_op->u4_num_disp_bufs, 32);
3773 }
3774
3775 ps_ctl_op->u4_error_code = ps_dec->i4_error_code;
3776
3777 ps_ctl_op->u4_frame_rate = 0; //make it proper
3778 ps_ctl_op->u4_bit_rate = 0; //make it proper
3779 ps_ctl_op->e_content_type = ps_dec->i4_content_type;
3780 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format;
3781 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3782
3783 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3784 {
3785 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420;
3786 }
3787 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3788 {
3789 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
3790 }
3791 else if(ps_dec->u1_chroma_format == IV_RGB_565)
3792 {
3793 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
3794 }
3795 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3796 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3797 {
3798 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
3799 }
3800
3801 else
3802 {
3803 //Invalid chroma format; Error code may be updated, verify in testing if needed
3804 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL;
3805 return IV_FAIL;
3806 }
3807
3808 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3809 {
3810 ps_ctl_op->u4_min_in_buf_size[i] = MIN_IN_BUF_SIZE;
3811 }
3812
3813 /*!*/
3814 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3815 {
3816 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3817 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3818 >> 2;
3819 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht)
3820 >> 2;
3821 }
3822 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3823 {
3824 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3825 * 2;
3826 ps_ctl_op->u4_min_out_buf_size[1] =
3827 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3828 }
3829 else if(ps_dec->u1_chroma_format == IV_RGB_565)
3830 {
3831 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3832 * 2;
3833 ps_ctl_op->u4_min_out_buf_size[1] =
3834 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3835 }
3836 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3837 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3838 {
3839 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3840 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3841 >> 1;
3842 ps_ctl_op->u4_min_out_buf_size[2] = 0;
3843 }
3844
3845 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3846 return IV_SUCCESS;
3847}
3848
3849/*****************************************************************************/
3850/* */
3851/* Function Name : ih264d_get_buf_info */
3852/* */
3853/* Description : */
3854/* */
3855/* Inputs :iv_obj_t decoder handle */
3856/* :pv_api_ip pointer to input structure */
3857/* :pv_api_op pointer to output structure */
3858/* Globals : <Does it use any global variables?> */
3859/* Outputs : */
3860/* Returns : void */
3861/* */
3862/* Issues : none */
3863/* */
3864/* Revision History: */
3865/* */
3866/* DD MM YYYY Author(s) Changes (Describe the changes made) */
3867/* 22 10 2008 100356 Draft */
3868/* */
3869/*****************************************************************************/
3870WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3871{
3872
3873 dec_struct_t * ps_dec;
3874 UWORD8 i = 0; // Default for 420P format
3875 UWORD16 pic_wd, pic_ht;
3876 ivd_ctl_getbufinfo_op_t *ps_ctl_op =
3877 (ivd_ctl_getbufinfo_op_t*)pv_api_op;
3878 UNUSED(pv_api_ip);
3879 ps_ctl_op->u4_error_code = 0;
3880
3881 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3882
3883 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3884 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3885 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420;
3886 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3887 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
3888 else if(ps_dec->u1_chroma_format == IV_RGB_565)
3889 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
3890 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3891 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3892 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
3893
3894 else
3895 {
3896 //Invalid chroma format; Error code may be updated, verify in testing if needed
3897 return IV_FAIL;
3898 }
3899
3900 ps_ctl_op->u4_num_disp_bufs = 1;
3901
3902 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3903 {
3904 ps_ctl_op->u4_min_in_buf_size[i] = MIN_IN_BUF_SIZE;
3905 }
3906
3907 pic_wd = ps_dec->u4_width_at_init;
3908 pic_ht = ps_dec->u4_height_at_init;
3909
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3910 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3911 {
3912
3913 if(0 == ps_dec->u4_share_disp_buf)
3914 {
3915 pic_wd = ps_dec->u2_disp_width;
3916 pic_ht = ps_dec->u2_disp_height;
3917
3918 }
3919 else
3920 {
3921 pic_wd = ps_dec->u2_frm_wd_y;
3922 pic_ht = ps_dec->u2_frm_ht_y;
3923 }
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3924
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3925 }
3926 else
3927 {
3928 if(1 == ps_dec->u4_share_disp_buf)
3929 {
3930 pic_wd += (PAD_LEN_Y_H << 1);
3931 pic_ht += (PAD_LEN_Y_V << 2);
3932
3933 }
3934 }
3935
3936 if((WORD32)ps_dec->u4_app_disp_width > pic_wd)
3937 pic_wd = ps_dec->u4_app_disp_width;
3938
3939 if(0 == ps_dec->u4_share_disp_buf)
3940 ps_ctl_op->u4_num_disp_bufs = 1;
3941 else
3942 {
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3943 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3944 {
3945 UWORD32 level, width_mbs, height_mbs;
3946
3947 level = ps_dec->u4_level_at_init;
3948 width_mbs = ps_dec->u2_frm_wd_in_mbs;
3949 height_mbs = ps_dec->u2_frm_ht_in_mbs;
3950
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3951 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1)
3952 && (ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3953 != 64))
3954 {
3955 ps_ctl_op->u4_num_disp_bufs =
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3956 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3957 }
3958 else
3959 {
3960 /*if VUI is not present assume maximum possible refrence frames for the level,
3961 * as max reorder frames*/
3962 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new(
3963 level, width_mbs, height_mbs);
3964 }
3965
3966 ps_ctl_op->u4_num_disp_bufs +=
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]3967 ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]3968
3969 }
3970 else
3971 {
3972 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size_new(
3973 ps_dec->u4_level_at_init,
3974 (ps_dec->u4_width_at_init >> 4),
3975 (ps_dec->u4_height_at_init >> 4));
3976
3977 ps_ctl_op->u4_num_disp_bufs +=
3978 ps_ctl_op->u4_num_disp_bufs;
3979
3980 ps_ctl_op->u4_num_disp_bufs =
3981 MIN(ps_ctl_op->u4_num_disp_bufs,
3982 (ps_dec->u4_num_ref_frames_at_init
3983 + ps_dec->u4_num_reorder_frames_at_init));
3984
3985 }
3986
3987 ps_ctl_op->u4_num_disp_bufs = MAX(
3988 ps_ctl_op->u4_num_disp_bufs, 6);
3989 ps_ctl_op->u4_num_disp_bufs = MIN(
3990 ps_ctl_op->u4_num_disp_bufs, 32);
3991 }
3992
3993 /*!*/
3994 if(ps_dec->u1_chroma_format == IV_YUV_420P)
3995 {
3996 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3997 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3998 >> 2;
3999 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht)
4000 >> 2;
4001 }
4002 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
4003 {
4004 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
4005 * 2;
4006 ps_ctl_op->u4_min_out_buf_size[1] =
4007 ps_ctl_op->u4_min_out_buf_size[2] = 0;
4008 }
4009 else if(ps_dec->u1_chroma_format == IV_RGB_565)
4010 {
4011 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
4012 * 2;
4013 ps_ctl_op->u4_min_out_buf_size[1] =
4014 ps_ctl_op->u4_min_out_buf_size[2] = 0;
4015 }
4016 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
4017 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
4018 {
4019 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
4020 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
4021 >> 1;
4022 ps_ctl_op->u4_min_out_buf_size[2] = 0;
4023 }
4024 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
4025
4026 return IV_SUCCESS;
4027}
4028
4029/*****************************************************************************/
4030/* */
4031/* Function Name : ih264d_set_params */
4032/* */
4033/* Description : */
4034/* */
4035/* Inputs :iv_obj_t decoder handle */
4036/* :pv_api_ip pointer to input structure */
4037/* :pv_api_op pointer to output structure */
4038/* Outputs : */
4039/* Returns : void */
4040/* */
4041/* Issues : none */
4042/* */
4043/* Revision History: */
4044/* */
4045/* DD MM YYYY Author(s) Changes (Describe the changes made) */
4046/* 22 10 2008 100356 Draft */
4047/* */
4048/*****************************************************************************/
4049WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4050{
4051
4052 dec_struct_t * ps_dec;
4053 WORD32 ret = IV_SUCCESS;
4054
4055 ivd_ctl_set_config_ip_t *ps_ctl_ip =
4056 (ivd_ctl_set_config_ip_t *)pv_api_ip;
4057 ivd_ctl_set_config_op_t *ps_ctl_op =
4058 (ivd_ctl_set_config_op_t *)pv_api_op;
4059
4060 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
4061
4062 ps_dec->u4_skip_frm_mask = 0;
4063
4064 ps_ctl_op->u4_error_code = 0;
4065
4066 ps_dec->i4_app_skip_mode = ps_ctl_ip->e_frm_skip_mode;
4067
4068 /*Is it really supported test it when you so the corner testing using test app*/
4069
4070 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE)
4071 {
4072
4073 if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_P)
4074 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT;
4075 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_B)
4076 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT;
4077 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_PB)
4078 {
4079 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT;
4080 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT;
4081 }
4082 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_I)
4083 ps_dec->u4_skip_frm_mask |= 1 << I_SLC_BIT;
4084 else
4085 {
4086 //dynamic parameter not supported
4087 //Put an appropriate error code to return the error..
4088 //when you do the error code tests and after that remove this comment
4089 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
4090 ret = IV_FAIL;
4091 }
4092 }
4093
4094 if((0 != ps_dec->u4_app_disp_width)
4095 && (ps_ctl_ip->u4_disp_wd
4096 != ps_dec->u4_app_disp_width))
4097 {
4098 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
4099 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
4100 ret = IV_FAIL;
4101 }
4102 else
4103 {
4104 if((ps_ctl_ip->u4_disp_wd >= ps_dec->u2_pic_wd)/* && (ps_ctl_ip->u4_disp_wd <= ps_dec->u4_width_at_init) */)
4105 {
4106 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
4107 }
4108 else if((0 == ps_dec->i4_header_decoded) /*&& (ps_ctl_ip->u4_disp_wd <= ps_dec->u4_width_at_init)*/)
4109 {
4110 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
4111 }
4112 else if(ps_ctl_ip->u4_disp_wd == 0)
4113 {
4114 ps_dec->u4_app_disp_width = 0;
4115 }
4116 else
4117 {
4118 /*
4119 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF)
4120 * does not propogate.
4121 */
4122 ps_dec->u4_app_disp_width = 0;
4123 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
4124 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
4125 ret = IV_FAIL;
4126 }
4127 }
4128 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME)
4129 ps_dec->i4_decode_header = 0;
4130 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER)
4131 ps_dec->i4_decode_header = 1;
4132 else
4133 {
4134 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
4135 ps_dec->i4_decode_header = 1;
4136 ret = IV_FAIL;
4137 }
4138
4139 return ret;
4140
4141}
4142
4143/*****************************************************************************/
4144/* */
4145/* Function Name : ih264d_set_default_params */
4146/* */
4147/* Description : */
4148/* */
4149/* Inputs :iv_obj_t decoder handle */
4150/* :pv_api_ip pointer to input structure */
4151/* :pv_api_op pointer to output structure */
4152/* Outputs : */
4153/* Returns : void */
4154/* */
4155/* Issues : none */
4156/* */
4157/* Revision History: */
4158/* */
4159/* DD MM YYYY Author(s) Changes (Describe the changes made) */
4160/* 08 08 2011 100421 Copied from set_params */
4161/* */
4162/*****************************************************************************/
4163WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl,
4164 void *pv_api_ip,
4165 void *pv_api_op)
4166{
4167
4168 dec_struct_t * ps_dec;
4169 WORD32 ret = IV_SUCCESS;
4170
4171 ivd_ctl_set_config_op_t *ps_ctl_op =
4172 (ivd_ctl_set_config_op_t *)pv_api_op;
4173 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
4174 UNUSED(pv_api_ip);
4175
4176
4177 {
4178 ps_dec->u4_app_disp_width = 0;
4179 ps_dec->u4_skip_frm_mask = 0;
4180 ps_dec->i4_decode_header = 1;
4181
4182 ps_ctl_op->u4_error_code = 0;
4183 }
4184
4185
4186 return ret;
4187}
4188
4189/*****************************************************************************/
4190/* */
4191/* Function Name : ih264d_reset */
4192/* */
4193/* Description : */
4194/* */
4195/* Inputs :iv_obj_t decoder handle */
4196/* :pv_api_ip pointer to input structure */
4197/* :pv_api_op pointer to output structure */
4198/* Globals : <Does it use any global variables?> */
4199/* Outputs : */
4200/* Returns : void */
4201/* */
4202/* Issues : none */
4203/* */
4204/* Revision History: */
4205/* */
4206/* DD MM YYYY Author(s) Changes (Describe the changes made) */
4207/* 22 10 2008 100356 Draft */
4208/* */
4209/*****************************************************************************/
4210WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4211{
4212 dec_struct_t * ps_dec;
4213 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op;
4214 UNUSED(pv_api_ip);
4215 ps_ctl_op->u4_error_code = 0;
4216
4217 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
4218//CHECK
4219 if(ps_dec != NULL)
4220 {
4221
4222 ih264d_init_decoder(ps_dec);
4223
4224 /*
4225 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
4226 memset(ps_dec->u4_disp_buf_mapping, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
4227 memset(ps_dec->u4_disp_buf_to_be_freed, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
4228 */
4229 }
4230 else
4231 {
4232 H264_DEC_DEBUG_PRINT(
4233 "\nReset called without Initializing the decoder\n");
4234 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE;
4235 }
4236
4237 return IV_SUCCESS;
4238}
4239
4240/*****************************************************************************/
4241/* */
4242/* Function Name : ih264d_ctl */
4243/* */
4244/* Description : */
4245/* */
4246/* Inputs :iv_obj_t decoder handle */
4247/* :pv_api_ip pointer to input structure */
4248/* :pv_api_op pointer to output structure */
4249/* Outputs : */
4250/* Returns : void */
4251/* */
4252/* Issues : none */
4253/* */
4254/* Revision History: */
4255/* */
4256/* DD MM YYYY Author(s) Changes (Describe the changes made) */
4257/* 22 10 2008 100356 Draft */
4258/* */
4259/*****************************************************************************/
4260WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4261{
4262 ivd_ctl_set_config_ip_t *ps_ctl_ip;
4263 ivd_ctl_set_config_op_t *ps_ctl_op;
4264 WORD32 ret = IV_SUCCESS;
4265 UWORD32 subcommand;
4266 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4267
4268 if(ps_dec->init_done != 1)
4269 {
4270 //Return proper Error Code
4271 return IV_FAIL;
4272 }
4273 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip;
4274 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op;
4275 ps_ctl_op->u4_error_code = 0;
4276 subcommand = ps_ctl_ip->e_sub_cmd;
4277
4278 switch(subcommand)
4279 {
4280 case IVD_CMD_CTL_GETPARAMS:
4281 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip,
4282 (void *)pv_api_op);
4283 break;
4284 case IVD_CMD_CTL_SETPARAMS:
4285 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip,
4286 (void *)pv_api_op);
4287 break;
4288 case IVD_CMD_CTL_RESET:
4289 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op);
4290 break;
4291 case IVD_CMD_CTL_SETDEFAULT:
4292 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip,
4293 (void *)pv_api_op);
4294 break;
4295 case IVD_CMD_CTL_FLUSH:
4296 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip,
4297 (void *)pv_api_op);
4298 break;
4299 case IVD_CMD_CTL_GETBUFINFO:
4300 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip,
4301 (void *)pv_api_op);
4302 break;
4303 case IVD_CMD_CTL_GETVERSION:
4304 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip,
4305 (void *)pv_api_op);
4306 break;
4307 case IH264D_CMD_CTL_DEGRADE:
4308 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip,
4309 (void *)pv_api_op);
4310 break;
4311
4312 case IH264D_CMD_CTL_SET_NUM_CORES:
4313 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip,
4314 (void *)pv_api_op);
4315 break;
4316 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
4317 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip,
4318 (void *)pv_api_op);
4319 break;
4320 case IH264D_CMD_CTL_SET_PROCESSOR:
4321 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip,
4322 (void *)pv_api_op);
4323 break;
4324 default:
4325 H264_DEC_DEBUG_PRINT("\ndo nothing\n")
4326 ;
4327 break;
4328 }
4329
4330 return ret;
4331}
4332/*****************************************************************************/
4333/* */
4334/* Function Name : ih264d_rel_display_frame */
4335/* */
4336/* Description : */
4337/* */
4338/* Inputs :iv_obj_t decoder handle */
4339/* :pv_api_ip pointer to input structure */
4340/* :pv_api_op pointer to output structure */
4341/* Outputs : */
4342/* Returns : void */
4343/* */
4344/* Issues : none */
4345/* */
4346/* Revision History: */
4347/* */
4348/* DD MM YYYY Author(s) Changes (Describe the changes made) */
4349/* 22 10 2008 100356 Draft */
4350/* */
4351/*****************************************************************************/
4352WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl,
4353 void *pv_api_ip,
4354 void *pv_api_op)
4355{
4356
4357 ivd_rel_display_frame_ip_t *ps_rel_ip;
4358 ivd_rel_display_frame_op_t *ps_rel_op;
4359 UWORD32 buf_released = 0;
4360
4361 UWORD32 u4_ts = -1;
4362 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4363
4364 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
4365 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op;
4366 ps_rel_op->u4_error_code = 0;
4367 u4_ts = ps_rel_ip->u4_disp_buf_id;
4368
4369 if(0 == ps_dec->u4_share_disp_buf)
4370 {
4371 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
4372 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0;
4373 return IV_SUCCESS;
4374 }
4375
4376 if(ps_dec->pv_pic_buf_mgr != NULL)
4377 {
4378 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts])
4379 {
4380 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
4381 ps_rel_ip->u4_disp_buf_id,
4382 BUF_MGR_IO);
4383 ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
4384 buf_released = 1;
4385 }
4386 }
4387
4388 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released))
4389 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1;
4390
4391 return IV_SUCCESS;
4392}
4393
4394/**
4395 *******************************************************************************
4396 *
4397 * @brief
4398 * Sets degrade params
4399 *
4400 * @par Description:
4401 * Sets degrade params.
4402 * Refer to ih264d_ctl_degrade_ip_t definition for details
4403 *
4404 * @param[in] ps_codec_obj
4405 * Pointer to codec object at API level
4406 *
4407 * @param[in] pv_api_ip
4408 * Pointer to input argument structure
4409 *
4410 * @param[out] pv_api_op
4411 * Pointer to output argument structure
4412 *
4413 * @returns Status
4414 *
4415 * @remarks
4416 *
4417 *
4418 *******************************************************************************
4419 */
4420
4421WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
4422 void *pv_api_ip,
4423 void *pv_api_op)
4424{
4425 ih264d_ctl_degrade_ip_t *ps_ip;
4426 ih264d_ctl_degrade_op_t *ps_op;
4427 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle;
4428
4429 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
4430 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
4431
4432 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type;
4433 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval;
4434 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics;
4435
4436 ps_op->u4_error_code = 0;
4437 ps_codec->i4_degrade_pic_cnt = 0;
4438
4439 return IV_SUCCESS;
4440}
4441
4442WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
4443 void *pv_api_ip,
4444 void *pv_api_op)
4445{
4446 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
4447 ih264d_ctl_get_frame_dimensions_op_t *ps_op;
4448 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4449 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
4450
4451 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
4452
4453 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
4454 UNUSED(ps_ip);
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]4455 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4456 {
4457 disp_wd = ps_dec->u2_disp_width;
4458 disp_ht = ps_dec->u2_disp_height;
4459
4460 if(0 == ps_dec->u4_share_disp_buf)
4461 {
4462 buffer_wd = disp_wd;
4463 buffer_ht = disp_ht;
4464 }
4465 else
4466 {
4467 buffer_wd = ps_dec->u2_frm_wd_y;
4468 buffer_ht = ps_dec->u2_frm_ht_y;
4469 }
4470 }
4471 else
4472 {
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4473 disp_wd = ps_dec->u4_width_at_init;
4474 disp_ht = ps_dec->u4_height_at_init;
4475
4476 if(0 == ps_dec->u4_share_disp_buf)
4477 {
4478 buffer_wd = disp_wd;
4479 buffer_ht = disp_ht;
4480 }
4481 else
4482 {
4483 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1);
4484 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]4485 }
4486 }
4487 if(ps_dec->u4_app_disp_width > buffer_wd)
4488 buffer_wd = ps_dec->u4_app_disp_width;
4489
4490 if(0 == ps_dec->u4_share_disp_buf)
4491 {
4492 x_offset = 0;
4493 y_offset = 0;
4494 }
4495 else
4496 {
4497 y_offset = (PAD_LEN_Y_V << 1);
4498 x_offset = PAD_LEN_Y_H;
4499
4500 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid))
4501 && (0 != ps_dec->u2_crop_offset_y))
4502 {
4503 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y;
4504 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y;
4505 }
4506 }
4507
4508 ps_op->u4_disp_wd[0] = disp_wd;
4509 ps_op->u4_disp_ht[0] = disp_ht;
4510 ps_op->u4_buffer_wd[0] = buffer_wd;
4511 ps_op->u4_buffer_ht[0] = buffer_ht;
4512 ps_op->u4_x_offset[0] = x_offset;
4513 ps_op->u4_y_offset[0] = y_offset;
4514
4515 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
4516 >> 1);
4517 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
4518 >> 1);
4519 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
4520 >> 1);
4521 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
4522 >> 1);
4523 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] =
4524 (ps_op->u4_x_offset[0] >> 1);
4525 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] =
4526 (ps_op->u4_y_offset[0] >> 1);
4527
4528 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
4529 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
4530 {
4531 ps_op->u4_disp_wd[2] = 0;
4532 ps_op->u4_disp_ht[2] = 0;
4533 ps_op->u4_buffer_wd[2] = 0;
4534 ps_op->u4_buffer_ht[2] = 0;
4535 ps_op->u4_x_offset[2] = 0;
4536 ps_op->u4_y_offset[2] = 0;
4537
4538 ps_op->u4_disp_wd[1] <<= 1;
4539 ps_op->u4_buffer_wd[1] <<= 1;
4540 ps_op->u4_x_offset[1] <<= 1;
4541 }
4542
4543 return IV_SUCCESS;
4544
4545}
4546
4547WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4548{
4549 ih264d_ctl_set_num_cores_ip_t *ps_ip;
4550 ih264d_ctl_set_num_cores_op_t *ps_op;
4551 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4552
4553 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
4554 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
4555 ps_op->u4_error_code = 0;
4556 ps_dec->u4_num_cores = ps_ip->u4_num_cores;
4557 if(ps_dec->u4_num_cores == 1)
4558 {
4559 ps_dec->u1_separate_parse = 0;
4560 ps_dec->pi4_ctxt_save_register_dec = ps_dec->pi4_ctxt_save_register;
4561 }
4562 else
4563 {
4564 ps_dec->u1_separate_parse = 1;
4565 }
4566
4567 /*using only upto three threads currently*/
4568 if(ps_dec->u4_num_cores > 3)
4569 ps_dec->u4_num_cores = 3;
4570
4571 return IV_SUCCESS;
4572}
4573
4574void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
4575 ivd_video_decode_op_t *ps_dec_op)
4576{
4577 if((ps_dec_op->u4_error_code & 0xff)
4578 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
4579 {
4580 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
4581 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
4582 }
4583 ps_dec_op->e_pic_type = ps_dec->i4_frametype;
4584
4585 ps_dec_op->u4_new_seq = 0;
4586 ps_dec_op->u4_output_present = ps_dec->u4_output_present;
4587 ps_dec_op->u4_progressive_frame_flag =
4588 ps_dec->s_disp_op.u4_progressive_frame_flag;
4589
4590 ps_dec_op->u4_is_ref_flag = 1;
4591 if(ps_dec_op->u4_frame_decoded_flag)
4592 {
4593 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0)
4594 ps_dec_op->u4_is_ref_flag = 0;
4595 }
4596
4597 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format;
4598 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
4599 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
4600 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
4601 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
4602}
4603
4604/*****************************************************************************/
4605/* */
4606/* Function Name : ih264d_api_function */
4607/* */
4608/* Description : */
4609/* */
4610/* Inputs :iv_obj_t decoder handle */
4611/* :pv_api_ip pointer to input structure */
4612/* :pv_api_op pointer to output structure */
4613/* Outputs : */
4614/* Returns : void */
4615/* */
4616/* Issues : none */
4617/* */
4618/* Revision History: */
4619/* */
4620/* DD MM YYYY Author(s) Changes (Describe the changes made) */
4621/* 22 10 2008 100356 Draft */
4622/* */
4623/*****************************************************************************/
4624IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl,
4625 void *pv_api_ip,
4626 void *pv_api_op)
4627{
4628 UWORD32 command;
4629 UWORD32 *pu2_ptr_cmd;
4630 UWORD32 u4_api_ret;
4631 IV_API_CALL_STATUS_T e_status;
4632 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op);
4633
4634 if(e_status != IV_SUCCESS)
4635 {
4636 UWORD32 *ptr_err;
4637
4638 ptr_err = (UWORD32 *)pv_api_op;
4639 UNUSED(ptr_err);
4640 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1));
4641 return IV_FAIL;
4642 }
4643
4644 pu2_ptr_cmd = (UWORD32 *)pv_api_ip;
4645 pu2_ptr_cmd++;
4646
4647 command = *pu2_ptr_cmd;
4648// H264_DEC_DEBUG_PRINT("inside lib = %d\n",command);
4649 switch(command)
4650 {
4651
4652 case IV_CMD_GET_NUM_MEM_REC:
4653 u4_api_ret = ih264d_get_num_rec((void *)pv_api_ip,
4654 (void *)pv_api_op);
4655
4656 break;
4657 case IV_CMD_FILL_NUM_MEM_REC:
4658
4659 u4_api_ret = ih264d_fill_num_mem_rec((void *)pv_api_ip,
4660 (void *)pv_api_op);
4661 break;
4662 case IV_CMD_INIT:
4663 u4_api_ret = ih264d_init(dec_hdl, (void *)pv_api_ip,
4664 (void *)pv_api_op);
4665 break;
4666
4667 case IVD_CMD_VIDEO_DECODE:
4668 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip,
4669 (void *)pv_api_op);
4670 break;
4671
4672 case IVD_CMD_GET_DISPLAY_FRAME:
4673 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip,
4674 (void *)pv_api_op);
4675
4676 break;
4677
4678 case IVD_CMD_SET_DISPLAY_FRAME:
4679 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip,
4680 (void *)pv_api_op);
4681
4682 break;
4683
4684 case IVD_CMD_REL_DISPLAY_FRAME:
4685 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip,
4686 (void *)pv_api_op);
4687 break;
4688
4689 case IV_CMD_RETRIEVE_MEMREC:
4690 u4_api_ret = ih264d_clr(dec_hdl, (void *)pv_api_ip,
4691 (void *)pv_api_op);
4692 break;
4693
4694 case IVD_CMD_VIDEO_CTL:
4695 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip,
4696 (void *)pv_api_op);
4697 break;
4698 default:
4699 u4_api_ret = IV_FAIL;
4700 break;
4701 }
4702
4703 return u4_api_ret;
4704}