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gerrit-public.fairphone.software / platform / external / libavc / refs/heads/int/p/fp2 / . / decoder / ih264d_utils.c
blob: 6c4ded070bc9c40037a999d80d38539a51f7579d [file] [log] [blame]
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1/******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19*/
20/*!
21 **************************************************************************
22 * \file ih264d_utils.c
23 *
24 * \brief
25 * Contains routines that handle of start and end of pic processing
26 *
27 * \date
28 * 19/12/2002
29 *
30 * \author AI
31 **************************************************************************
32 */
33
34#include <string.h>
35#include "ih264_typedefs.h"
36#include "ithread.h"
37#include "ih264d_deblocking.h"
38#include "ih264d_parse_slice.h"
39#include "ih264d_parse_cavlc.h"
40#include "ih264d_dpb_manager.h"
41#include "ih264d_defs.h"
42#include "ih264d_structs.h"
43#include "ih264d_mem_request.h"
44#include "ih264_typedefs.h"
45#include "ih264_macros.h"
46#include "ih264_platform_macros.h"
47#include "ih264d_tables.h"
48#include "ih264d_debug.h"
49#include "ih264d_mb_utils.h"
50#include "ih264d_error_handler.h"
51#include "ih264d_dpb_manager.h"
52#include "ih264d_utils.h"
53#include "ih264d_defs.h"
54#include "ih264d_tables.h"
55#include "ih264d_inter_pred.h"
56#include "ih264d_dpb_manager.h"
57#include "iv.h"
58#include "ivd.h"
59#include "ih264d_format_conv.h"
60#include "ih264_error.h"
61#include "ih264_disp_mgr.h"
62#include "ih264_buf_mgr.h"
63#include "ih264d_utils.h"
64
65/*!
66 **************************************************************************
67 * \if Function name : ih264d_is_end_of_pic \endif
68 *
69 * \brief
70 * Determines whether current slice is first slice of a new picture as
71 * defined in 7.4.1.2.4 of 14496-10.
72 *
73 * \return
74 * Return 1 if current slice is first slice of a new picture
75 * Otherwise it returns 0
76 **************************************************************************
77 */
78UWORD8 ih264d_is_end_of_pic(UWORD16 u2_frame_num,
79 UWORD8 u1_nal_ref_idc,
80 pocstruct_t *ps_cur_poc,
81 pocstruct_t *ps_prev_poc,
82 dec_slice_params_t * ps_prev_slice, /*!< Previous slice parameters*/
83 UWORD8 u1_pic_order_cnt_type,
84 UWORD8 u1_nal_unit_type,
85 UWORD32 u4_idr_pic_id,
86 UWORD8 u1_field_pic_flag,
87 UWORD8 u1_bottom_field_flag)
88{
89 WORD8 i1_is_end_of_pic;
90 WORD8 a, b, c, d, e, f, g, h;
91
92 a = b = c = d = e = f = g = h = 0;
93 a = (ps_prev_slice->u2_frame_num != u2_frame_num);
94 b = (ps_prev_slice->u1_field_pic_flag != u1_field_pic_flag);
95 if(u1_field_pic_flag && ps_prev_slice->u1_field_pic_flag)
96 c = (u1_bottom_field_flag != ps_prev_slice->u1_bottom_field_flag);
97 d =
98 (u1_nal_ref_idc == 0 && ps_prev_slice->u1_nal_ref_idc != 0)
99 || (u1_nal_ref_idc != 0
100 && ps_prev_slice->u1_nal_ref_idc
101 == 0);
102 if(!a)
103 {
104 if((u1_pic_order_cnt_type == 0)
105 && (ps_prev_slice->u1_pic_order_cnt_type == 0))
106 {
107 e =
108 ((ps_cur_poc->i4_pic_order_cnt_lsb
109 != ps_prev_poc->i4_pic_order_cnt_lsb)
110 || (ps_cur_poc->i4_delta_pic_order_cnt_bottom
111 != ps_prev_poc->i4_delta_pic_order_cnt_bottom));
112 }
113
114 if((u1_pic_order_cnt_type == 1)
115 && (ps_prev_slice->u1_pic_order_cnt_type == 1))
116 {
117 f =
118 ((ps_cur_poc->i4_delta_pic_order_cnt[0]
119 != ps_prev_poc->i4_delta_pic_order_cnt[0])
120 || (ps_cur_poc->i4_delta_pic_order_cnt[1]
121 != ps_prev_poc->i4_delta_pic_order_cnt[1]));
122 }
123 }
124
125 if((u1_nal_unit_type == IDR_SLICE_NAL)
126 && (ps_prev_slice->u1_nal_unit_type == IDR_SLICE_NAL))
127 {
128 g = (u4_idr_pic_id != ps_prev_slice->u4_idr_pic_id);
129 }
130
131 if((u1_nal_unit_type == IDR_SLICE_NAL)
132 && (ps_prev_slice->u1_nal_unit_type != IDR_SLICE_NAL))
133 {
134 h = 1;
135 }
136 i1_is_end_of_pic = a + b + c + d + e + f + g + h;
137 return (i1_is_end_of_pic);
138}
139
140/*!
141 **************************************************************************
142 * \if Function name : ih264d_decode_pic_order_cnt \endif
143 *
144 * \brief
145 * Calculates picture order count of picture.
146 *
147 * \return
148 * Returns the pic order count of the picture to which current
149 * Slice belongs.
150 *
151 **************************************************************************
152 */
153WORD32 ih264d_decode_pic_order_cnt(UWORD8 u1_is_idr_slice,
154 UWORD32 u2_frame_num,
155 pocstruct_t *ps_prev_poc,
156 pocstruct_t *ps_cur_poc,
157 dec_slice_params_t *ps_cur_slice, /*!< Pointer to current slice Params*/
158 dec_pic_params_t * ps_pps,
159 UWORD8 u1_nal_ref_idc,
160 UWORD8 u1_bottom_field_flag,
161 UWORD8 u1_field_pic_flag,
162 WORD32 *pi4_poc)
163{
164 WORD16 i1_pic_msb;
165 WORD32 i4_top_field_order_cnt = 0, i4_bottom_field_order_cnt = 0;
166 dec_seq_params_t *ps_seq = ps_pps->ps_sps;
167 WORD32 i4_prev_frame_num_ofst;
168
169 switch(ps_seq->u1_pic_order_cnt_type)
170 {
171 case 0:
172 /* POC TYPE 0 */
173 if(u1_is_idr_slice)
174 {
175 ps_prev_poc->i4_pic_order_cnt_msb = 0;
176 ps_prev_poc->i4_pic_order_cnt_lsb = 0;
177 }
178 if(ps_prev_poc->u1_mmco_equalto5)
179 {
180 if(ps_prev_poc->u1_bot_field != 1)
181 {
182 ps_prev_poc->i4_pic_order_cnt_msb = 0;
183 ps_prev_poc->i4_pic_order_cnt_lsb =
184 ps_prev_poc->i4_top_field_order_count;
185 }
186 else
187 {
188 ps_prev_poc->i4_pic_order_cnt_msb = 0;
189 ps_prev_poc->i4_pic_order_cnt_lsb = 0;
190 }
191 }
192
193 if((ps_cur_poc->i4_pic_order_cnt_lsb
194 < ps_prev_poc->i4_pic_order_cnt_lsb)
195 && ((ps_prev_poc->i4_pic_order_cnt_lsb
196 - ps_cur_poc->i4_pic_order_cnt_lsb)
197 >= (ps_seq->i4_max_pic_order_cntLsb
198 >> 1)))
199 {
200 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb
201 + ps_seq->i4_max_pic_order_cntLsb;
202 }
203 else if((ps_cur_poc->i4_pic_order_cnt_lsb
204 > ps_prev_poc->i4_pic_order_cnt_lsb)
205 && ((ps_cur_poc->i4_pic_order_cnt_lsb
206 - ps_prev_poc->i4_pic_order_cnt_lsb)
207 >= (ps_seq->i4_max_pic_order_cntLsb
208 >> 1)))
209 {
210 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb
211 - ps_seq->i4_max_pic_order_cntLsb;
212 }
213 else
214 {
215 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb;
216 }
217
218 if(!u1_field_pic_flag || !u1_bottom_field_flag)
219 i4_top_field_order_cnt = i1_pic_msb
220 + ps_cur_poc->i4_pic_order_cnt_lsb;
221
222 if(!u1_field_pic_flag)
223 {
224 i4_bottom_field_order_cnt = i4_top_field_order_cnt
225 + ps_cur_poc->i4_delta_pic_order_cnt_bottom;
226 }
227 else if(u1_bottom_field_flag)
228 {
229 i4_bottom_field_order_cnt = i1_pic_msb
230 + ps_cur_poc->i4_pic_order_cnt_lsb;
231 }
232 ps_cur_poc->i4_pic_order_cnt_msb = i1_pic_msb;
233 break;
234
235 case 1:
236 {
237 /* POC TYPE 1 */
238 UWORD8 i;
239 WORD32 prev_frame_num;
240 WORD32 frame_num_ofst;
241 WORD32 abs_frm_num;
242 WORD32 poc_cycle_cnt, frame_num_in_poc_cycle;
243 WORD32 expected_delta_poc_cycle;
244 WORD32 expected_poc;
245
246 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num;
247 if(!u1_is_idr_slice)
248 {
249 if(ps_cur_slice->u1_mmco_equalto5)
250 {
251 prev_frame_num = 0;
252 i4_prev_frame_num_ofst = 0;
253 }
254 else
255 {
256 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst;
257 }
258 }
259 else
260 i4_prev_frame_num_ofst = 0;
261
262 /* 1. Derivation for FrameNumOffset */
263 if(u1_is_idr_slice)
264 {
265 frame_num_ofst = 0;
266 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
267 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
268 }
269 else if(prev_frame_num > ((WORD32)u2_frame_num))
270 {
271 frame_num_ofst = i4_prev_frame_num_ofst
272 + ps_seq->u2_u4_max_pic_num_minus1 + 1;
273 }
274 else
275 frame_num_ofst = i4_prev_frame_num_ofst;
276
277 /* 2. Derivation for absFrameNum */
278 if(0 != ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle)
279 abs_frm_num = frame_num_ofst + u2_frame_num;
280 else
281 abs_frm_num = 0;
282 if((u1_nal_ref_idc == 0) && (abs_frm_num > 0))
283 abs_frm_num = abs_frm_num - 1;
284
285 /* 4. expectedDeltaPerPicOrderCntCycle is derived as */
286 expected_delta_poc_cycle = 0;
287 for(i = 0; i < ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle;
288 i++)
289 {
290 expected_delta_poc_cycle +=
291 ps_seq->i4_ofst_for_ref_frame[i];
292 }
293
294 /* 3. When absFrameNum > 0, picOrderCntCycleCnt and
295 frame_num_in_poc_cycle are derived as : */
296 /* 5. expectedPicOrderCnt is derived as : */
297 if(abs_frm_num > 0)
298 {
299 poc_cycle_cnt =
300 DIV((abs_frm_num - 1),
301 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle);
302 frame_num_in_poc_cycle =
303 MOD((abs_frm_num - 1),
304 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle);
305
306 expected_poc = poc_cycle_cnt
307 * expected_delta_poc_cycle;
308 for(i = 0; i <= frame_num_in_poc_cycle; i++)
309 {
310 expected_poc = expected_poc
311 + ps_seq->i4_ofst_for_ref_frame[i];
312 }
313 }
314 else
315 expected_poc = 0;
316
317 if(u1_nal_ref_idc == 0)
318 {
319 expected_poc = expected_poc
320 + ps_seq->i4_ofst_for_non_ref_pic;
321 }
322
323 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */
324 if(!u1_field_pic_flag)
325 {
326 i4_top_field_order_cnt = expected_poc
327 + ps_cur_poc->i4_delta_pic_order_cnt[0];
328 i4_bottom_field_order_cnt = i4_top_field_order_cnt
329 + ps_seq->i4_ofst_for_top_to_bottom_field
330 + ps_cur_poc->i4_delta_pic_order_cnt[1];
331 }
332 else if(!u1_bottom_field_flag)
333 {
334 i4_top_field_order_cnt = expected_poc
335 + ps_cur_poc->i4_delta_pic_order_cnt[0];
336 }
337 else
338 {
339 i4_bottom_field_order_cnt = expected_poc
340 + ps_seq->i4_ofst_for_top_to_bottom_field
341 + ps_cur_poc->i4_delta_pic_order_cnt[0];
342 }
343 /* Copy the current POC info into Previous POC structure */
344 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst;
345 }
346
347 break;
348 case 2:
349 {
350 /* POC TYPE 2 */
351 WORD32 prev_frame_num;
352 WORD32 frame_num_ofst;
353 WORD32 tmp_poc;
354
355 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num;
356 if(!u1_is_idr_slice)
357 {
358 if(ps_cur_slice->u1_mmco_equalto5)
359 {
360 prev_frame_num = 0;
361 i4_prev_frame_num_ofst = 0;
362 }
363 else
364 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst;
365 }
366 else
367 i4_prev_frame_num_ofst = 0;
368
369 /* 1. Derivation for FrameNumOffset */
370 if(u1_is_idr_slice)
371 {
372 frame_num_ofst = 0;
373 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
374 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
375 }
376 else if(prev_frame_num > ((WORD32)u2_frame_num))
377 {
378 frame_num_ofst = i4_prev_frame_num_ofst
379 + ps_seq->u2_u4_max_pic_num_minus1 + 1;
380 }
381 else
382 frame_num_ofst = i4_prev_frame_num_ofst;
383
384 /* 2. Derivation for tempPicOrderCnt */
385 if(u1_is_idr_slice)
386 tmp_poc = 0;
387 else if(u1_nal_ref_idc == 0)
388 tmp_poc = ((frame_num_ofst + u2_frame_num) << 1)
389 - 1;
390 else
391 tmp_poc = ((frame_num_ofst + u2_frame_num) << 1);
392
393 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */
394 if(!u1_field_pic_flag)
395 {
396 i4_top_field_order_cnt = tmp_poc;
397 i4_bottom_field_order_cnt = tmp_poc;
398 }
399 else if(!u1_bottom_field_flag)
400 i4_top_field_order_cnt = tmp_poc;
401 else
402 i4_bottom_field_order_cnt = tmp_poc;
403
404 /* Copy the current POC info into Previous POC structure */
405 ps_prev_poc->i4_prev_frame_num_ofst = frame_num_ofst;
406 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst;
407 }
408 break;
409 default:
410 return ERROR_INV_POC_TYPE_T;
411 break;
412 }
413
414 if(!u1_field_pic_flag) // or a complementary field pair
415 {
416 *pi4_poc = MIN(i4_top_field_order_cnt, i4_bottom_field_order_cnt);
417 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt;
418 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt;
419 }
420 else if(!u1_bottom_field_flag)
421 {
422 *pi4_poc = i4_top_field_order_cnt;
423 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt;
424 }
425 else
426 {
427 *pi4_poc = i4_bottom_field_order_cnt;
428 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt;
429 }
430
431 ps_pps->i4_avg_poc = *pi4_poc;
432
433 return OK;
434}
435
436/*!
437 **************************************************************************
438 * \if Function name : ih264d_end_of_pic_processing \endif
439 *
440 * \brief
441 * Performs the end of picture processing.
442 *
443 * It performs deblocking on the current picture and sets the i4_status of
444 * current picture as decoded.
445 *
446 * \return
447 * 0 on Success and Error code otherwise.
448 **************************************************************************
449 */
450WORD32 ih264d_end_of_pic_processing(dec_struct_t *ps_dec)
451{
452 UWORD8 u1_pic_type, u1_nal_ref_idc;
453 dec_slice_params_t *ps_cur_slice = ps_dec->ps_cur_slice;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]454
455 /* If nal_ref_idc is equal to 0 for one slice or slice data partition NAL
456 unit of a particular picture, it shall be equal to 0 for all slice and
457 slice data partition NAL units of the picture. nal_ref_idc greater
458 than 0 indicates that the content of the NAL unit belongs to a decoded
459 picture that is stored and marked for use as a reference picture in the
460 decoded picture buffer. */
461
462 /* 1. Do MMCO
463 2. Add Cur Pic to list of reference pics.
464 */
465
466 /* Call MMCO */
467 u1_pic_type = 0;
468 u1_nal_ref_idc = ps_cur_slice->u1_nal_ref_idc;
469
470 if(u1_nal_ref_idc)
471 {
472 if(ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
473 {
474 if(ps_dec->ps_dpb_cmds->u1_long_term_reference_flag == 0)
475 {
476 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr);
Harish Mahendrakar27b7a142016-04-26 17:23:03 +0530[diff] [blame]477 /* ignore DPB errors */
478 ih264d_insert_st_node(ps_dec->ps_dpb_mgr,
479 ps_dec->ps_cur_pic,
480 ps_dec->u1_pic_buf_id,
481 ps_cur_slice->u2_frame_num);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]482 }
483 else
484 {
485 /* Equivalent of inserting a pic directly as longterm Pic */
486
487 {
Harish Mahendrakar27b7a142016-04-26 17:23:03 +0530[diff] [blame]488 /* ignore DPB errors */
489 ih264d_insert_st_node(ps_dec->ps_dpb_mgr,
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]490 ps_dec->ps_cur_pic,
491 ps_dec->u1_pic_buf_id,
492 ps_cur_slice->u2_frame_num);
Harish Mahendrakar27b7a142016-04-26 17:23:03 +0530[diff] [blame]493
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]494 /* Set longTermIdx = 0, MaxLongTermFrameIdx = 0 */
Harish Mahendrakar27b7a142016-04-26 17:23:03 +0530[diff] [blame]495 ih264d_delete_st_node_or_make_lt(
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]496 ps_dec->ps_dpb_mgr,
497 ps_cur_slice->u2_frame_num, 0,
498 ps_cur_slice->u1_field_pic_flag);
Harish Mahendrakar27b7a142016-04-26 17:23:03 +0530[diff] [blame]499
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]500 ps_dec->ps_dpb_mgr->u1_max_lt_pic_idx_plus1 = 1;
501 }
502 }
503 }
504 else
505 {
506
507 {
508 UWORD16 u2_pic_num = ps_cur_slice->u2_frame_num;
509
Harish Mahendrakar27b7a142016-04-26 17:23:03 +0530[diff] [blame]510 /* ignore DPB errors */
511 ih264d_do_mmco_buffer(ps_dec->ps_dpb_cmds, ps_dec->ps_dpb_mgr,
512 ps_dec->ps_cur_sps->u1_num_ref_frames, u2_pic_num,
513 (ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1),
514 ps_dec->u1_nal_unit_type, ps_dec->ps_cur_pic,
515 ps_dec->u1_pic_buf_id,
516 ps_cur_slice->u1_field_pic_flag,
517 ps_dec->e_dec_status);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]518
519
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]520 }
521 }
522 ih264d_update_default_index_list(ps_dec->ps_dpb_mgr);
523 }
524
525 if(ps_cur_slice->u1_field_pic_flag)
526 {
527 if(ps_cur_slice->u1_bottom_field_flag)
528 {
529 if(u1_nal_ref_idc)
530 u1_pic_type = u1_pic_type | BOT_REF;
531 u1_pic_type = u1_pic_type | BOT_FLD;
532 }
533 else
534 {
535 if(u1_nal_ref_idc)
536 u1_pic_type = u1_pic_type | TOP_REF;
537 u1_pic_type = u1_pic_type | TOP_FLD;
538 }
539 }
540 else
541 u1_pic_type = TOP_REF | BOT_REF;
542 ps_dec->ps_cur_pic->u1_pic_type |= u1_pic_type;
543
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]544
545 if(ps_cur_slice->u1_field_pic_flag)
546 {
547 H264_DEC_DEBUG_PRINT("Toggling secondField\n");
548 ps_dec->u1_second_field = 1 - ps_dec->u1_second_field;
549 }
550
551 return OK;
552}
553
554/*****************************************************************************/
555/* */
556/* Function Name : init_dpb_size */
557/* */
558/* Description : This function calculates the DBP i4_size in frames */
559/* Inputs : ps_seq - current sequence params */
560/* */
561/* Globals : None */
562/* */
563/* Outputs : None */
564/* */
565/* Returns : DPB in frames */
566/* */
567/* Issues : None */
568/* */
569/* Revision History: */
570/* */
571/* DD MM YYYY Author(s) Changes (Describe the changes made) */
572/* 28 04 2005 NS Draft */
573/* */
574/*****************************************************************************/
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]575WORD32 ih264d_get_dpb_size(dec_seq_params_t *ps_seq)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]576{
577 WORD32 i4_size;
578 UWORD8 u1_level_idc;
579
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]580 u1_level_idc = ps_seq->u1_level_idc;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]581
582 switch(u1_level_idc)
583 {
584 case 10:
585 i4_size = 152064;
586 break;
587 case 11:
588 i4_size = 345600;
589 break;
590 case 12:
591 i4_size = 912384;
592 break;
593 case 13:
594 i4_size = 912384;
595 break;
596 case 20:
597 i4_size = 912384;
598 break;
599 case 21:
600 i4_size = 1824768;
601 break;
602 case 22:
603 i4_size = 3110400;
604 break;
605 case 30:
606 i4_size = 3110400;
607 break;
608 case 31:
609 i4_size = 6912000;
610 break;
611 case 32:
612 i4_size = 7864320;
613 break;
614 case 40:
615 i4_size = 12582912;
616 break;
617 case 41:
618 i4_size = 12582912;
619 break;
620 case 42:
621 i4_size = 12582912;
622 break;
623 case 50:
624 i4_size = 42393600;
625 break;
626 case 51:
627 i4_size = 70778880;
628 break;
Hamsalekha S9327d0e2015-05-20 17:07:10 +0530[diff] [blame]629 case 52:
630 i4_size = 70778880;
631 break;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]632 default:
Hamsalekha S9327d0e2015-05-20 17:07:10 +0530[diff] [blame]633 i4_size = 70778880;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]634 break;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]635 }
636
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]637 i4_size /= (ps_seq->u2_frm_wd_in_mbs * (ps_seq->u2_frm_ht_in_mbs << (1 - ps_seq->u1_frame_mbs_only_flag)));
638 i4_size /= 384;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]639 i4_size = MIN(i4_size, 16);
640 i4_size = MAX(i4_size, 1);
641 return (i4_size);
642}
643
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]644/**************************************************************************/
645/* This function initialises the value of ps_dec->u1_recon_mb_grp */
646/* ps_dec->u1_recon_mb_grp must satisfy the following criteria */
647/* - multiple of 2 (required for N/2 parse-mvpred design) */
648/* - multiple of 4 (if it is not a frame_mbs_only sequence), */
649/* in this case N/2 itself needs to be even for mbpair processing */
650/* - lesser than ps_dec->u2_frm_wd_in_mbs/2 (at least 3 N-Chunks */
651/* should make a row to ensure proper MvTop transferring) */
652/**************************************************************************/
653WORD32 ih264d_init_dec_mb_grp(dec_struct_t *ps_dec)
654{
655 dec_seq_params_t *ps_seq = ps_dec->ps_cur_sps;
656 UWORD8 u1_frm = ps_seq->u1_frame_mbs_only_flag;
657
Harish Mahendrakar6676aeb2016-10-14 17:19:53 +0530[diff] [blame]658 ps_dec->u1_recon_mb_grp = ps_dec->u2_frm_wd_in_mbs << ps_seq->u1_mb_aff_flag;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]659
660 ps_dec->u1_recon_mb_grp_pair = ps_dec->u1_recon_mb_grp >> 1;
661
662 if(!ps_dec->u1_recon_mb_grp)
663 {
664 return ERROR_MB_GROUP_ASSGN_T;
665 }
666
667 ps_dec->u4_num_mbs_prev_nmb = ps_dec->u1_recon_mb_grp;
668
669 return OK;
670}
671
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]672
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]673/*!
674 **************************************************************************
675 * \if Function name : ih264d_init_pic \endif
676 *
677 * \brief
678 * Initializes the picture.
679 *
680 * \return
681 * 0 on Success and Error code otherwise
682 *
683 * \note
684 * This function is called when first slice of the
685 * NON -IDR picture is encountered.
686 **************************************************************************
687 */
688WORD32 ih264d_init_pic(dec_struct_t *ps_dec,
689 UWORD16 u2_frame_num,
690 WORD32 i4_poc,
691 dec_pic_params_t *ps_pps)
692{
693 dec_seq_params_t *ps_seq = ps_pps->ps_sps;
694 prev_seq_params_t * ps_prev_seq_params = &ps_dec->s_prev_seq_params;
695 WORD32 i4_pic_bufs;
696 WORD32 ret;
697
698 ps_dec->ps_cur_slice->u2_frame_num = u2_frame_num;
699 ps_dec->ps_cur_slice->i4_poc = i4_poc;
700 ps_dec->ps_cur_pps = ps_pps;
701 ps_dec->ps_cur_pps->pv_codec_handle = ps_dec;
702
703 ps_dec->ps_cur_sps = ps_seq;
704 ps_dec->ps_dpb_mgr->i4_max_frm_num = ps_seq->u2_u4_max_pic_num_minus1
705 + 1;
706
707 ps_dec->ps_dpb_mgr->u2_pic_ht = ps_dec->u2_pic_ht;
708 ps_dec->ps_dpb_mgr->u2_pic_wd = ps_dec->u2_pic_wd;
709 ps_dec->i4_pic_type = -1;
710 ps_dec->i4_frametype = -1;
711 ps_dec->i4_content_type = -1;
712
713 /*--------------------------------------------------------------------*/
714 /* Get the value of MaxMbAddress and frmheight in Mbs */
715 /*--------------------------------------------------------------------*/
716 ps_seq->u2_max_mb_addr =
717 (ps_seq->u2_frm_wd_in_mbs
718 * (ps_dec->u2_pic_ht
719 >> (4
720 + ps_dec->ps_cur_slice->u1_field_pic_flag)))
721 - 1;
722 ps_dec->u2_frm_ht_in_mbs = (ps_dec->u2_pic_ht
723 >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag));
724
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]725 /***************************************************************************/
726 /* If change in Level or the required PicBuffers i4_size is more than the */
727 /* current one FREE the current PicBuffers and allocate affresh */
728 /***************************************************************************/
Hamsalekha Sf15bb322017-06-22 17:08:44 +0530[diff] [blame]729 if(!ps_dec->u1_init_dec_flag)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]730 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]731 ps_dec->u1_max_dec_frame_buffering = ih264d_get_dpb_size(ps_seq);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]732
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]733 ps_dec->i4_display_delay = ps_dec->u1_max_dec_frame_buffering;
734 if((1 == ps_seq->u1_vui_parameters_present_flag) &&
735 (1 == ps_seq->s_vui.u1_bitstream_restriction_flag))
736 {
737 if(ps_seq->u1_frame_mbs_only_flag == 1)
738 ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames + 1;
739 else
740 ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames * 2 + 2;
741 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]742
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]743 if(IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode)
744 ps_dec->i4_display_delay = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]745
746 if(ps_dec->u4_share_disp_buf == 0)
747 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]748 if(ps_seq->u1_frame_mbs_only_flag == 1)
749 ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + ps_seq->u1_num_ref_frames + 1;
750 else
751 ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + ps_seq->u1_num_ref_frames * 2 + 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]752 }
753 else
754 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]755 ps_dec->u1_pic_bufs = (WORD32)ps_dec->u4_num_disp_bufs;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]756 }
757
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]758 /* Ensure at least two buffers are allocated */
759 ps_dec->u1_pic_bufs = MAX(ps_dec->u1_pic_bufs, 2);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]760
761 if(ps_dec->u4_share_disp_buf == 0)
762 ps_dec->u1_pic_bufs = MIN(ps_dec->u1_pic_bufs,
763 (H264_MAX_REF_PICS * 2));
764
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]765 ps_dec->u1_max_dec_frame_buffering = MIN(
766 ps_dec->u1_max_dec_frame_buffering,
767 ps_dec->u1_pic_bufs);
768
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]769 /* Temporary hack to run Tractor Cav/Cab/MbAff Profiler streams also for CAFI1_SVA_C.264 in conformance*/
770 if(ps_dec->u1_init_dec_flag)
771 {
772 ih264d_release_pics_in_dpb((void *)ps_dec,
773 ps_dec->u1_pic_bufs);
774 ih264d_release_display_bufs(ps_dec);
775 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr);
776 }
777
778 /*********************************************************************/
779 /* Configuring decoder parameters based on level and then */
780 /* fresh pointer initialisation in decoder scratch and state buffers */
781 /*********************************************************************/
782 if(!ps_dec->u1_init_dec_flag ||
783 ((ps_seq->u1_level_idc < H264_LEVEL_3_0) ^ (ps_prev_seq_params->u1_level_idc < H264_LEVEL_3_0)))
784 {
785 ret = ih264d_init_dec_mb_grp(ps_dec);
786 if(ret != OK)
787 return ret;
788 }
789
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]790 ret = ih264d_allocate_dynamic_bufs(ps_dec);
791 if(ret != OK)
792 {
793 /* Free any dynamic buffers that are allocated */
794 ih264d_free_dynamic_bufs(ps_dec);
795 ps_dec->i4_error_code = IVD_MEM_ALLOC_FAILED;
796 return IVD_MEM_ALLOC_FAILED;
797 }
798
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]799 ret = ih264d_create_pic_buffers(ps_dec->u1_pic_bufs,
800 ps_dec);
801 if(ret != OK)
802 return ret;
803
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]804
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]805
806 ret = ih264d_create_mv_bank(ps_dec, ps_dec->u2_pic_wd,
807 ps_dec->u2_pic_ht);
808 if(ret != OK)
809 return ret;
810
811 /* In shared mode, set all of them as used by display */
812 if(ps_dec->u4_share_disp_buf == 1)
813 {
814 WORD32 i;
815
816 for(i = 0; i < ps_dec->u1_pic_bufs; i++)
817 {
818 ih264_buf_mgr_set_status((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i,
819 BUF_MGR_IO);
820 }
821 }
822
823 ps_dec->u1_init_dec_flag = 1;
824 ps_prev_seq_params->u2_frm_wd_in_mbs = ps_seq->u2_frm_wd_in_mbs;
825 ps_prev_seq_params->u1_level_idc = ps_seq->u1_level_idc;
826 ps_prev_seq_params->u1_profile_idc = ps_seq->u1_profile_idc;
827 ps_prev_seq_params->u2_frm_ht_in_mbs = ps_seq->u2_frm_ht_in_mbs;
828 ps_prev_seq_params->u1_frame_mbs_only_flag =
829 ps_seq->u1_frame_mbs_only_flag;
830 ps_prev_seq_params->u1_direct_8x8_inference_flag =
831 ps_seq->u1_direct_8x8_inference_flag;
832
833 ps_dec->i4_cur_display_seq = 0;
834 ps_dec->i4_prev_max_display_seq = 0;
835 ps_dec->i4_max_poc = 0;
836
837 {
838 /* 0th entry of CtxtIncMbMap will be always be containing default values
839 for CABAC context representing MB not available */
840 ctxt_inc_mb_info_t *p_DefCtxt = ps_dec->p_ctxt_inc_mb_map - 1;
841 UWORD8 *pu1_temp;
842 WORD8 i;
843 p_DefCtxt->u1_mb_type = CAB_SKIP;
844
845 p_DefCtxt->u1_cbp = 0x0f;
846 p_DefCtxt->u1_intra_chroma_pred_mode = 0;
847
848 p_DefCtxt->u1_yuv_dc_csbp = 0x7;
849
850 p_DefCtxt->u1_transform8x8_ctxt = 0;
851
852 pu1_temp = (UWORD8*)p_DefCtxt->i1_ref_idx;
853 for(i = 0; i < 4; i++, pu1_temp++)
854 (*pu1_temp) = 0;
855 pu1_temp = (UWORD8*)p_DefCtxt->u1_mv;
856 for(i = 0; i < 16; i++, pu1_temp++)
857 (*pu1_temp) = 0;
858 ps_dec->ps_def_ctxt_mb_info = p_DefCtxt;
859 }
860
861 }
862 /* reset DBP commands read u4_flag */
863 ps_dec->ps_dpb_cmds->u1_dpb_commands_read = 0;
864
865 return OK;
866}
867
868/*****************************************************************************/
869/* */
870/* Function Name : ih264d_get_next_display_field */
871/* */
872/* Description : Application calls this module to get the next field */
873/* to be displayed */
874/* */
875/* Inputs : 1. IBUFAPI_Handle Hnadle to the Display buffer */
876/* 2. IH264DEC_DispUnit Pointer to the display struct */
877/* */
878/* Globals : */
879/* */
880/* */
881/* Processing : None */
882/* Outputs : None */
883/* Returns : None */
884/* Issues : None */
885/* */
886/* Revision History: */
887/* */
888/* DD MM YYYY Author(s) Changes (Describe the changes made) */
889/* 27 05 2005 Ittiam Draft */
890/* */
891/*****************************************************************************/
892
893WORD32 ih264d_get_next_display_field(dec_struct_t * ps_dec,
894 ivd_out_bufdesc_t *ps_out_buffer,
895 ivd_get_display_frame_op_t *pv_disp_op)
896{
897 pic_buffer_t *pic_buf;
898
899 UWORD8 i1_cur_fld;
900 WORD32 u4_api_ret = -1;
901 WORD32 i4_disp_buf_id;
902 iv_yuv_buf_t *ps_op_frm;
903
904
905
906 ps_op_frm = &(ps_dec->s_disp_frame_info);
907 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex);
908 pic_buf = (pic_buffer_t *)ih264_disp_mgr_get(
909 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, &i4_disp_buf_id);
910 ps_dec->u4_num_fld_in_frm = 0;
911 u4_api_ret = -1;
912 pv_disp_op->u4_ts = -1;
913 pv_disp_op->e_output_format = ps_dec->u1_chroma_format;
914
915 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_out_buffer->pu1_bufs[0];
916 pv_disp_op->s_disp_frm_buf.pv_u_buf = ps_out_buffer->pu1_bufs[1];
917 pv_disp_op->s_disp_frm_buf.pv_v_buf = ps_out_buffer->pu1_bufs[2];
918 if(pic_buf != NULL)
919 {
920 pv_disp_op->e4_fld_type = 0;
921 pv_disp_op->u4_disp_buf_id = i4_disp_buf_id;
922
923 ps_op_frm->u4_y_ht = pic_buf->u2_disp_height << 1;
924 ps_op_frm->u4_u_ht = ps_op_frm->u4_v_ht = ps_op_frm->u4_y_ht >> 1;
925 ps_op_frm->u4_y_wd = pic_buf->u2_disp_width;
926
927 ps_op_frm->u4_u_wd = ps_op_frm->u4_v_wd = ps_op_frm->u4_y_wd >> 1;
928
929 ps_op_frm->u4_y_strd = pic_buf->u2_frm_wd_y;
930 ps_op_frm->u4_u_strd = ps_op_frm->u4_v_strd = pic_buf->u2_frm_wd_uv;
931
932 /* ! */
933 pv_disp_op->u4_ts = pic_buf->u4_ts;
934
935 /* set the start of the Y, U and V buffer pointer for display */
936 ps_op_frm->pv_y_buf = pic_buf->pu1_buf1 + pic_buf->u2_crop_offset_y;
937 ps_op_frm->pv_u_buf = pic_buf->pu1_buf2 + pic_buf->u2_crop_offset_uv;
938 ps_op_frm->pv_v_buf = pic_buf->pu1_buf3 + pic_buf->u2_crop_offset_uv;
939 ps_dec->u4_num_fld_in_frm++;
940 ps_dec->u4_num_fld_in_frm++;
941 u4_api_ret = 0;
942
943 if(pic_buf->u1_picturetype == 0)
944 pv_disp_op->u4_progressive_frame_flag = 1;
945 else
946 pv_disp_op->u4_progressive_frame_flag = 0;
947
948 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex);
949 pv_disp_op->u4_error_code = u4_api_ret;
950 pv_disp_op->e_pic_type = 0xFFFFFFFF; //Junk;
951
952 if(u4_api_ret)
953 {
954 pv_disp_op->u4_error_code = 1; //put a proper error code here
955 }
956 else
957 {
958
959 //Release the buffer if being sent for display
960 UWORD32 temp;
961 UWORD32 dest_inc_Y = 0, dest_inc_UV = 0;
962
963 pv_disp_op->s_disp_frm_buf.u4_y_wd = temp = MIN(ps_op_frm->u4_y_wd,
964 ps_op_frm->u4_y_strd);
965 pv_disp_op->s_disp_frm_buf.u4_u_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd
966 >> 1;
967 pv_disp_op->s_disp_frm_buf.u4_v_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd
968 >> 1;
969
970 pv_disp_op->s_disp_frm_buf.u4_y_ht = ps_op_frm->u4_y_ht;
971 pv_disp_op->s_disp_frm_buf.u4_u_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht
972 >> 1;
973 pv_disp_op->s_disp_frm_buf.u4_v_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht
974 >> 1;
975 if(0 == ps_dec->u4_share_disp_buf)
976 {
977 pv_disp_op->s_disp_frm_buf.u4_y_strd =
978 pv_disp_op->s_disp_frm_buf.u4_y_wd;
979 pv_disp_op->s_disp_frm_buf.u4_u_strd =
980 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1;
981 pv_disp_op->s_disp_frm_buf.u4_v_strd =
982 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1;
983
984 }
985 else
986 {
987 pv_disp_op->s_disp_frm_buf.u4_y_strd = ps_op_frm->u4_y_strd;
988 }
989
990 if(ps_dec->u4_app_disp_width)
991 {
992 pv_disp_op->s_disp_frm_buf.u4_y_strd = MAX(
993 ps_dec->u4_app_disp_width,
994 pv_disp_op->s_disp_frm_buf.u4_y_strd);
995 }
996
997 pv_disp_op->u4_error_code = 0;
998 if(pv_disp_op->e_output_format == IV_YUV_420P)
999 {
1000 UWORD32 i;
1001 pv_disp_op->s_disp_frm_buf.u4_u_strd =
1002 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1;
1003 pv_disp_op->s_disp_frm_buf.u4_v_strd =
1004 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1;
1005
1006 pv_disp_op->s_disp_frm_buf.u4_u_wd = ps_op_frm->u4_y_wd >> 1;
1007 pv_disp_op->s_disp_frm_buf.u4_v_wd = ps_op_frm->u4_y_wd >> 1;
1008
1009 if(1 == ps_dec->u4_share_disp_buf)
1010 {
1011 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf;
1012
1013 for(i = 0; i < MAX_DISP_BUFS_NEW; i++)
1014 {
1015 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0];
1016 buf += ps_dec->disp_bufs[i].u4_ofst[0];
1017 if(((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf
1018 - pic_buf->u2_crop_offset_y) == buf)
1019 {
1020 buf = ps_dec->disp_bufs[i].buf[1];
1021 buf += ps_dec->disp_bufs[i].u4_ofst[1];
1022 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf
Ritu Baldwac3b026a2017-12-27 17:45:30 +0530[diff] [blame]1023 + (pic_buf->u2_crop_offset_uv
1024 / YUV420SP_FACTOR);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1025
1026 buf = ps_dec->disp_bufs[i].buf[2];
1027 buf += ps_dec->disp_bufs[i].u4_ofst[2];
1028 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf
Ritu Baldwac3b026a2017-12-27 17:45:30 +0530[diff] [blame]1029 + (pic_buf->u2_crop_offset_uv
1030 / YUV420SP_FACTOR);
1031
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1032 }
1033 }
1034 }
1035
1036 }
1037 else if((pv_disp_op->e_output_format == IV_YUV_420SP_UV)
1038 || (pv_disp_op->e_output_format == IV_YUV_420SP_VU))
1039 {
1040 pv_disp_op->s_disp_frm_buf.u4_u_strd =
1041 pv_disp_op->s_disp_frm_buf.u4_y_strd;
1042 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0;
1043
1044 if(1 == ps_dec->u4_share_disp_buf)
1045 {
1046 UWORD32 i;
1047
1048 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf;
1049
1050 for(i = 0; i < MAX_DISP_BUFS_NEW; i++)
1051 {
1052 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0];
1053 buf += ps_dec->disp_bufs[i].u4_ofst[0];
1054 if((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf
1055 - pic_buf->u2_crop_offset_y == buf)
1056 {
1057 buf = ps_dec->disp_bufs[i].buf[1];
1058 buf += ps_dec->disp_bufs[i].u4_ofst[1];
1059 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf
1060 + pic_buf->u2_crop_offset_uv;
1061 ;
1062
1063 buf = ps_dec->disp_bufs[i].buf[2];
1064 buf += ps_dec->disp_bufs[i].u4_ofst[2];
1065 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf
1066 + pic_buf->u2_crop_offset_uv;
1067 ;
1068 }
1069 }
1070 }
1071 pv_disp_op->s_disp_frm_buf.u4_u_wd =
1072 pv_disp_op->s_disp_frm_buf.u4_y_wd;
1073 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0;
1074
1075 }
1076 else if((pv_disp_op->e_output_format == IV_RGB_565)
1077 || (pv_disp_op->e_output_format == IV_YUV_422ILE))
1078 {
1079
1080 pv_disp_op->s_disp_frm_buf.u4_u_strd = 0;
1081 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0;
1082 pv_disp_op->s_disp_frm_buf.u4_u_wd = 0;
1083 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0;
1084 pv_disp_op->s_disp_frm_buf.u4_u_ht = 0;
1085 pv_disp_op->s_disp_frm_buf.u4_v_ht = 0;
1086
1087 }
1088
1089
1090 }
1091
1092 return u4_api_ret;
1093}
1094
1095
1096/*****************************************************************************/
1097/* Function Name : ih264d_release_display_field */
1098/* */
1099/* Description : This function releases the display field that was returned */
1100/* here. */
1101/* Inputs : ps_dec - Decoder parameters */
1102/* Globals : None */
1103/* Processing : Refer bumping process in the standard */
1104/* Outputs : Assigns display sequence number. */
1105/* Returns : None */
1106/* */
1107/* Issues : None */
1108/* */
1109/* Revision History: */
1110/* */
1111/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1112/* 27 04 2005 NS Draft */
1113/* */
1114/*****************************************************************************/
1115void ih264d_release_display_field(dec_struct_t *ps_dec,
1116 ivd_get_display_frame_op_t *pv_disp_op)
1117{
1118 if(1 == pv_disp_op->u4_error_code)
1119 {
1120 if(1 == ps_dec->u1_flushfrm)
1121 {
1122 UWORD32 i;
1123
1124 if(1 == ps_dec->u4_share_disp_buf)
1125 {
1126 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex);
1127 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
1128 {
1129 if(1 == ps_dec->u4_disp_buf_mapping[i])
1130 {
1131 ih264_buf_mgr_release(
1132 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i,
1133 BUF_MGR_IO);
1134 ps_dec->u4_disp_buf_mapping[i] = 0;
1135 }
1136 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex);
1137
1138 memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1139 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1140 for(i = 0; i < ps_dec->u1_pic_bufs; i++)
1141 ps_dec->u4_disp_buf_mapping[i] = 1;
1142 }
1143 ps_dec->u1_flushfrm = 0;
1144
1145 }
1146 }
1147 else
1148 {
1149 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex);
1150
1151 if(0 == ps_dec->u4_share_disp_buf)
1152 {
1153 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
1154 pv_disp_op->u4_disp_buf_id,
1155 BUF_MGR_IO);
1156
1157 }
1158 else
1159 {
1160 ps_dec->u4_disp_buf_mapping[pv_disp_op->u4_disp_buf_id] = 1;
1161 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex);
1162
1163 }
1164}
1165/*****************************************************************************/
1166/* Function Name : ih264d_assign_display_seq */
1167/* */
1168/* Description : This function implments bumping process. Every outgoing */
1169/* frame from DPB is assigned a display sequence number */
1170/* which increases monotonically. System looks for this */
1171/* number to display a frame. */
1172/* here. */
1173/* Inputs : ps_dec - Decoder parameters */
1174/* Globals : None */
1175/* Processing : Refer bumping process in the standard */
1176/* Outputs : Assigns display sequence number. */
1177/* Returns : None */
1178/* */
1179/* Issues : None */
1180/* */
1181/* Revision History: */
1182/* */
1183/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1184/* 27 04 2005 NS Draft */
1185/* */
1186/*****************************************************************************/
1187WORD32 ih264d_assign_display_seq(dec_struct_t *ps_dec)
1188{
1189 WORD32 i;
1190 WORD32 i4_min_poc;
1191 WORD32 i4_min_poc_buf_id;
1192 WORD32 i4_min_index;
1193 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1194 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map;
1195
1196 i4_min_poc = 0x7fffffff;
1197 i4_min_poc_buf_id = -1;
1198 i4_min_index = -1;
1199
1200 if(ps_dpb_mgr->i1_poc_buf_id_entries >= ps_dec->i4_display_delay)
1201 {
1202 for(i = 0; i < MAX_FRAMES; i++)
1203 {
1204 if((i4_poc_buf_id_map[i][0] != -1)
1205 && (DO_NOT_DISP
1206 != ps_dpb_mgr->ai4_poc_buf_id_map[i][0]))
1207 {
Harish Mahendrakar7f33b962019-12-17 15:42:03 -0800[diff] [blame]1208 /* Checking for <= is necessary to handle cases where there is one
1209 valid buffer with poc set to 0x7FFFFFFF. */
1210 if(i4_poc_buf_id_map[i][1] <= i4_min_poc)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1211 {
1212 i4_min_poc = i4_poc_buf_id_map[i][1];
1213 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0];
1214 i4_min_index = i;
1215 }
1216 }
1217 }
1218
1219 if((i4_min_index != -1) && (DO_NOT_DISP != i4_min_poc_buf_id))
1220 {
1221 ps_dec->i4_cur_display_seq++;
1222 ih264_disp_mgr_add(
1223 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr,
1224 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq,
1225 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]);
1226 i4_poc_buf_id_map[i4_min_index][0] = -1;
1227 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff;
1228 ps_dpb_mgr->i1_poc_buf_id_entries--;
1229 }
1230 else if(DO_NOT_DISP == i4_min_poc_buf_id)
1231 {
1232 WORD32 i4_error_code;
1233 i4_error_code = ERROR_GAPS_IN_FRM_NUM;
1234// i4_error_code |= 1<<IVD_CORRUPTEDDATA;
1235 return i4_error_code;
1236 }
1237 }
1238 return OK;
1239}
1240
1241/*****************************************************************************/
1242/* */
1243/* Function Name : ih264d_release_display_bufs */
1244/* */
1245/* Description : This function implments bumping process when mmco = 5. */
1246/* Each outgoing frame from DPB is assigned a display */
1247/* sequence number which increases monotonically. System */
1248/* looks for this number to display a frame. */
1249/* Inputs : ps_dec - Decoder parameters */
1250/* Globals : None */
1251/* Processing : Refer bumping process in the standard for mmco = 5 */
1252/* Outputs : Assigns display sequence number. */
1253/* Returns : None */
1254/* */
1255/* Issues : None */
1256/* */
1257/* Revision History: */
1258/* */
1259/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1260/* 27 04 2005 NS Draft */
1261/* */
1262/*****************************************************************************/
1263void ih264d_release_display_bufs(dec_struct_t *ps_dec)
1264{
1265 WORD32 i, j;
1266 WORD32 i4_min_poc;
1267 WORD32 i4_min_poc_buf_id;
1268 WORD32 i4_min_index;
1269 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1270 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map;
1271
1272 i4_min_poc = 0x7fffffff;
Harish Mahendrakar7f33b962019-12-17 15:42:03 -0800[diff] [blame]1273 i4_min_poc_buf_id = 0;
1274 i4_min_index = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1275
1276 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1277
1278 for(j = 0; j < ps_dpb_mgr->i1_poc_buf_id_entries; j++)
1279 {
1280 i4_min_poc = 0x7fffffff;
1281 for(i = 0; i < MAX_FRAMES; i++)
1282 {
1283 if(i4_poc_buf_id_map[i][0] != -1)
1284 {
Harish Mahendrakar7f33b962019-12-17 15:42:03 -0800[diff] [blame]1285 /* Checking for <= is necessary to handle cases where there is one
1286 valid buffer with poc set to 0x7FFFFFFF. */
1287 if(i4_poc_buf_id_map[i][1] <= i4_min_poc)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1288 {
1289 i4_min_poc = i4_poc_buf_id_map[i][1];
1290 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0];
1291 i4_min_index = i;
1292 }
1293 }
1294 }
1295
1296 if(DO_NOT_DISP != i4_min_poc_buf_id)
1297 {
1298 ps_dec->i4_cur_display_seq++;
1299 ih264_disp_mgr_add(
1300 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr,
1301 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq,
1302 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]);
1303 i4_poc_buf_id_map[i4_min_index][0] = -1;
1304 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff;
1305 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0;
1306 }
1307 else
1308 {
1309 i4_poc_buf_id_map[i4_min_index][0] = -1;
1310 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff;
1311 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0;
1312 }
1313 }
1314 ps_dpb_mgr->i1_poc_buf_id_entries = 0;
1315 ps_dec->i4_prev_max_display_seq = ps_dec->i4_prev_max_display_seq
1316 + ps_dec->i4_max_poc + ps_dec->u1_max_dec_frame_buffering
1317 + 1;
1318 ps_dec->i4_max_poc = 0;
1319}
1320
1321/*****************************************************************************/
1322/* */
1323/* Function Name : ih264d_assign_pic_num */
1324/* */
1325/* Description : This function assigns pic num to each reference frame */
1326/* depending on the cur_frame_num as speified in section */
1327/* 8.2.4.1 */
1328/* */
1329/* Inputs : ps_dec */
1330/* */
1331/* Globals : NO globals used */
1332/* */
1333/* Processing : for all ST pictures */
1334/* if( FrameNum > cur_frame_num) */
1335/* PicNum = FrameNum - MaxFrameNum */
1336/* else */
1337/* PicNum = FrameNum */
1338/* */
1339/* Returns : void */
1340/* */
1341/* Issues : NO */
1342/* */
1343/* Revision History: */
1344/* */
1345/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1346/* 13 07 2002 Jay Draft */
1347/* */
1348/*****************************************************************************/
1349
1350void ih264d_assign_pic_num(dec_struct_t *ps_dec)
1351{
1352 dpb_manager_t *ps_dpb_mgr;
1353 struct dpb_info_t *ps_next_dpb;
1354 WORD8 i;
1355 WORD32 i4_cur_frame_num, i4_max_frame_num;
1356 WORD32 i4_ref_frame_num;
1357 UWORD8 u1_fld_pic_flag = ps_dec->ps_cur_slice->u1_field_pic_flag;
1358
1359 i4_max_frame_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1;
1360 i4_cur_frame_num = ps_dec->ps_cur_pic->i4_frame_num;
1361 ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1362
1363 /* Start from ST head */
1364 ps_next_dpb = ps_dpb_mgr->ps_dpb_st_head;
1365 for(i = 0; i < ps_dpb_mgr->u1_num_st_ref_bufs; i++)
1366 {
1367 WORD32 i4_pic_num;
1368
1369 i4_ref_frame_num = ps_next_dpb->ps_pic_buf->i4_frame_num;
1370 if(i4_ref_frame_num > i4_cur_frame_num)
1371 {
1372 /* RefPic Buf frame_num is before Current frame_num in decode order */
1373 i4_pic_num = i4_ref_frame_num - i4_max_frame_num;
1374 }
1375 else
1376 {
1377 /* RefPic Buf frame_num is after Current frame_num in decode order */
1378 i4_pic_num = i4_ref_frame_num;
1379 }
1380
1381 ps_next_dpb->ps_pic_buf->i4_pic_num = i4_pic_num;
1382 ps_next_dpb->i4_frame_num = i4_pic_num;
1383 ps_next_dpb->ps_pic_buf->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1384 if(u1_fld_pic_flag)
1385 {
1386 /* Assign the pic num to top fields and bot fields */
1387
1388 ps_next_dpb->s_top_field.i4_pic_num = i4_pic_num * 2
1389 + !(ps_dec->ps_cur_slice->u1_bottom_field_flag);
1390 ps_next_dpb->s_bot_field.i4_pic_num = i4_pic_num * 2
1391 + ps_dec->ps_cur_slice->u1_bottom_field_flag;
1392 }
1393 /* Chase the next link */
1394 ps_next_dpb = ps_next_dpb->ps_prev_short;
1395 }
1396
1397 if(ps_dec->ps_cur_sps->u1_gaps_in_frame_num_value_allowed_flag
1398 && ps_dpb_mgr->u1_num_gaps)
1399 {
1400 WORD32 i4_start_frm, i4_end_frm;
1401 /* Assign pic numbers for gaps */
1402 for(i = 0; i < MAX_FRAMES; i++)
1403 {
1404 i4_start_frm = ps_dpb_mgr->ai4_gaps_start_frm_num[i];
1405 if(i4_start_frm != INVALID_FRAME_NUM)
1406 {
1407 if(i4_start_frm > i4_cur_frame_num)
1408 {
1409 /* gap's frame_num is before Current frame_num in
1410 decode order */
1411 i4_start_frm -= i4_max_frame_num;
1412 }
1413 ps_dpb_mgr->ai4_gaps_start_frm_num[i] = i4_start_frm;
1414 i4_end_frm = ps_dpb_mgr->ai4_gaps_end_frm_num[i];
1415
1416 if(i4_end_frm > i4_cur_frame_num)
1417 {
1418 /* gap's frame_num is before Current frame_num in
1419 decode order */
1420 i4_end_frm -= i4_max_frame_num;
1421 }
1422 ps_dpb_mgr->ai4_gaps_end_frm_num[i] = i4_end_frm;
1423 }
1424 }
1425 }
1426}
1427
1428/*!
1429 **************************************************************************
1430 * \if Function name : ih264d_update_qp \endif
1431 *
1432 * \brief
1433 * Updates the values of QP and its related entities
1434 *
1435 * \return
1436 * 0 on Success and Error code otherwise
1437 *
1438 **************************************************************************
1439 */
1440WORD32 ih264d_update_qp(dec_struct_t * ps_dec, const WORD8 i1_qp)
1441{
1442 WORD32 i_temp;
1443 i_temp = (ps_dec->u1_qp + i1_qp + 52) % 52;
1444
1445 if((i_temp < 0) || (i_temp > 51) || (i1_qp < -26) || (i1_qp > 25))
1446 return ERROR_INV_RANGE_QP_T;
1447
1448 ps_dec->u1_qp = i_temp;
1449 ps_dec->u1_qp_y_rem6 = ps_dec->u1_qp % 6;
1450 ps_dec->u1_qp_y_div6 = ps_dec->u1_qp / 6;
1451 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_chroma_qp_index_offset);
1452 ps_dec->u1_qp_u_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1453 ps_dec->u1_qp_u_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1454
1455 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_second_chroma_qp_index_offset);
1456 ps_dec->u1_qp_v_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1457 ps_dec->u1_qp_v_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1458
1459 ps_dec->pu2_quant_scale_y =
1460 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_y_rem6];
1461 ps_dec->pu2_quant_scale_u =
1462 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_u_rem6];
1463 ps_dec->pu2_quant_scale_v =
1464 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_v_rem6];
1465 return OK;
1466}
1467
1468/*****************************************************************************/
1469/* */
1470/* Function Name : ih264d_decode_gaps_in_frame_num */
1471/* */
1472/* Description : This function decodes gaps in frame number */
1473/* */
1474/* Inputs : ps_dec Decoder parameters */
1475/* u2_frame_num current frame number */
1476/* */
1477/* Globals : None */
1478/* Processing : This functionality needs to be implemented */
1479/* Outputs : None */
1480/* Returns : None */
1481/* */
1482/* Issues : Not implemented */
1483/* */
1484/* Revision History: */
1485/* */
1486/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1487/* 06 05 2002 NS Draft */
1488/* */
1489/*****************************************************************************/
1490WORD32 ih264d_decode_gaps_in_frame_num(dec_struct_t *ps_dec,
1491 UWORD16 u2_frame_num)
1492{
1493 UWORD32 u4_next_frm_num, u4_start_frm_num;
1494 UWORD32 u4_max_frm_num;
1495 pocstruct_t s_tmp_poc;
1496 WORD32 i4_poc;
1497 dec_slice_params_t *ps_cur_slice;
1498
1499 dec_pic_params_t *ps_pic_params;
1500 WORD8 i1_gap_idx;
1501 WORD32 *i4_gaps_start_frm_num;
1502 dpb_manager_t *ps_dpb_mgr;
1503 WORD32 i4_frame_gaps;
1504 WORD8 *pi1_gaps_per_seq;
1505 WORD32 ret;
1506
1507 ps_cur_slice = ps_dec->ps_cur_slice;
1508 if(ps_cur_slice->u1_field_pic_flag)
1509 {
1510 if(ps_dec->u2_prev_ref_frame_num == u2_frame_num)
1511 return 0;
1512 }
1513
1514 u4_next_frm_num = ps_dec->u2_prev_ref_frame_num + 1;
1515 u4_max_frm_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1;
1516
1517 // check
1518 if(u4_next_frm_num >= u4_max_frm_num)
1519 {
1520 u4_next_frm_num -= u4_max_frm_num;
1521 }
1522
1523 if(u4_next_frm_num == u2_frame_num)
1524 {
1525 return (0);
1526 }
1527
1528 // check
1529 if((ps_dec->u1_nal_unit_type == IDR_SLICE_NAL)
1530 && (u4_next_frm_num >= u2_frame_num))
1531 {
1532 return (0);
1533 }
1534 u4_start_frm_num = u4_next_frm_num;
1535
1536 s_tmp_poc.i4_pic_order_cnt_lsb = 0;
1537 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0;
1538 s_tmp_poc.i4_pic_order_cnt_lsb = 0;
1539 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0;
1540 s_tmp_poc.i4_delta_pic_order_cnt[0] = 0;
1541 s_tmp_poc.i4_delta_pic_order_cnt[1] = 0;
1542
1543 ps_cur_slice = ps_dec->ps_cur_slice;
1544 ps_pic_params = ps_dec->ps_cur_pps;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1545
1546 i4_frame_gaps = 0;
1547 ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1548
1549 /* Find a empty slot to store gap seqn info */
1550 i4_gaps_start_frm_num = ps_dpb_mgr->ai4_gaps_start_frm_num;
1551 for(i1_gap_idx = 0; i1_gap_idx < MAX_FRAMES; i1_gap_idx++)
1552 {
1553 if(INVALID_FRAME_NUM == i4_gaps_start_frm_num[i1_gap_idx])
1554 break;
1555 }
1556 if(MAX_FRAMES == i1_gap_idx)
1557 {
1558 UWORD32 i4_error_code;
1559 i4_error_code = ERROR_DBP_MANAGER_T;
1560// i4_error_code |= 1<<IVD_CORRUPTEDDATA;
1561 return i4_error_code;
1562 }
1563
1564 i4_poc = 0;
1565 i4_gaps_start_frm_num[i1_gap_idx] = u4_start_frm_num;
1566 ps_dpb_mgr->ai4_gaps_end_frm_num[i1_gap_idx] = u2_frame_num - 1;
1567 pi1_gaps_per_seq = ps_dpb_mgr->ai1_gaps_per_seq;
1568 pi1_gaps_per_seq[i1_gap_idx] = 0;
1569 while(u4_next_frm_num != u2_frame_num)
1570 {
1571 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1572 if(ps_pic_params->ps_sps->u1_pic_order_cnt_type)
1573 {
1574 /* allocate a picture buffer and insert it as ST node */
1575 ret = ih264d_decode_pic_order_cnt(0, u4_next_frm_num,
1576 &ps_dec->s_prev_pic_poc,
1577 &s_tmp_poc, ps_cur_slice,
1578 ps_pic_params, 1, 0, 0,
1579 &i4_poc);
1580 if(ret != OK)
1581 return ret;
1582
1583 /* Display seq no calculations */
1584 if(i4_poc >= ps_dec->i4_max_poc)
1585 ps_dec->i4_max_poc = i4_poc;
1586 /* IDR Picture or POC wrap around */
1587 if(i4_poc == 0)
1588 {
1589 ps_dec->i4_prev_max_display_seq =
1590 ps_dec->i4_prev_max_display_seq
1591 + ps_dec->i4_max_poc
1592 + ps_dec->u1_max_dec_frame_buffering
1593 + 1;
1594 ps_dec->i4_max_poc = 0;
1595 }
1596
1597 ps_cur_slice->u1_mmco_equalto5 = 0;
1598 ps_cur_slice->u2_frame_num = u4_next_frm_num;
1599 }
1600
1601 // check
1602 if(ps_dpb_mgr->i1_poc_buf_id_entries
1603 >= ps_dec->u1_max_dec_frame_buffering)
1604 {
1605 ret = ih264d_assign_display_seq(ps_dec);
1606 if(ret != OK)
1607 return ret;
1608 }
1609
1610 ret = ih264d_insert_pic_in_display_list(
1611 ps_dec->ps_dpb_mgr, (WORD8) DO_NOT_DISP,
1612 (WORD32)(ps_dec->i4_prev_max_display_seq + i4_poc),
1613 u4_next_frm_num);
1614 if(ret != OK)
1615 return ret;
1616
1617 pi1_gaps_per_seq[i1_gap_idx]++;
1618 ret = ih264d_do_mmco_for_gaps(ps_dpb_mgr,
1619 ps_dec->ps_cur_sps->u1_num_ref_frames);
1620 if(ret != OK)
1621 return ret;
1622
1623 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1624
1625 u4_next_frm_num++;
1626 if(u4_next_frm_num >= u4_max_frm_num)
1627 {
1628 u4_next_frm_num -= u4_max_frm_num;
1629 }
1630
1631 i4_frame_gaps++;
1632 }
1633
1634 return OK;
1635}
1636
1637/*!
1638 **************************************************************************
1639 * \if Function name : ih264d_create_pic_buffers \endif
1640 *
1641 * \brief
1642 * This function creates Picture Buffers.
1643 *
1644 * \return
1645 * 0 on Success and -1 on error
1646 **************************************************************************
1647 */
1648WORD32 ih264d_create_pic_buffers(UWORD8 u1_num_of_buf,
1649 dec_struct_t *ps_dec)
1650{
1651 struct pic_buffer_t *ps_pic_buf;
1652 UWORD8 i;
1653 UWORD32 u4_luma_size, u4_chroma_size;
1654 UWORD8 u1_frm = ps_dec->ps_cur_sps->u1_frame_mbs_only_flag;
1655 WORD32 j;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1656 UWORD8 *pu1_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1657
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1658 ps_pic_buf = ps_dec->ps_pic_buf_base;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1659 ih264_disp_mgr_init((disp_mgr_t *)ps_dec->pv_disp_buf_mgr);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1660 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_pic_buf_mgr);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1661 u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y;
1662 u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv;
1663
1664 {
1665 if(ps_dec->u4_share_disp_buf == 1)
1666 {
1667 /* In case of buffers getting shared between application and library
1668 there is no need of reference memtabs. Instead of setting the i4_size
1669 to zero, it is reduced to a small i4_size to ensure that changes
1670 in the code are minimal */
1671 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
1672 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)
1673 || (ps_dec->u1_chroma_format == IV_YUV_420P))
1674 {
1675 u4_luma_size = 64;
1676 }
1677
1678 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1679 {
1680 u4_chroma_size = 64;
1681 }
1682
1683 }
1684 }
1685
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1686 pu1_buf = ps_dec->pu1_pic_buf_base;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1687
1688 /* Allocate memory for refernce buffers */
1689 for(i = 0; i < u1_num_of_buf; i++)
1690 {
1691 UWORD32 u4_offset;
1692 WORD32 buf_ret;
1693 UWORD8 *pu1_luma, *pu1_chroma;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1694 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1695
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1696 pu1_luma = pu1_buf;
1697 pu1_buf += ALIGN64(u4_luma_size);
1698 pu1_chroma = pu1_buf;
1699 pu1_buf += ALIGN64(u4_chroma_size);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1700
1701 /* Offset to the start of the pic from the top left corner of the frame
1702 buffer */
1703
1704 if((0 == ps_dec->u4_share_disp_buf)
1705 || (NULL == ps_dec->disp_bufs[i].buf[0]))
1706 {
1707 UWORD32 pad_len_h, pad_len_v;
1708
1709 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H;
1710 ps_pic_buf->pu1_buf1 = (UWORD8 *)(pu1_luma) + u4_offset;
1711
1712 pad_len_h = MAX(PAD_LEN_UV_H, (PAD_LEN_Y_H >> 1));
1713 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V);
1714
1715 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h;
1716
1717 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset;
1718 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset;
1719
1720 }
1721 else
1722 {
1723 UWORD32 pad_len_h, pad_len_v;
1724 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H;
1725 ps_pic_buf->pu1_buf1 = (UWORD8 *)ps_dec->disp_bufs[i].buf[0]
1726 + u4_offset;
1727
1728 ps_dec->disp_bufs[i].u4_ofst[0] = u4_offset;
1729
1730 if(ps_dec->u1_chroma_format == IV_YUV_420P)
1731 {
1732 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR,
1733 (PAD_LEN_Y_H >> 1));
1734 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V);
1735
1736 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h;
1737 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset;
1738 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset;
1739
1740 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset;
1741 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset;
1742
1743 }
1744 else
1745 {
1746 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR,
1747 (PAD_LEN_Y_H >> 1));
1748 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V);
1749
1750 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h;
1751 ps_pic_buf->pu1_buf2 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1])
1752 + u4_offset;
1753 ps_pic_buf->pu1_buf3 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1])
1754 + u4_offset;
1755
1756 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset;
1757 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1758 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1759 }
1760
1761 ps_pic_buf->u2_frm_ht_y = ps_dec->u2_frm_ht_y;
1762 ps_pic_buf->u2_frm_ht_uv = ps_dec->u2_frm_ht_uv;
1763 ps_pic_buf->u2_frm_wd_y = ps_dec->u2_frm_wd_y;
1764 ps_pic_buf->u2_frm_wd_uv = ps_dec->u2_frm_wd_uv;
1765
1766 ps_pic_buf->u1_pic_buf_id = i;
1767
1768 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
1769 ps_pic_buf, i);
1770 if(0 != buf_ret)
1771 {
1772 ps_dec->i4_error_code = ERROR_BUF_MGR;
1773 return ERROR_BUF_MGR;
1774 }
1775
1776 ps_dec->apv_buf_id_pic_buf_map[i] = (void *)ps_pic_buf;
1777 ps_pic_buf++;
1778 }
1779
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1780 if(1 == ps_dec->u4_share_disp_buf)
1781 {
1782 for(i = 0; i < u1_num_of_buf; i++)
1783 ps_dec->u4_disp_buf_mapping[i] = 1;
1784 }
1785 return OK;
1786}
1787
1788/*!
1789 **************************************************************************
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1790 * \if Function name : ih264d_allocate_dynamic_bufs \endif
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1791 *
1792 * \brief
1793 * This function allocates memory required by Decoder.
1794 *
1795 * \param ps_dec: Pointer to dec_struct_t.
1796 *
1797 * \return
1798 * Returns i4_status as returned by MemManager.
1799 *
1800 **************************************************************************
1801 */
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1802WORD16 ih264d_allocate_dynamic_bufs(dec_struct_t * ps_dec)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1803{
1804 struct MemReq s_MemReq;
1805 struct MemBlock *p_MemBlock;
1806
1807 pred_info_t *ps_pred_frame;
1808 dec_mb_info_t *ps_frm_mb_info;
1809 dec_slice_struct_t *ps_dec_slice_buf;
1810 UWORD8 *pu1_dec_mb_map, *pu1_recon_mb_map;
1811 UWORD16 *pu2_slice_num_map;
1812
1813 WORD16 *pi16_res_coeff;
1814 WORD16 i16_status = 0;
1815 UWORD8 uc_frmOrFld = (1 - ps_dec->ps_cur_sps->u1_frame_mbs_only_flag);
1816 UWORD16 u4_luma_wd = ps_dec->u2_frm_wd_y;
1817 UWORD16 u4_chroma_wd = ps_dec->u2_frm_wd_uv;
1818 WORD8 c_i = 0;
1819 dec_seq_params_t *ps_sps = ps_dec->ps_cur_sps;
1820 UWORD32 u4_total_mbs = ps_sps->u2_total_num_of_mbs << uc_frmOrFld;
1821 UWORD32 u4_wd_mbs = ps_dec->u2_frm_wd_in_mbs;
1822 UWORD32 u4_ht_mbs = ps_dec->u2_frm_ht_in_mbs;
1823 UWORD32 u4_blk_wd;
1824 UWORD32 ui_size = 0;
1825 UWORD32 u4_int_scratch_size = 0, u4_ref_pred_size = 0;
1826 UWORD8 *pu1_buf;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1827 WORD32 num_entries;
1828 WORD32 size;
1829 void *pv_buf;
1830 UWORD32 u4_num_bufs;
1831 UWORD32 u4_luma_size, u4_chroma_size;
1832 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1833
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1834 size = u4_total_mbs;
1835 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1836 RETURN_IF((NULL == pv_buf), IV_FAIL);
1837 ps_dec->pu1_dec_mb_map = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1838
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1839 size = u4_total_mbs;
1840 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1841 RETURN_IF((NULL == pv_buf), IV_FAIL);
1842 ps_dec->pu1_recon_mb_map = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1843
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1844 size = u4_total_mbs * sizeof(UWORD16);
1845 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1846 RETURN_IF((NULL == pv_buf), IV_FAIL);
1847 ps_dec->pu2_slice_num_map = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1848
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1849 /************************************************************/
1850 /* Post allocation Initialisations */
1851 /************************************************************/
1852 ps_dec->ps_parse_cur_slice = &(ps_dec->ps_dec_slice_buf[0]);
1853 ps_dec->ps_decode_cur_slice = &(ps_dec->ps_dec_slice_buf[0]);
1854 ps_dec->ps_computebs_cur_slice = &(ps_dec->ps_dec_slice_buf[0]);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1855
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1856 ps_dec->ps_pred_start = ps_dec->ps_pred;
1857
1858 size = sizeof(parse_pmbarams_t) * (ps_dec->u1_recon_mb_grp);
1859 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1860 RETURN_IF((NULL == pv_buf), IV_FAIL);
Hamsalekha S2575ae62017-04-05 11:11:39 +0530[diff] [blame]1861 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1862 ps_dec->ps_parse_mb_data = pv_buf;
1863
1864 size = sizeof(parse_part_params_t)
1865 * ((ps_dec->u1_recon_mb_grp) << 4);
1866 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1867 RETURN_IF((NULL == pv_buf), IV_FAIL);
1868 ps_dec->ps_parse_part_params = pv_buf;
1869
1870 size = ((u4_wd_mbs * sizeof(deblkmb_neighbour_t)) << uc_frmOrFld);
1871 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1872 RETURN_IF((NULL == pv_buf), IV_FAIL);
1873 ps_dec->ps_deblk_top_mb = pv_buf;
1874
1875 size = ((sizeof(ctxt_inc_mb_info_t))
1876 * (((u4_wd_mbs + 1) << uc_frmOrFld) + 1));
1877 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1878 RETURN_IF((NULL == pv_buf), IV_FAIL);
1879 ps_dec->p_ctxt_inc_mb_map = pv_buf;
1880
Harish Mahendrakarbd67b742016-04-26 16:28:57 +0530[diff] [blame]1881 /* 0th entry of CtxtIncMbMap will be always be containing default values
1882 for CABAC context representing MB not available */
1883 ps_dec->p_ctxt_inc_mb_map += 1;
1884
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1885 size = (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp
1886 * 16);
1887 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1888 RETURN_IF((NULL == pv_buf), IV_FAIL);
1889 ps_dec->ps_mv_p[0] = pv_buf;
1890
1891 size = (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp
1892 * 16);
1893 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1894 RETURN_IF((NULL == pv_buf), IV_FAIL);
1895 ps_dec->ps_mv_p[1] = pv_buf;
1896
1897 {
1898 UWORD8 i;
1899 for(i = 0; i < MV_SCRATCH_BUFS; i++)
1900 {
1901 size = (sizeof(mv_pred_t)
1902 * ps_dec->u1_recon_mb_grp * 4);
1903 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1904 RETURN_IF((NULL == pv_buf), IV_FAIL);
1905 ps_dec->ps_mv_top_p[i] = pv_buf;
1906 }
1907 }
1908
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]1909 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1910 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1911 RETURN_IF((NULL == pv_buf), IV_FAIL);
1912 ps_dec->pu1_y_intra_pred_line = pv_buf;
1913 memset(ps_dec->pu1_y_intra_pred_line, 0, size);
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]1914 ps_dec->pu1_y_intra_pred_line += MB_SIZE;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1915
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]1916 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1917 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1918 RETURN_IF((NULL == pv_buf), IV_FAIL);
1919 ps_dec->pu1_u_intra_pred_line = pv_buf;
1920 memset(ps_dec->pu1_u_intra_pred_line, 0, size);
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]1921 ps_dec->pu1_u_intra_pred_line += MB_SIZE;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1922
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]1923 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1924 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1925 RETURN_IF((NULL == pv_buf), IV_FAIL);
1926 ps_dec->pu1_v_intra_pred_line = pv_buf;
1927 memset(ps_dec->pu1_v_intra_pred_line, 0, size);
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]1928 ps_dec->pu1_v_intra_pred_line += MB_SIZE;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1929
1930 if(ps_dec->u1_separate_parse)
1931 {
Harish Mahendrakar9b095de2016-12-15 18:04:53 +0530[diff] [blame]1932 /* Needs one extra row of info, to hold top row data */
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1933 size = sizeof(mb_neigbour_params_t)
Harish Mahendrakar9b095de2016-12-15 18:04:53 +0530[diff] [blame]1934 * 2 * ((u4_wd_mbs + 2) * (u4_ht_mbs + 1));
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1935 }
1936 else
1937 {
1938 size = sizeof(mb_neigbour_params_t)
1939 * 2 * ((u4_wd_mbs + 2) << uc_frmOrFld);
1940 }
1941 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1942 RETURN_IF((NULL == pv_buf), IV_FAIL);
1943
1944 ps_dec->ps_nbr_mb_row = pv_buf;
1945 memset(ps_dec->ps_nbr_mb_row, 0, size);
1946
1947 /* Allocate deblock MB info */
1948 size = (u4_total_mbs + u4_wd_mbs) * sizeof(deblk_mb_t);
1949
1950 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1951 RETURN_IF((NULL == pv_buf), IV_FAIL);
1952 ps_dec->ps_deblk_pic = pv_buf;
1953
1954 memset(ps_dec->ps_deblk_pic, 0, size);
1955
1956 /* Allocate frame level mb info */
1957 size = sizeof(dec_mb_info_t) * u4_total_mbs;
1958 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1959 RETURN_IF((NULL == pv_buf), IV_FAIL);
1960 ps_dec->ps_frm_mb_info = pv_buf;
1961 memset(ps_dec->ps_frm_mb_info, 0, size);
1962
1963 /* Allocate memory for slice headers dec_slice_struct_t */
1964 num_entries = MAX_FRAMES;
1965 if((1 >= ps_dec->ps_cur_sps->u1_num_ref_frames) &&
1966 (0 == ps_dec->i4_display_delay))
1967 {
1968 num_entries = 1;
1969 }
1970 num_entries = ((2 * num_entries) + 1);
Hamsalekha Sa925a6b2017-04-21 11:01:52 +0530[diff] [blame]1971 num_entries *= 2;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1972
1973 size = num_entries * sizeof(void *);
1974 size += PAD_MAP_IDX_POC * sizeof(void *);
1975 size *= u4_total_mbs;
1976 size += sizeof(dec_slice_struct_t) * u4_total_mbs;
1977 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1978 RETURN_IF((NULL == pv_buf), IV_FAIL);
1979
1980 ps_dec->ps_dec_slice_buf = pv_buf;
1981 memset(ps_dec->ps_dec_slice_buf, 0, size);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1982 pu1_buf = (UWORD8 *)ps_dec->ps_dec_slice_buf;
1983 pu1_buf += sizeof(dec_slice_struct_t) * u4_total_mbs;
1984 ps_dec->pv_map_ref_idx_to_poc_buf = (void *)pu1_buf;
1985
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1986 /* Allocate memory for packed pred info */
1987 num_entries = u4_total_mbs;
Hamsalekha S9008aed2017-05-08 17:21:56 +0530[diff] [blame]1988 num_entries *= 16 * 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1989
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1990 size = sizeof(pred_info_pkd_t) * num_entries;
1991 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1992 RETURN_IF((NULL == pv_buf), IV_FAIL);
1993 ps_dec->ps_pred_pkd = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1994
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1995 /* Allocate memory for coeff data */
1996 size = MB_LUM_SIZE * sizeof(WORD16);
1997 /*For I16x16 MBs, 16 4x4 AC coeffs and 1 4x4 DC coeff TU blocks will be sent
1998 For all MBs along with 8 4x4 AC coeffs 2 2x2 DC coeff TU blocks will be sent
1999 So use 17 4x4 TU blocks for luma and 9 4x4 TU blocks for chroma */
2000 size += u4_total_mbs * (MAX(17 * sizeof(tu_sblk4x4_coeff_data_t),4 * sizeof(tu_blk8x8_coeff_data_t))
2001 + 9 * sizeof(tu_sblk4x4_coeff_data_t));
2002 //32 bytes for each mb to store u1_prev_intra4x4_pred_mode and u1_rem_intra4x4_pred_mode data
2003 size += u4_total_mbs * 32;
2004 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2005 RETURN_IF((NULL == pv_buf), IV_FAIL);
2006
2007 ps_dec->pi2_coeff_data = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2008
2009 ps_dec->pv_pic_tu_coeff_data = (void *)(ps_dec->pi2_coeff_data + MB_LUM_SIZE);
2010
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2011 /* Allocate MV bank buffer */
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2012 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2013 UWORD32 col_flag_buffer_size, mvpred_buffer_size;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2014
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2015 col_flag_buffer_size = ((ps_dec->u2_pic_wd * ps_dec->u2_pic_ht) >> 4);
2016 mvpred_buffer_size = sizeof(mv_pred_t)
2017 * ((ps_dec->u2_pic_wd * (ps_dec->u2_pic_ht + PAD_MV_BANK_ROW)) >> 4);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2018
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2019 u4_num_bufs = ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2020
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2021 u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs);
2022 u4_num_bufs = MAX(u4_num_bufs, 2);
2023 size = ALIGN64(mvpred_buffer_size) + ALIGN64(col_flag_buffer_size);
2024 size *= u4_num_bufs;
2025 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2026 RETURN_IF((NULL == pv_buf), IV_FAIL);
2027 ps_dec->pu1_mv_bank_buf_base = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2028 }
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2029
2030 /* Allocate Pic buffer */
2031 u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y;
2032 u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv;
2033
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2034 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2035 if(ps_dec->u4_share_disp_buf == 1)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2036 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2037 /* In case of buffers getting shared between application and library
2038 there is no need of reference memtabs. Instead of setting the i4_size
2039 to zero, it is reduced to a small i4_size to ensure that changes
2040 in the code are minimal */
2041 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
2042 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)
2043 || (ps_dec->u1_chroma_format == IV_YUV_420P))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2044 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2045 u4_luma_size = 64;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2046 }
2047
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2048 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2049 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2050 u4_chroma_size = 64;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2051 }
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2052
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2053 }
2054 }
2055
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2056 size = ALIGN64(u4_luma_size) + ALIGN64(u4_chroma_size);
2057 size *= ps_dec->u1_pic_bufs;
2058 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2059 RETURN_IF((NULL == pv_buf), IV_FAIL);
2060 ps_dec->pu1_pic_buf_base = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2061
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2062 /* Post allocation Increment Actions */
2063
2064 /***************************************************************************/
2065 /*Initialize cabac context pointers for every SE that has fixed contextIdx */
2066 /***************************************************************************/
2067 {
2068 bin_ctxt_model_t * const p_cabac_ctxt_table_t =
2069 ps_dec->p_cabac_ctxt_table_t;
2070 bin_ctxt_model_t * * p_coeff_abs_level_minus1_t =
2071 ps_dec->p_coeff_abs_level_minus1_t;
2072 bin_ctxt_model_t * * p_cbf_t = ps_dec->p_cbf_t;
2073
2074 ps_dec->p_mb_field_dec_flag_t = p_cabac_ctxt_table_t
2075 + MB_FIELD_DECODING_FLAG;
2076 ps_dec->p_prev_intra4x4_pred_mode_flag_t = p_cabac_ctxt_table_t
2077 + PREV_INTRA4X4_PRED_MODE_FLAG;
2078 ps_dec->p_rem_intra4x4_pred_mode_t = p_cabac_ctxt_table_t
2079 + REM_INTRA4X4_PRED_MODE;
2080 ps_dec->p_intra_chroma_pred_mode_t = p_cabac_ctxt_table_t
2081 + INTRA_CHROMA_PRED_MODE;
2082 ps_dec->p_mb_qp_delta_t = p_cabac_ctxt_table_t + MB_QP_DELTA;
2083 ps_dec->p_ref_idx_t = p_cabac_ctxt_table_t + REF_IDX;
2084 ps_dec->p_mvd_x_t = p_cabac_ctxt_table_t + MVD_X;
2085 ps_dec->p_mvd_y_t = p_cabac_ctxt_table_t + MVD_Y;
2086 p_cbf_t[0] = p_cabac_ctxt_table_t + CBF + 0;
2087 p_cbf_t[1] = p_cabac_ctxt_table_t + CBF + 4;
2088 p_cbf_t[2] = p_cabac_ctxt_table_t + CBF + 8;
2089 p_cbf_t[3] = p_cabac_ctxt_table_t + CBF + 12;
2090 p_cbf_t[4] = p_cabac_ctxt_table_t + CBF + 16;
2091 ps_dec->p_cbp_luma_t = p_cabac_ctxt_table_t + CBP_LUMA;
2092 ps_dec->p_cbp_chroma_t = p_cabac_ctxt_table_t + CBP_CHROMA;
2093
2094 p_coeff_abs_level_minus1_t[LUMA_DC_CTXCAT] = p_cabac_ctxt_table_t
2095 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_0_OFFSET;
2096
2097 p_coeff_abs_level_minus1_t[LUMA_AC_CTXCAT] = p_cabac_ctxt_table_t
2098 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_1_OFFSET;
2099
2100 p_coeff_abs_level_minus1_t[LUMA_4X4_CTXCAT] = p_cabac_ctxt_table_t
2101 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_2_OFFSET;
2102
2103 p_coeff_abs_level_minus1_t[CHROMA_DC_CTXCAT] = p_cabac_ctxt_table_t
2104 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_3_OFFSET;
2105
2106 p_coeff_abs_level_minus1_t[CHROMA_AC_CTXCAT] = p_cabac_ctxt_table_t
2107 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_4_OFFSET;
2108
2109 p_coeff_abs_level_minus1_t[LUMA_8X8_CTXCAT] = p_cabac_ctxt_table_t
2110 + COEFF_ABS_LEVEL_MINUS1_8X8
2111 + COEFF_ABS_LEVEL_CAT_5_OFFSET;
2112
2113 /********************************************************/
2114 /* context for the high profile related syntax elements */
2115 /* This is maintained seperately in s_high_profile */
2116 /********************************************************/
2117 {
2118
2119 ps_dec->s_high_profile.ps_transform8x8_flag = p_cabac_ctxt_table_t
2120 + TRANSFORM_SIZE_8X8_FLAG;
2121
2122 ps_dec->s_high_profile.ps_sigcoeff_8x8_frame = p_cabac_ctxt_table_t
2123 + SIGNIFICANT_COEFF_FLAG_8X8_FRAME;
2124
2125 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_frame =
2126 p_cabac_ctxt_table_t
2127 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FRAME;
2128
2129 ps_dec->s_high_profile.ps_coeff_abs_levelminus1 =
2130 p_cabac_ctxt_table_t + COEFF_ABS_LEVEL_MINUS1_8X8;
2131
2132 ps_dec->s_high_profile.ps_sigcoeff_8x8_field = p_cabac_ctxt_table_t
2133 + SIGNIFICANT_COEFF_FLAG_8X8_FIELD;
2134
2135 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_field =
2136 p_cabac_ctxt_table_t
2137 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FIELD;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2138 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2139 }
2140 return (i16_status);
2141}
2142
2143/*!
2144 **************************************************************************
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2145 * \if Function name : ih264d_free_dynamic_bufs \endif
2146 *
2147 * \brief
2148 * This function frees dynamic memory allocated by Decoder.
2149 *
2150 * \param ps_dec: Pointer to dec_struct_t.
2151 *
2152 * \return
2153 * Returns i4_status as returned by MemManager.
2154 *
2155 **************************************************************************
2156 */
2157WORD16 ih264d_free_dynamic_bufs(dec_struct_t * ps_dec)
2158{
2159 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_dynamic);
2160
2161 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_pic);
2162 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_dec_mb_map);
2163 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_recon_mb_map);
2164 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu2_slice_num_map);
2165 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_slice_buf);
2166 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_frm_mb_info);
2167 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_coeff_data);
2168 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_mb_data);
2169 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_part_params);
2170 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_top_mb);
2171
2172 if(ps_dec->p_ctxt_inc_mb_map)
2173 {
2174 ps_dec->p_ctxt_inc_mb_map -= 1;
2175 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_ctxt_inc_mb_map);
2176 }
2177
2178 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[0]);
2179 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[1]);
2180 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred_pkd);
2181 {
2182 UWORD8 i;
2183 for(i = 0; i < MV_SCRATCH_BUFS; i++)
2184 {
2185 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_top_p[i]);
2186 }
2187 }
2188
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]2189 if(ps_dec->pu1_y_intra_pred_line)
2190 {
2191 ps_dec->pu1_y_intra_pred_line -= MB_SIZE;
2192 }
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2193 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_y_intra_pred_line);
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]2194
2195 if(ps_dec->pu1_u_intra_pred_line)
2196 {
2197 ps_dec->pu1_u_intra_pred_line -= MB_SIZE;
2198 }
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2199 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_u_intra_pred_line);
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]2200
2201 if(ps_dec->pu1_v_intra_pred_line)
2202 {
2203 ps_dec->pu1_v_intra_pred_line -= MB_SIZE;
2204 }
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2205 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_v_intra_pred_line);
2206 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_nbr_mb_row);
2207 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_mv_bank_buf_base);
2208 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_pic_buf_base);
2209 return 0;
2210}
2211
2212/*!
2213 **************************************************************************
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2214 * \if Function name : ih264d_create_mv_bank \endif
2215 *
2216 * \brief
2217 * This function creates MV bank.
2218 *
2219 * \param memType : Type of memory being handled
2220 * 0: Display Buffer
2221 * 1: Decoder Buffer
2222 * 2: Internal Buffer
2223 * \param u1_num_of_buf: Number of decode or display buffers.
2224 * \param u4_wd : Frame width.
2225 * \param u4_ht : Frame Height.
2226 * \param ps_pic_buf_api : Pointer to Picture Buffer API.
2227 * \param ih264d_dec_mem_manager : Memory manager utility supplied by system.
2228 *
2229 * \return
2230 * 0 on Success and -1 on error
2231 *
2232 **************************************************************************
2233 */
2234WORD32 ih264d_create_mv_bank(void *pv_dec,
2235 UWORD32 ui_width,
2236 UWORD32 ui_height)
2237{
2238 UWORD8 i;
2239 UWORD32 col_flag_buffer_size, mvpred_buffer_size;
2240 UWORD8 *pu1_mv_buf_mgr_base, *pu1_mv_bank_base;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2241 col_mv_buf_t *ps_col_mv;
2242 mv_pred_t *ps_mv;
2243 UWORD8 *pu1_col_zero_flag_buf;
2244 dec_struct_t *ps_dec = (dec_struct_t *)pv_dec;
2245 WORD32 buf_ret;
Hamsalekha S8a503282015-07-28 14:41:24 +0530[diff] [blame]2246 UWORD32 u4_num_bufs;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2247 UWORD8 *pu1_buf;
2248 WORD32 size;
2249 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2250
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2251 col_flag_buffer_size = ((ui_width * ui_height) >> 4);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2252 mvpred_buffer_size = sizeof(mv_pred_t)
2253 * ((ui_width * (ui_height + PAD_MV_BANK_ROW)) >> 4);
2254
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2255 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_mv_buf_mgr);
2256
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2257 ps_col_mv = ps_dec->ps_col_mv_base;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2258
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2259 u4_num_bufs = ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
Hamsalekha S8a503282015-07-28 14:41:24 +0530[diff] [blame]2260
2261 u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2262 u4_num_bufs = MAX(u4_num_bufs, 2);
2263 pu1_buf = ps_dec->pu1_mv_bank_buf_base;
Hamsalekha S8a503282015-07-28 14:41:24 +0530[diff] [blame]2264 for(i = 0 ; i < u4_num_bufs ; i++)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2265 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2266 pu1_col_zero_flag_buf = pu1_buf;
2267 pu1_buf += ALIGN64(col_flag_buffer_size);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2268
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2269 ps_mv = (mv_pred_t *)pu1_buf;
2270 pu1_buf += ALIGN64(mvpred_buffer_size);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2271
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2272 memset(ps_mv, 0, ((ui_width * OFFSET_MV_BANK_ROW) >> 4) * sizeof(mv_pred_t));
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2273 ps_mv += (ui_width*OFFSET_MV_BANK_ROW) >> 4;
2274
2275 ps_col_mv->pv_col_zero_flag = (void *)pu1_col_zero_flag_buf;
2276 ps_col_mv->pv_mv = (void *)ps_mv;
2277 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_mv_buf_mgr, ps_col_mv, i);
2278 if(0 != buf_ret)
2279 {
2280 ps_dec->i4_error_code = ERROR_BUF_MGR;
2281 return ERROR_BUF_MGR;
2282 }
2283 ps_col_mv++;
2284 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2285 return OK;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2286}
2287
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2288void ih264d_unpack_coeff4x4_dc_4x4blk(tu_sblk4x4_coeff_data_t *ps_tu_4x4,
2289 WORD16 *pi2_out_coeff_data,
2290 UWORD8 *pu1_inv_scan)
2291{
2292 UWORD16 u2_sig_coeff_map = ps_tu_4x4->u2_sig_coeff_map;
2293 WORD32 idx;
2294 WORD16 *pi2_coeff_data = &ps_tu_4x4->ai2_level[0];
2295
2296 while(u2_sig_coeff_map)
2297 {
2298 idx = CLZ(u2_sig_coeff_map);
2299
2300 idx = 31 - idx;
2301 RESET_BIT(u2_sig_coeff_map,idx);
2302
2303 idx = pu1_inv_scan[idx];
2304 pi2_out_coeff_data[idx] = *pi2_coeff_data++;
2305
2306 }
2307}