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gerrit-public.fairphone.software / platform / external / libavc / refs/tags/rel/13/fp3/6.A.023.1 / . / decoder / ih264d_utils.c
blob: 93c379b34160a4f076955287150682d3302d6761 [file] [log] [blame]
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1/******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19*/
20/*!
21 **************************************************************************
22 * \file ih264d_utils.c
23 *
24 * \brief
25 * Contains routines that handle of start and end of pic processing
26 *
27 * \date
28 * 19/12/2002
29 *
30 * \author AI
31 **************************************************************************
32 */
33
34#include <string.h>
35#include "ih264_typedefs.h"
36#include "ithread.h"
37#include "ih264d_deblocking.h"
38#include "ih264d_parse_slice.h"
39#include "ih264d_parse_cavlc.h"
40#include "ih264d_dpb_manager.h"
41#include "ih264d_defs.h"
42#include "ih264d_structs.h"
43#include "ih264d_mem_request.h"
44#include "ih264_typedefs.h"
45#include "ih264_macros.h"
46#include "ih264_platform_macros.h"
47#include "ih264d_tables.h"
48#include "ih264d_debug.h"
49#include "ih264d_mb_utils.h"
50#include "ih264d_error_handler.h"
51#include "ih264d_dpb_manager.h"
52#include "ih264d_utils.h"
53#include "ih264d_defs.h"
54#include "ih264d_tables.h"
55#include "ih264d_inter_pred.h"
56#include "ih264d_dpb_manager.h"
57#include "iv.h"
58#include "ivd.h"
59#include "ih264d_format_conv.h"
60#include "ih264_error.h"
61#include "ih264_disp_mgr.h"
62#include "ih264_buf_mgr.h"
63#include "ih264d_utils.h"
64
65/*!
66 **************************************************************************
67 * \if Function name : ih264d_is_end_of_pic \endif
68 *
69 * \brief
70 * Determines whether current slice is first slice of a new picture as
71 * defined in 7.4.1.2.4 of 14496-10.
72 *
73 * \return
74 * Return 1 if current slice is first slice of a new picture
75 * Otherwise it returns 0
76 **************************************************************************
77 */
78UWORD8 ih264d_is_end_of_pic(UWORD16 u2_frame_num,
79 UWORD8 u1_nal_ref_idc,
80 pocstruct_t *ps_cur_poc,
81 pocstruct_t *ps_prev_poc,
82 dec_slice_params_t * ps_prev_slice, /*!< Previous slice parameters*/
83 UWORD8 u1_pic_order_cnt_type,
84 UWORD8 u1_nal_unit_type,
85 UWORD32 u4_idr_pic_id,
86 UWORD8 u1_field_pic_flag,
87 UWORD8 u1_bottom_field_flag)
88{
89 WORD8 i1_is_end_of_pic;
90 WORD8 a, b, c, d, e, f, g, h;
91
92 a = b = c = d = e = f = g = h = 0;
93 a = (ps_prev_slice->u2_frame_num != u2_frame_num);
94 b = (ps_prev_slice->u1_field_pic_flag != u1_field_pic_flag);
95 if(u1_field_pic_flag && ps_prev_slice->u1_field_pic_flag)
96 c = (u1_bottom_field_flag != ps_prev_slice->u1_bottom_field_flag);
97 d =
98 (u1_nal_ref_idc == 0 && ps_prev_slice->u1_nal_ref_idc != 0)
99 || (u1_nal_ref_idc != 0
100 && ps_prev_slice->u1_nal_ref_idc
101 == 0);
102 if(!a)
103 {
104 if((u1_pic_order_cnt_type == 0)
105 && (ps_prev_slice->u1_pic_order_cnt_type == 0))
106 {
107 e =
108 ((ps_cur_poc->i4_pic_order_cnt_lsb
109 != ps_prev_poc->i4_pic_order_cnt_lsb)
110 || (ps_cur_poc->i4_delta_pic_order_cnt_bottom
111 != ps_prev_poc->i4_delta_pic_order_cnt_bottom));
112 }
113
114 if((u1_pic_order_cnt_type == 1)
115 && (ps_prev_slice->u1_pic_order_cnt_type == 1))
116 {
117 f =
118 ((ps_cur_poc->i4_delta_pic_order_cnt[0]
119 != ps_prev_poc->i4_delta_pic_order_cnt[0])
120 || (ps_cur_poc->i4_delta_pic_order_cnt[1]
121 != ps_prev_poc->i4_delta_pic_order_cnt[1]));
122 }
123 }
124
125 if((u1_nal_unit_type == IDR_SLICE_NAL)
126 && (ps_prev_slice->u1_nal_unit_type == IDR_SLICE_NAL))
127 {
128 g = (u4_idr_pic_id != ps_prev_slice->u4_idr_pic_id);
129 }
130
131 if((u1_nal_unit_type == IDR_SLICE_NAL)
132 && (ps_prev_slice->u1_nal_unit_type != IDR_SLICE_NAL))
133 {
134 h = 1;
135 }
136 i1_is_end_of_pic = a + b + c + d + e + f + g + h;
137 return (i1_is_end_of_pic);
138}
139
140/*!
141 **************************************************************************
142 * \if Function name : ih264d_decode_pic_order_cnt \endif
143 *
144 * \brief
145 * Calculates picture order count of picture.
146 *
147 * \return
148 * Returns the pic order count of the picture to which current
149 * Slice belongs.
150 *
151 **************************************************************************
152 */
153WORD32 ih264d_decode_pic_order_cnt(UWORD8 u1_is_idr_slice,
154 UWORD32 u2_frame_num,
155 pocstruct_t *ps_prev_poc,
156 pocstruct_t *ps_cur_poc,
157 dec_slice_params_t *ps_cur_slice, /*!< Pointer to current slice Params*/
158 dec_pic_params_t * ps_pps,
159 UWORD8 u1_nal_ref_idc,
160 UWORD8 u1_bottom_field_flag,
161 UWORD8 u1_field_pic_flag,
162 WORD32 *pi4_poc)
163{
Shivaansh Agrawal6efeedf2020-11-17 20:56:42 +0530[diff] [blame]164 WORD64 i8_pic_msb;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]165 WORD32 i4_top_field_order_cnt = 0, i4_bottom_field_order_cnt = 0;
166 dec_seq_params_t *ps_seq = ps_pps->ps_sps;
167 WORD32 i4_prev_frame_num_ofst;
168
169 switch(ps_seq->u1_pic_order_cnt_type)
170 {
171 case 0:
172 /* POC TYPE 0 */
173 if(u1_is_idr_slice)
174 {
175 ps_prev_poc->i4_pic_order_cnt_msb = 0;
176 ps_prev_poc->i4_pic_order_cnt_lsb = 0;
177 }
178 if(ps_prev_poc->u1_mmco_equalto5)
179 {
180 if(ps_prev_poc->u1_bot_field != 1)
181 {
182 ps_prev_poc->i4_pic_order_cnt_msb = 0;
183 ps_prev_poc->i4_pic_order_cnt_lsb =
184 ps_prev_poc->i4_top_field_order_count;
185 }
186 else
187 {
188 ps_prev_poc->i4_pic_order_cnt_msb = 0;
189 ps_prev_poc->i4_pic_order_cnt_lsb = 0;
190 }
191 }
192
193 if((ps_cur_poc->i4_pic_order_cnt_lsb
194 < ps_prev_poc->i4_pic_order_cnt_lsb)
195 && ((ps_prev_poc->i4_pic_order_cnt_lsb
196 - ps_cur_poc->i4_pic_order_cnt_lsb)
197 >= (ps_seq->i4_max_pic_order_cntLsb
198 >> 1)))
199 {
Shivaansh Agrawal6efeedf2020-11-17 20:56:42 +0530[diff] [blame]200 i8_pic_msb = (WORD64)ps_prev_poc->i4_pic_order_cnt_msb
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]201 + ps_seq->i4_max_pic_order_cntLsb;
202 }
203 else if((ps_cur_poc->i4_pic_order_cnt_lsb
204 > ps_prev_poc->i4_pic_order_cnt_lsb)
205 && ((ps_cur_poc->i4_pic_order_cnt_lsb
206 - ps_prev_poc->i4_pic_order_cnt_lsb)
207 >= (ps_seq->i4_max_pic_order_cntLsb
208 >> 1)))
209 {
Shivaansh Agrawal6efeedf2020-11-17 20:56:42 +0530[diff] [blame]210 i8_pic_msb = (WORD64)ps_prev_poc->i4_pic_order_cnt_msb
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]211 - ps_seq->i4_max_pic_order_cntLsb;
212 }
213 else
214 {
Shivaansh Agrawal6efeedf2020-11-17 20:56:42 +0530[diff] [blame]215 i8_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]216 }
217
218 if(!u1_field_pic_flag || !u1_bottom_field_flag)
Shivaansh Agrawal6efeedf2020-11-17 20:56:42 +0530[diff] [blame]219 {
220 WORD64 i8_result = i8_pic_msb + ps_cur_poc->i4_pic_order_cnt_lsb;
221 if(IS_OUT_OF_RANGE_S32(i8_result))
222 {
223 return ERROR_INV_POC;
224 }
225 i4_top_field_order_cnt = i8_result;
226 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]227
228 if(!u1_field_pic_flag)
229 {
Shivaansh Agrawal6efeedf2020-11-17 20:56:42 +0530[diff] [blame]230 WORD64 i8_result = (WORD64)i4_top_field_order_cnt
231 + ps_cur_poc->i4_delta_pic_order_cnt_bottom;
232 if(IS_OUT_OF_RANGE_S32(i8_result))
233 {
234 return ERROR_INV_POC;
235 }
236 i4_bottom_field_order_cnt = i8_result;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]237 }
238 else if(u1_bottom_field_flag)
239 {
Shivaansh Agrawal6efeedf2020-11-17 20:56:42 +0530[diff] [blame]240 WORD64 i8_result = i8_pic_msb + ps_cur_poc->i4_pic_order_cnt_lsb;
241 if(IS_OUT_OF_RANGE_S32(i8_result))
242 {
243 return ERROR_INV_POC;
244 }
245 i4_bottom_field_order_cnt = i8_result;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]246 }
Shivaansh Agrawal6efeedf2020-11-17 20:56:42 +0530[diff] [blame]247
248 if(IS_OUT_OF_RANGE_S32(i8_pic_msb))
249 {
250 return ERROR_INV_POC;
251 }
252 ps_cur_poc->i4_pic_order_cnt_msb = i8_pic_msb;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]253 break;
254
255 case 1:
256 {
257 /* POC TYPE 1 */
258 UWORD8 i;
259 WORD32 prev_frame_num;
260 WORD32 frame_num_ofst;
261 WORD32 abs_frm_num;
262 WORD32 poc_cycle_cnt, frame_num_in_poc_cycle;
Isha Kulkarni34769a52019-01-28 17:43:35 +0530[diff] [blame]263 WORD64 i8_expected_delta_poc_cycle;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]264 WORD32 expected_poc;
Isha Kulkarni34769a52019-01-28 17:43:35 +0530[diff] [blame]265 WORD64 i8_result;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]266
267 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num;
268 if(!u1_is_idr_slice)
269 {
270 if(ps_cur_slice->u1_mmco_equalto5)
271 {
272 prev_frame_num = 0;
273 i4_prev_frame_num_ofst = 0;
274 }
275 else
276 {
277 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst;
278 }
279 }
280 else
281 i4_prev_frame_num_ofst = 0;
282
283 /* 1. Derivation for FrameNumOffset */
284 if(u1_is_idr_slice)
285 {
286 frame_num_ofst = 0;
287 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
288 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
289 }
290 else if(prev_frame_num > ((WORD32)u2_frame_num))
291 {
Shivaansh Agrawal6efeedf2020-11-17 20:56:42 +0530[diff] [blame]292 WORD64 i8_result = i4_prev_frame_num_ofst
293 + (WORD64)ps_seq->u2_u4_max_pic_num_minus1 + 1;
294 if(IS_OUT_OF_RANGE_S32(i8_result))
295 {
296 return ERROR_INV_FRAME_NUM;
297 }
298 frame_num_ofst = i8_result;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]299 }
300 else
301 frame_num_ofst = i4_prev_frame_num_ofst;
302
303 /* 2. Derivation for absFrameNum */
304 if(0 != ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle)
Shivaansh Agrawal6efeedf2020-11-17 20:56:42 +0530[diff] [blame]305 {
306 WORD64 i8_result = frame_num_ofst + (WORD64)u2_frame_num;
307 if(IS_OUT_OF_RANGE_S32(i8_result))
308 {
309 return ERROR_INV_FRAME_NUM;
310 }
311 abs_frm_num = i8_result;
312 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]313 else
314 abs_frm_num = 0;
315 if((u1_nal_ref_idc == 0) && (abs_frm_num > 0))
316 abs_frm_num = abs_frm_num - 1;
317
318 /* 4. expectedDeltaPerPicOrderCntCycle is derived as */
Isha Kulkarni34769a52019-01-28 17:43:35 +0530[diff] [blame]319 i8_expected_delta_poc_cycle = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]320 for(i = 0; i < ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle;
321 i++)
322 {
Isha Kulkarni34769a52019-01-28 17:43:35 +0530[diff] [blame]323 i8_expected_delta_poc_cycle +=
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]324 ps_seq->i4_ofst_for_ref_frame[i];
325 }
326
327 /* 3. When absFrameNum > 0, picOrderCntCycleCnt and
328 frame_num_in_poc_cycle are derived as : */
329 /* 5. expectedPicOrderCnt is derived as : */
330 if(abs_frm_num > 0)
331 {
332 poc_cycle_cnt =
333 DIV((abs_frm_num - 1),
334 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle);
335 frame_num_in_poc_cycle =
336 MOD((abs_frm_num - 1),
337 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle);
338
Isha Kulkarni34769a52019-01-28 17:43:35 +0530[diff] [blame]339 i8_result = poc_cycle_cnt
340 * i8_expected_delta_poc_cycle;
341
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]342 for(i = 0; i <= frame_num_in_poc_cycle; i++)
343 {
Isha Kulkarni34769a52019-01-28 17:43:35 +0530[diff] [blame]344 i8_result = i8_result
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]345 + ps_seq->i4_ofst_for_ref_frame[i];
346 }
Isha Kulkarni34769a52019-01-28 17:43:35 +0530[diff] [blame]347
Isha Kulkarni89daff52019-05-13 16:53:50 +0530[diff] [blame]348 if(IS_OUT_OF_RANGE_S32(i8_result))
349 return ERROR_INV_POC;
350
351 expected_poc = (WORD32)i8_result;
352
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]353 }
354 else
355 expected_poc = 0;
356
357 if(u1_nal_ref_idc == 0)
358 {
Harish Mahendrakar1d672d22019-07-03 10:12:53 -0700[diff] [blame]359 i8_result = (WORD64)expected_poc
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]360 + ps_seq->i4_ofst_for_non_ref_pic;
Isha Kulkarni89daff52019-05-13 16:53:50 +0530[diff] [blame]361
362 if(IS_OUT_OF_RANGE_S32(i8_result))
363 return ERROR_INV_POC;
364
365 expected_poc = (WORD32)i8_result;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]366 }
367
368 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */
369 if(!u1_field_pic_flag)
370 {
Harish Mahendrakar1d672d22019-07-03 10:12:53 -0700[diff] [blame]371 i8_result = (WORD64)expected_poc
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]372 + ps_cur_poc->i4_delta_pic_order_cnt[0];
Isha Kulkarni89daff52019-05-13 16:53:50 +0530[diff] [blame]373
374 if(IS_OUT_OF_RANGE_S32(i8_result))
375 return ERROR_INV_POC;
376 i4_top_field_order_cnt = (WORD32)i8_result;
377
Harish Mahendrakar1d672d22019-07-03 10:12:53 -0700[diff] [blame]378 i8_result = (WORD64)i4_top_field_order_cnt
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]379 + ps_seq->i4_ofst_for_top_to_bottom_field
380 + ps_cur_poc->i4_delta_pic_order_cnt[1];
Isha Kulkarni89daff52019-05-13 16:53:50 +0530[diff] [blame]381
382 if(IS_OUT_OF_RANGE_S32(i8_result))
383 return ERROR_INV_POC;
384 i4_bottom_field_order_cnt = (WORD32)i8_result;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]385 }
386 else if(!u1_bottom_field_flag)
387 {
Harish Mahendrakar1d672d22019-07-03 10:12:53 -0700[diff] [blame]388 i8_result = (WORD64)expected_poc
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]389 + ps_cur_poc->i4_delta_pic_order_cnt[0];
Isha Kulkarni89daff52019-05-13 16:53:50 +0530[diff] [blame]390
391 if(IS_OUT_OF_RANGE_S32(i8_result))
392 return ERROR_INV_POC;
393 i4_top_field_order_cnt = (WORD32)i8_result;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]394 }
395 else
396 {
Harish Mahendrakar1d672d22019-07-03 10:12:53 -0700[diff] [blame]397 i8_result = (WORD64)expected_poc
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]398 + ps_seq->i4_ofst_for_top_to_bottom_field
399 + ps_cur_poc->i4_delta_pic_order_cnt[0];
Isha Kulkarni89daff52019-05-13 16:53:50 +0530[diff] [blame]400
401 if(IS_OUT_OF_RANGE_S32(i8_result))
402 return ERROR_INV_POC;
403 i4_bottom_field_order_cnt = (WORD32)i8_result;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]404 }
405 /* Copy the current POC info into Previous POC structure */
406 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst;
407 }
408
409 break;
410 case 2:
411 {
412 /* POC TYPE 2 */
413 WORD32 prev_frame_num;
414 WORD32 frame_num_ofst;
415 WORD32 tmp_poc;
416
417 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num;
418 if(!u1_is_idr_slice)
419 {
420 if(ps_cur_slice->u1_mmco_equalto5)
421 {
422 prev_frame_num = 0;
423 i4_prev_frame_num_ofst = 0;
424 }
425 else
426 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst;
427 }
428 else
429 i4_prev_frame_num_ofst = 0;
430
431 /* 1. Derivation for FrameNumOffset */
432 if(u1_is_idr_slice)
433 {
434 frame_num_ofst = 0;
435 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
436 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
437 }
438 else if(prev_frame_num > ((WORD32)u2_frame_num))
439 {
Shivaansh Agrawal6efeedf2020-11-17 20:56:42 +0530[diff] [blame]440 WORD64 i8_result = i4_prev_frame_num_ofst
441 + (WORD64)ps_seq->u2_u4_max_pic_num_minus1 + 1;
442 if(IS_OUT_OF_RANGE_S32(i8_result))
443 {
444 return ERROR_INV_FRAME_NUM;
445 }
446 frame_num_ofst = i8_result;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]447 }
448 else
449 frame_num_ofst = i4_prev_frame_num_ofst;
450
451 /* 2. Derivation for tempPicOrderCnt */
452 if(u1_is_idr_slice)
453 tmp_poc = 0;
454 else if(u1_nal_ref_idc == 0)
Shivaansh Agrawal6efeedf2020-11-17 20:56:42 +0530[diff] [blame]455 {
456 WORD64 i8_result = ((frame_num_ofst + (WORD64)u2_frame_num) << 1) - 1;
457 if(IS_OUT_OF_RANGE_S32(i8_result))
458 {
459 return ERROR_INV_POC;
460 }
461 tmp_poc = i8_result;
462 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]463 else
Shivaansh Agrawal6efeedf2020-11-17 20:56:42 +0530[diff] [blame]464 {
465 WORD64 i8_result = (frame_num_ofst + (WORD64)u2_frame_num) << 1;
466 if(IS_OUT_OF_RANGE_S32(i8_result))
467 {
468 return ERROR_INV_POC;
469 }
470 tmp_poc = i8_result;
471 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]472
473 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */
474 if(!u1_field_pic_flag)
475 {
476 i4_top_field_order_cnt = tmp_poc;
477 i4_bottom_field_order_cnt = tmp_poc;
478 }
479 else if(!u1_bottom_field_flag)
480 i4_top_field_order_cnt = tmp_poc;
481 else
482 i4_bottom_field_order_cnt = tmp_poc;
483
484 /* Copy the current POC info into Previous POC structure */
485 ps_prev_poc->i4_prev_frame_num_ofst = frame_num_ofst;
486 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst;
487 }
488 break;
489 default:
490 return ERROR_INV_POC_TYPE_T;
491 break;
492 }
493
494 if(!u1_field_pic_flag) // or a complementary field pair
495 {
496 *pi4_poc = MIN(i4_top_field_order_cnt, i4_bottom_field_order_cnt);
497 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt;
498 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt;
499 }
500 else if(!u1_bottom_field_flag)
501 {
502 *pi4_poc = i4_top_field_order_cnt;
503 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt;
504 }
505 else
506 {
507 *pi4_poc = i4_bottom_field_order_cnt;
508 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt;
509 }
510
511 ps_pps->i4_avg_poc = *pi4_poc;
512
513 return OK;
514}
515
516/*!
517 **************************************************************************
518 * \if Function name : ih264d_end_of_pic_processing \endif
519 *
520 * \brief
521 * Performs the end of picture processing.
522 *
523 * It performs deblocking on the current picture and sets the i4_status of
524 * current picture as decoded.
525 *
526 * \return
527 * 0 on Success and Error code otherwise.
528 **************************************************************************
529 */
530WORD32 ih264d_end_of_pic_processing(dec_struct_t *ps_dec)
531{
532 UWORD8 u1_pic_type, u1_nal_ref_idc;
533 dec_slice_params_t *ps_cur_slice = ps_dec->ps_cur_slice;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]534
535 /* If nal_ref_idc is equal to 0 for one slice or slice data partition NAL
536 unit of a particular picture, it shall be equal to 0 for all slice and
537 slice data partition NAL units of the picture. nal_ref_idc greater
538 than 0 indicates that the content of the NAL unit belongs to a decoded
539 picture that is stored and marked for use as a reference picture in the
540 decoded picture buffer. */
541
542 /* 1. Do MMCO
543 2. Add Cur Pic to list of reference pics.
544 */
545
546 /* Call MMCO */
547 u1_pic_type = 0;
548 u1_nal_ref_idc = ps_cur_slice->u1_nal_ref_idc;
549
550 if(u1_nal_ref_idc)
551 {
552 if(ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
553 {
Shivaansh Agrawal2a28c972020-08-27 19:17:35 +0530[diff] [blame]554 ps_dec->ps_dpb_mgr->u1_mmco_error_in_seq = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]555 if(ps_dec->ps_dpb_cmds->u1_long_term_reference_flag == 0)
556 {
557 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr);
Harish Mahendrakar27b7a142016-04-26 17:23:03 +0530[diff] [blame]558 /* ignore DPB errors */
559 ih264d_insert_st_node(ps_dec->ps_dpb_mgr,
560 ps_dec->ps_cur_pic,
561 ps_dec->u1_pic_buf_id,
562 ps_cur_slice->u2_frame_num);
Aasaipriya Chandran083b9fc2020-06-10 13:42:04 +0530[diff] [blame]563 ps_dec->ps_dpb_mgr->u1_max_lt_frame_idx = NO_LONG_TERM_INDICIES;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]564 }
565 else
566 {
567 /* Equivalent of inserting a pic directly as longterm Pic */
568
569 {
Harish Mahendrakar27b7a142016-04-26 17:23:03 +0530[diff] [blame]570 /* ignore DPB errors */
571 ih264d_insert_st_node(ps_dec->ps_dpb_mgr,
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]572 ps_dec->ps_cur_pic,
573 ps_dec->u1_pic_buf_id,
574 ps_cur_slice->u2_frame_num);
Harish Mahendrakar27b7a142016-04-26 17:23:03 +0530[diff] [blame]575
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]576 /* Set longTermIdx = 0, MaxLongTermFrameIdx = 0 */
Harish Mahendrakar27b7a142016-04-26 17:23:03 +0530[diff] [blame]577 ih264d_delete_st_node_or_make_lt(
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]578 ps_dec->ps_dpb_mgr,
579 ps_cur_slice->u2_frame_num, 0,
580 ps_cur_slice->u1_field_pic_flag);
Harish Mahendrakar27b7a142016-04-26 17:23:03 +0530[diff] [blame]581
Aasaipriya Chandran083b9fc2020-06-10 13:42:04 +0530[diff] [blame]582 ps_dec->ps_dpb_mgr->u1_max_lt_frame_idx = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]583 }
584 }
585 }
586 else
587 {
588
589 {
590 UWORD16 u2_pic_num = ps_cur_slice->u2_frame_num;
591
Shivaansh Agrawal2a28c972020-08-27 19:17:35 +0530[diff] [blame]592 if(!ps_dec->ps_dpb_mgr->u1_mmco_error_in_seq)
593 {
594 WORD32 ret = ih264d_do_mmco_buffer(ps_dec->ps_dpb_cmds, ps_dec->ps_dpb_mgr,
595 ps_dec->ps_cur_sps->u1_num_ref_frames, u2_pic_num,
596 (ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1),
597 ps_dec->u1_nal_unit_type, ps_dec->ps_cur_pic,
598 ps_dec->u1_pic_buf_id,
599 ps_cur_slice->u1_field_pic_flag,
600 ps_dec->e_dec_status);
601 ps_dec->ps_dpb_mgr->u1_mmco_error_in_seq = ret != OK;
602 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]603 }
604 }
605 ih264d_update_default_index_list(ps_dec->ps_dpb_mgr);
606 }
607
608 if(ps_cur_slice->u1_field_pic_flag)
609 {
610 if(ps_cur_slice->u1_bottom_field_flag)
611 {
612 if(u1_nal_ref_idc)
613 u1_pic_type = u1_pic_type | BOT_REF;
614 u1_pic_type = u1_pic_type | BOT_FLD;
615 }
616 else
617 {
618 if(u1_nal_ref_idc)
619 u1_pic_type = u1_pic_type | TOP_REF;
620 u1_pic_type = u1_pic_type | TOP_FLD;
621 }
622 }
623 else
624 u1_pic_type = TOP_REF | BOT_REF;
625 ps_dec->ps_cur_pic->u1_pic_type |= u1_pic_type;
626
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]627
628 if(ps_cur_slice->u1_field_pic_flag)
629 {
630 H264_DEC_DEBUG_PRINT("Toggling secondField\n");
631 ps_dec->u1_second_field = 1 - ps_dec->u1_second_field;
632 }
633
634 return OK;
635}
636
637/*****************************************************************************/
638/* */
639/* Function Name : init_dpb_size */
640/* */
641/* Description : This function calculates the DBP i4_size in frames */
642/* Inputs : ps_seq - current sequence params */
643/* */
644/* Globals : None */
645/* */
646/* Outputs : None */
647/* */
648/* Returns : DPB in frames */
649/* */
650/* Issues : None */
651/* */
652/* Revision History: */
653/* */
654/* DD MM YYYY Author(s) Changes (Describe the changes made) */
655/* 28 04 2005 NS Draft */
656/* */
657/*****************************************************************************/
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]658WORD32 ih264d_get_dpb_size(dec_seq_params_t *ps_seq)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]659{
660 WORD32 i4_size;
661 UWORD8 u1_level_idc;
662
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]663 u1_level_idc = ps_seq->u1_level_idc;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]664
665 switch(u1_level_idc)
666 {
667 case 10:
668 i4_size = 152064;
669 break;
670 case 11:
671 i4_size = 345600;
672 break;
673 case 12:
674 i4_size = 912384;
675 break;
676 case 13:
677 i4_size = 912384;
678 break;
679 case 20:
680 i4_size = 912384;
681 break;
682 case 21:
683 i4_size = 1824768;
684 break;
685 case 22:
686 i4_size = 3110400;
687 break;
688 case 30:
689 i4_size = 3110400;
690 break;
691 case 31:
692 i4_size = 6912000;
693 break;
694 case 32:
695 i4_size = 7864320;
696 break;
697 case 40:
698 i4_size = 12582912;
699 break;
700 case 41:
701 i4_size = 12582912;
702 break;
703 case 42:
704 i4_size = 12582912;
705 break;
706 case 50:
707 i4_size = 42393600;
708 break;
709 case 51:
710 i4_size = 70778880;
711 break;
Hamsalekha S9327d0e2015-05-20 17:07:10 +0530[diff] [blame]712 case 52:
713 i4_size = 70778880;
714 break;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]715 default:
Hamsalekha S9327d0e2015-05-20 17:07:10 +0530[diff] [blame]716 i4_size = 70778880;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]717 break;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]718 }
719
Marco Nelissen8ef4c3f2015-06-03 07:26:32 -0700[diff] [blame]720 i4_size /= (ps_seq->u2_frm_wd_in_mbs * (ps_seq->u2_frm_ht_in_mbs << (1 - ps_seq->u1_frame_mbs_only_flag)));
721 i4_size /= 384;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]722 i4_size = MIN(i4_size, 16);
723 i4_size = MAX(i4_size, 1);
724 return (i4_size);
725}
726
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]727/**************************************************************************/
728/* This function initialises the value of ps_dec->u1_recon_mb_grp */
729/* ps_dec->u1_recon_mb_grp must satisfy the following criteria */
730/* - multiple of 2 (required for N/2 parse-mvpred design) */
731/* - multiple of 4 (if it is not a frame_mbs_only sequence), */
732/* in this case N/2 itself needs to be even for mbpair processing */
733/* - lesser than ps_dec->u2_frm_wd_in_mbs/2 (at least 3 N-Chunks */
734/* should make a row to ensure proper MvTop transferring) */
735/**************************************************************************/
736WORD32 ih264d_init_dec_mb_grp(dec_struct_t *ps_dec)
737{
738 dec_seq_params_t *ps_seq = ps_dec->ps_cur_sps;
739 UWORD8 u1_frm = ps_seq->u1_frame_mbs_only_flag;
740
Harish Mahendrakar6676aeb2016-10-14 17:19:53 +0530[diff] [blame]741 ps_dec->u1_recon_mb_grp = ps_dec->u2_frm_wd_in_mbs << ps_seq->u1_mb_aff_flag;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]742
743 ps_dec->u1_recon_mb_grp_pair = ps_dec->u1_recon_mb_grp >> 1;
744
745 if(!ps_dec->u1_recon_mb_grp)
746 {
747 return ERROR_MB_GROUP_ASSGN_T;
748 }
749
750 ps_dec->u4_num_mbs_prev_nmb = ps_dec->u1_recon_mb_grp;
751
752 return OK;
753}
754
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]755
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]756/*!
757 **************************************************************************
758 * \if Function name : ih264d_init_pic \endif
759 *
760 * \brief
761 * Initializes the picture.
762 *
763 * \return
764 * 0 on Success and Error code otherwise
765 *
766 * \note
767 * This function is called when first slice of the
768 * NON -IDR picture is encountered.
769 **************************************************************************
770 */
771WORD32 ih264d_init_pic(dec_struct_t *ps_dec,
772 UWORD16 u2_frame_num,
773 WORD32 i4_poc,
774 dec_pic_params_t *ps_pps)
775{
776 dec_seq_params_t *ps_seq = ps_pps->ps_sps;
777 prev_seq_params_t * ps_prev_seq_params = &ps_dec->s_prev_seq_params;
778 WORD32 i4_pic_bufs;
779 WORD32 ret;
780
781 ps_dec->ps_cur_slice->u2_frame_num = u2_frame_num;
782 ps_dec->ps_cur_slice->i4_poc = i4_poc;
783 ps_dec->ps_cur_pps = ps_pps;
784 ps_dec->ps_cur_pps->pv_codec_handle = ps_dec;
785
786 ps_dec->ps_cur_sps = ps_seq;
787 ps_dec->ps_dpb_mgr->i4_max_frm_num = ps_seq->u2_u4_max_pic_num_minus1
788 + 1;
789
790 ps_dec->ps_dpb_mgr->u2_pic_ht = ps_dec->u2_pic_ht;
791 ps_dec->ps_dpb_mgr->u2_pic_wd = ps_dec->u2_pic_wd;
Isha Kulkarni34769a52019-01-28 17:43:35 +0530[diff] [blame]792 ps_dec->i4_pic_type = NA_SLICE;
793 ps_dec->i4_frametype = IV_NA_FRAME;
794 ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]795
796 /*--------------------------------------------------------------------*/
797 /* Get the value of MaxMbAddress and frmheight in Mbs */
798 /*--------------------------------------------------------------------*/
799 ps_seq->u2_max_mb_addr =
800 (ps_seq->u2_frm_wd_in_mbs
801 * (ps_dec->u2_pic_ht
802 >> (4
803 + ps_dec->ps_cur_slice->u1_field_pic_flag)))
804 - 1;
805 ps_dec->u2_frm_ht_in_mbs = (ps_dec->u2_pic_ht
806 >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag));
807
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]808 /***************************************************************************/
809 /* If change in Level or the required PicBuffers i4_size is more than the */
810 /* current one FREE the current PicBuffers and allocate affresh */
811 /***************************************************************************/
Hamsalekha Sf15bb322017-06-22 17:08:44 +0530[diff] [blame]812 if(!ps_dec->u1_init_dec_flag)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]813 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]814 ps_dec->u1_max_dec_frame_buffering = ih264d_get_dpb_size(ps_seq);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]815
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]816 ps_dec->i4_display_delay = ps_dec->u1_max_dec_frame_buffering;
817 if((1 == ps_seq->u1_vui_parameters_present_flag) &&
818 (1 == ps_seq->s_vui.u1_bitstream_restriction_flag))
819 {
820 if(ps_seq->u1_frame_mbs_only_flag == 1)
821 ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames + 1;
822 else
823 ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames * 2 + 2;
824 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]825
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]826 if(IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode)
827 ps_dec->i4_display_delay = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]828
829 if(ps_dec->u4_share_disp_buf == 0)
830 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]831 if(ps_seq->u1_frame_mbs_only_flag == 1)
832 ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + ps_seq->u1_num_ref_frames + 1;
833 else
834 ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + ps_seq->u1_num_ref_frames * 2 + 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]835 }
836 else
837 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]838 ps_dec->u1_pic_bufs = (WORD32)ps_dec->u4_num_disp_bufs;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]839 }
840
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]841 /* Ensure at least two buffers are allocated */
842 ps_dec->u1_pic_bufs = MAX(ps_dec->u1_pic_bufs, 2);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]843
844 if(ps_dec->u4_share_disp_buf == 0)
845 ps_dec->u1_pic_bufs = MIN(ps_dec->u1_pic_bufs,
846 (H264_MAX_REF_PICS * 2));
847
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]848 ps_dec->u1_max_dec_frame_buffering = MIN(
849 ps_dec->u1_max_dec_frame_buffering,
850 ps_dec->u1_pic_bufs);
851
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]852 /* Temporary hack to run Tractor Cav/Cab/MbAff Profiler streams also for CAFI1_SVA_C.264 in conformance*/
853 if(ps_dec->u1_init_dec_flag)
854 {
855 ih264d_release_pics_in_dpb((void *)ps_dec,
856 ps_dec->u1_pic_bufs);
857 ih264d_release_display_bufs(ps_dec);
858 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr);
859 }
860
861 /*********************************************************************/
862 /* Configuring decoder parameters based on level and then */
863 /* fresh pointer initialisation in decoder scratch and state buffers */
864 /*********************************************************************/
865 if(!ps_dec->u1_init_dec_flag ||
866 ((ps_seq->u1_level_idc < H264_LEVEL_3_0) ^ (ps_prev_seq_params->u1_level_idc < H264_LEVEL_3_0)))
867 {
868 ret = ih264d_init_dec_mb_grp(ps_dec);
869 if(ret != OK)
870 return ret;
871 }
872
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]873 ret = ih264d_allocate_dynamic_bufs(ps_dec);
874 if(ret != OK)
875 {
876 /* Free any dynamic buffers that are allocated */
877 ih264d_free_dynamic_bufs(ps_dec);
878 ps_dec->i4_error_code = IVD_MEM_ALLOC_FAILED;
879 return IVD_MEM_ALLOC_FAILED;
880 }
881
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]882 ret = ih264d_create_pic_buffers(ps_dec->u1_pic_bufs,
883 ps_dec);
884 if(ret != OK)
885 return ret;
886
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]887
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]888
889 ret = ih264d_create_mv_bank(ps_dec, ps_dec->u2_pic_wd,
890 ps_dec->u2_pic_ht);
891 if(ret != OK)
892 return ret;
893
894 /* In shared mode, set all of them as used by display */
895 if(ps_dec->u4_share_disp_buf == 1)
896 {
897 WORD32 i;
898
899 for(i = 0; i < ps_dec->u1_pic_bufs; i++)
900 {
901 ih264_buf_mgr_set_status((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i,
902 BUF_MGR_IO);
903 }
904 }
905
906 ps_dec->u1_init_dec_flag = 1;
907 ps_prev_seq_params->u2_frm_wd_in_mbs = ps_seq->u2_frm_wd_in_mbs;
908 ps_prev_seq_params->u1_level_idc = ps_seq->u1_level_idc;
909 ps_prev_seq_params->u1_profile_idc = ps_seq->u1_profile_idc;
910 ps_prev_seq_params->u2_frm_ht_in_mbs = ps_seq->u2_frm_ht_in_mbs;
911 ps_prev_seq_params->u1_frame_mbs_only_flag =
912 ps_seq->u1_frame_mbs_only_flag;
913 ps_prev_seq_params->u1_direct_8x8_inference_flag =
914 ps_seq->u1_direct_8x8_inference_flag;
915
916 ps_dec->i4_cur_display_seq = 0;
917 ps_dec->i4_prev_max_display_seq = 0;
918 ps_dec->i4_max_poc = 0;
919
920 {
921 /* 0th entry of CtxtIncMbMap will be always be containing default values
922 for CABAC context representing MB not available */
923 ctxt_inc_mb_info_t *p_DefCtxt = ps_dec->p_ctxt_inc_mb_map - 1;
924 UWORD8 *pu1_temp;
925 WORD8 i;
926 p_DefCtxt->u1_mb_type = CAB_SKIP;
927
928 p_DefCtxt->u1_cbp = 0x0f;
929 p_DefCtxt->u1_intra_chroma_pred_mode = 0;
930
931 p_DefCtxt->u1_yuv_dc_csbp = 0x7;
932
933 p_DefCtxt->u1_transform8x8_ctxt = 0;
934
935 pu1_temp = (UWORD8*)p_DefCtxt->i1_ref_idx;
936 for(i = 0; i < 4; i++, pu1_temp++)
937 (*pu1_temp) = 0;
938 pu1_temp = (UWORD8*)p_DefCtxt->u1_mv;
939 for(i = 0; i < 16; i++, pu1_temp++)
940 (*pu1_temp) = 0;
941 ps_dec->ps_def_ctxt_mb_info = p_DefCtxt;
942 }
943
944 }
945 /* reset DBP commands read u4_flag */
946 ps_dec->ps_dpb_cmds->u1_dpb_commands_read = 0;
947
948 return OK;
949}
950
951/*****************************************************************************/
952/* */
953/* Function Name : ih264d_get_next_display_field */
954/* */
955/* Description : Application calls this module to get the next field */
956/* to be displayed */
957/* */
958/* Inputs : 1. IBUFAPI_Handle Hnadle to the Display buffer */
959/* 2. IH264DEC_DispUnit Pointer to the display struct */
960/* */
961/* Globals : */
962/* */
963/* */
964/* Processing : None */
965/* Outputs : None */
966/* Returns : None */
967/* Issues : None */
968/* */
969/* Revision History: */
970/* */
971/* DD MM YYYY Author(s) Changes (Describe the changes made) */
972/* 27 05 2005 Ittiam Draft */
973/* */
974/*****************************************************************************/
975
976WORD32 ih264d_get_next_display_field(dec_struct_t * ps_dec,
977 ivd_out_bufdesc_t *ps_out_buffer,
978 ivd_get_display_frame_op_t *pv_disp_op)
979{
980 pic_buffer_t *pic_buf;
981
982 UWORD8 i1_cur_fld;
983 WORD32 u4_api_ret = -1;
984 WORD32 i4_disp_buf_id;
985 iv_yuv_buf_t *ps_op_frm;
986
987
988
989 ps_op_frm = &(ps_dec->s_disp_frame_info);
990 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex);
991 pic_buf = (pic_buffer_t *)ih264_disp_mgr_get(
992 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, &i4_disp_buf_id);
993 ps_dec->u4_num_fld_in_frm = 0;
994 u4_api_ret = -1;
Isha Kulkarni34769a52019-01-28 17:43:35 +0530[diff] [blame]995 pv_disp_op->u4_ts = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]996 pv_disp_op->e_output_format = ps_dec->u1_chroma_format;
997
998 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_out_buffer->pu1_bufs[0];
999 pv_disp_op->s_disp_frm_buf.pv_u_buf = ps_out_buffer->pu1_bufs[1];
1000 pv_disp_op->s_disp_frm_buf.pv_v_buf = ps_out_buffer->pu1_bufs[2];
Rakesh Kumarfe5a6ad2019-03-07 12:30:09 +0530[diff] [blame]1001 ps_dec->i4_display_index = DEFAULT_POC;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1002 if(pic_buf != NULL)
1003 {
Chamarthi Kishoread2eaf82019-10-01 11:59:43 +0530[diff] [blame]1004 ps_dec->pv_disp_sei_params = &pic_buf->s_sei_pic;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1005 pv_disp_op->e4_fld_type = 0;
1006 pv_disp_op->u4_disp_buf_id = i4_disp_buf_id;
1007
1008 ps_op_frm->u4_y_ht = pic_buf->u2_disp_height << 1;
1009 ps_op_frm->u4_u_ht = ps_op_frm->u4_v_ht = ps_op_frm->u4_y_ht >> 1;
1010 ps_op_frm->u4_y_wd = pic_buf->u2_disp_width;
1011
1012 ps_op_frm->u4_u_wd = ps_op_frm->u4_v_wd = ps_op_frm->u4_y_wd >> 1;
1013
1014 ps_op_frm->u4_y_strd = pic_buf->u2_frm_wd_y;
1015 ps_op_frm->u4_u_strd = ps_op_frm->u4_v_strd = pic_buf->u2_frm_wd_uv;
1016
1017 /* ! */
1018 pv_disp_op->u4_ts = pic_buf->u4_ts;
Rakesh Kumarfe5a6ad2019-03-07 12:30:09 +0530[diff] [blame]1019 ps_dec->i4_display_index = pic_buf->i4_poc;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1020
1021 /* set the start of the Y, U and V buffer pointer for display */
1022 ps_op_frm->pv_y_buf = pic_buf->pu1_buf1 + pic_buf->u2_crop_offset_y;
1023 ps_op_frm->pv_u_buf = pic_buf->pu1_buf2 + pic_buf->u2_crop_offset_uv;
1024 ps_op_frm->pv_v_buf = pic_buf->pu1_buf3 + pic_buf->u2_crop_offset_uv;
1025 ps_dec->u4_num_fld_in_frm++;
1026 ps_dec->u4_num_fld_in_frm++;
1027 u4_api_ret = 0;
1028
1029 if(pic_buf->u1_picturetype == 0)
1030 pv_disp_op->u4_progressive_frame_flag = 1;
1031 else
1032 pv_disp_op->u4_progressive_frame_flag = 0;
1033
1034 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex);
1035 pv_disp_op->u4_error_code = u4_api_ret;
1036 pv_disp_op->e_pic_type = 0xFFFFFFFF; //Junk;
1037
1038 if(u4_api_ret)
1039 {
1040 pv_disp_op->u4_error_code = 1; //put a proper error code here
1041 }
1042 else
1043 {
1044
1045 //Release the buffer if being sent for display
1046 UWORD32 temp;
1047 UWORD32 dest_inc_Y = 0, dest_inc_UV = 0;
1048
1049 pv_disp_op->s_disp_frm_buf.u4_y_wd = temp = MIN(ps_op_frm->u4_y_wd,
1050 ps_op_frm->u4_y_strd);
1051 pv_disp_op->s_disp_frm_buf.u4_u_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd
1052 >> 1;
1053 pv_disp_op->s_disp_frm_buf.u4_v_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd
1054 >> 1;
1055
1056 pv_disp_op->s_disp_frm_buf.u4_y_ht = ps_op_frm->u4_y_ht;
1057 pv_disp_op->s_disp_frm_buf.u4_u_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht
1058 >> 1;
1059 pv_disp_op->s_disp_frm_buf.u4_v_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht
1060 >> 1;
1061 if(0 == ps_dec->u4_share_disp_buf)
1062 {
1063 pv_disp_op->s_disp_frm_buf.u4_y_strd =
1064 pv_disp_op->s_disp_frm_buf.u4_y_wd;
1065 pv_disp_op->s_disp_frm_buf.u4_u_strd =
1066 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1;
1067 pv_disp_op->s_disp_frm_buf.u4_v_strd =
1068 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1;
1069
1070 }
1071 else
1072 {
1073 pv_disp_op->s_disp_frm_buf.u4_y_strd = ps_op_frm->u4_y_strd;
1074 }
1075
1076 if(ps_dec->u4_app_disp_width)
1077 {
1078 pv_disp_op->s_disp_frm_buf.u4_y_strd = MAX(
1079 ps_dec->u4_app_disp_width,
1080 pv_disp_op->s_disp_frm_buf.u4_y_strd);
1081 }
1082
1083 pv_disp_op->u4_error_code = 0;
1084 if(pv_disp_op->e_output_format == IV_YUV_420P)
1085 {
1086 UWORD32 i;
1087 pv_disp_op->s_disp_frm_buf.u4_u_strd =
1088 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1;
1089 pv_disp_op->s_disp_frm_buf.u4_v_strd =
1090 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1;
1091
1092 pv_disp_op->s_disp_frm_buf.u4_u_wd = ps_op_frm->u4_y_wd >> 1;
1093 pv_disp_op->s_disp_frm_buf.u4_v_wd = ps_op_frm->u4_y_wd >> 1;
1094
1095 if(1 == ps_dec->u4_share_disp_buf)
1096 {
1097 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf;
1098
1099 for(i = 0; i < MAX_DISP_BUFS_NEW; i++)
1100 {
1101 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0];
1102 buf += ps_dec->disp_bufs[i].u4_ofst[0];
1103 if(((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf
1104 - pic_buf->u2_crop_offset_y) == buf)
1105 {
1106 buf = ps_dec->disp_bufs[i].buf[1];
1107 buf += ps_dec->disp_bufs[i].u4_ofst[1];
1108 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf
Ritu Baldwac3b026a2017-12-27 17:45:30 +0530[diff] [blame]1109 + (pic_buf->u2_crop_offset_uv
1110 / YUV420SP_FACTOR);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1111
1112 buf = ps_dec->disp_bufs[i].buf[2];
1113 buf += ps_dec->disp_bufs[i].u4_ofst[2];
1114 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf
Ritu Baldwac3b026a2017-12-27 17:45:30 +0530[diff] [blame]1115 + (pic_buf->u2_crop_offset_uv
1116 / YUV420SP_FACTOR);
1117
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1118 }
1119 }
1120 }
1121
1122 }
1123 else if((pv_disp_op->e_output_format == IV_YUV_420SP_UV)
1124 || (pv_disp_op->e_output_format == IV_YUV_420SP_VU))
1125 {
1126 pv_disp_op->s_disp_frm_buf.u4_u_strd =
1127 pv_disp_op->s_disp_frm_buf.u4_y_strd;
1128 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0;
1129
1130 if(1 == ps_dec->u4_share_disp_buf)
1131 {
1132 UWORD32 i;
1133
1134 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf;
1135
1136 for(i = 0; i < MAX_DISP_BUFS_NEW; i++)
1137 {
1138 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0];
1139 buf += ps_dec->disp_bufs[i].u4_ofst[0];
1140 if((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf
1141 - pic_buf->u2_crop_offset_y == buf)
1142 {
1143 buf = ps_dec->disp_bufs[i].buf[1];
1144 buf += ps_dec->disp_bufs[i].u4_ofst[1];
1145 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf
1146 + pic_buf->u2_crop_offset_uv;
1147 ;
1148
1149 buf = ps_dec->disp_bufs[i].buf[2];
1150 buf += ps_dec->disp_bufs[i].u4_ofst[2];
1151 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf
1152 + pic_buf->u2_crop_offset_uv;
1153 ;
1154 }
1155 }
1156 }
1157 pv_disp_op->s_disp_frm_buf.u4_u_wd =
1158 pv_disp_op->s_disp_frm_buf.u4_y_wd;
1159 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0;
1160
1161 }
1162 else if((pv_disp_op->e_output_format == IV_RGB_565)
1163 || (pv_disp_op->e_output_format == IV_YUV_422ILE))
1164 {
1165
1166 pv_disp_op->s_disp_frm_buf.u4_u_strd = 0;
1167 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0;
1168 pv_disp_op->s_disp_frm_buf.u4_u_wd = 0;
1169 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0;
1170 pv_disp_op->s_disp_frm_buf.u4_u_ht = 0;
1171 pv_disp_op->s_disp_frm_buf.u4_v_ht = 0;
1172
1173 }
1174
1175
1176 }
1177
1178 return u4_api_ret;
1179}
1180
1181
1182/*****************************************************************************/
1183/* Function Name : ih264d_release_display_field */
1184/* */
1185/* Description : This function releases the display field that was returned */
1186/* here. */
1187/* Inputs : ps_dec - Decoder parameters */
1188/* Globals : None */
1189/* Processing : Refer bumping process in the standard */
1190/* Outputs : Assigns display sequence number. */
1191/* Returns : None */
1192/* */
1193/* Issues : None */
1194/* */
1195/* Revision History: */
1196/* */
1197/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1198/* 27 04 2005 NS Draft */
1199/* */
1200/*****************************************************************************/
1201void ih264d_release_display_field(dec_struct_t *ps_dec,
1202 ivd_get_display_frame_op_t *pv_disp_op)
1203{
1204 if(1 == pv_disp_op->u4_error_code)
1205 {
1206 if(1 == ps_dec->u1_flushfrm)
1207 {
1208 UWORD32 i;
1209
1210 if(1 == ps_dec->u4_share_disp_buf)
1211 {
1212 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex);
1213 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
1214 {
1215 if(1 == ps_dec->u4_disp_buf_mapping[i])
1216 {
1217 ih264_buf_mgr_release(
1218 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i,
1219 BUF_MGR_IO);
1220 ps_dec->u4_disp_buf_mapping[i] = 0;
1221 }
1222 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex);
1223
1224 memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1225 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1226 for(i = 0; i < ps_dec->u1_pic_bufs; i++)
1227 ps_dec->u4_disp_buf_mapping[i] = 1;
1228 }
1229 ps_dec->u1_flushfrm = 0;
1230
1231 }
1232 }
1233 else
1234 {
1235 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex);
1236
1237 if(0 == ps_dec->u4_share_disp_buf)
1238 {
1239 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
1240 pv_disp_op->u4_disp_buf_id,
1241 BUF_MGR_IO);
1242
1243 }
1244 else
1245 {
1246 ps_dec->u4_disp_buf_mapping[pv_disp_op->u4_disp_buf_id] = 1;
1247 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex);
1248
1249 }
1250}
1251/*****************************************************************************/
1252/* Function Name : ih264d_assign_display_seq */
1253/* */
1254/* Description : This function implments bumping process. Every outgoing */
1255/* frame from DPB is assigned a display sequence number */
1256/* which increases monotonically. System looks for this */
1257/* number to display a frame. */
1258/* here. */
1259/* Inputs : ps_dec - Decoder parameters */
1260/* Globals : None */
1261/* Processing : Refer bumping process in the standard */
1262/* Outputs : Assigns display sequence number. */
1263/* Returns : None */
1264/* */
1265/* Issues : None */
1266/* */
1267/* Revision History: */
1268/* */
1269/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1270/* 27 04 2005 NS Draft */
1271/* */
1272/*****************************************************************************/
1273WORD32 ih264d_assign_display_seq(dec_struct_t *ps_dec)
1274{
1275 WORD32 i;
1276 WORD32 i4_min_poc;
1277 WORD32 i4_min_poc_buf_id;
1278 WORD32 i4_min_index;
1279 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1280 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map;
1281
1282 i4_min_poc = 0x7fffffff;
1283 i4_min_poc_buf_id = -1;
1284 i4_min_index = -1;
1285
1286 if(ps_dpb_mgr->i1_poc_buf_id_entries >= ps_dec->i4_display_delay)
1287 {
1288 for(i = 0; i < MAX_FRAMES; i++)
1289 {
1290 if((i4_poc_buf_id_map[i][0] != -1)
1291 && (DO_NOT_DISP
1292 != ps_dpb_mgr->ai4_poc_buf_id_map[i][0]))
1293 {
Harish Mahendrakarffcf2a82019-12-17 15:42:03 -0800[diff] [blame]1294 /* Checking for <= is necessary to handle cases where there is one
1295 valid buffer with poc set to 0x7FFFFFFF. */
1296 if(i4_poc_buf_id_map[i][1] <= i4_min_poc)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1297 {
1298 i4_min_poc = i4_poc_buf_id_map[i][1];
1299 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0];
1300 i4_min_index = i;
1301 }
1302 }
1303 }
1304
1305 if((i4_min_index != -1) && (DO_NOT_DISP != i4_min_poc_buf_id))
1306 {
1307 ps_dec->i4_cur_display_seq++;
1308 ih264_disp_mgr_add(
1309 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr,
1310 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq,
1311 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]);
1312 i4_poc_buf_id_map[i4_min_index][0] = -1;
1313 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff;
1314 ps_dpb_mgr->i1_poc_buf_id_entries--;
1315 }
1316 else if(DO_NOT_DISP == i4_min_poc_buf_id)
1317 {
1318 WORD32 i4_error_code;
1319 i4_error_code = ERROR_GAPS_IN_FRM_NUM;
1320// i4_error_code |= 1<<IVD_CORRUPTEDDATA;
1321 return i4_error_code;
1322 }
1323 }
1324 return OK;
1325}
1326
1327/*****************************************************************************/
1328/* */
1329/* Function Name : ih264d_release_display_bufs */
1330/* */
1331/* Description : This function implments bumping process when mmco = 5. */
1332/* Each outgoing frame from DPB is assigned a display */
1333/* sequence number which increases monotonically. System */
1334/* looks for this number to display a frame. */
1335/* Inputs : ps_dec - Decoder parameters */
1336/* Globals : None */
1337/* Processing : Refer bumping process in the standard for mmco = 5 */
1338/* Outputs : Assigns display sequence number. */
1339/* Returns : None */
1340/* */
1341/* Issues : None */
1342/* */
1343/* Revision History: */
1344/* */
1345/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1346/* 27 04 2005 NS Draft */
1347/* */
1348/*****************************************************************************/
1349void ih264d_release_display_bufs(dec_struct_t *ps_dec)
1350{
1351 WORD32 i, j;
1352 WORD32 i4_min_poc;
1353 WORD32 i4_min_poc_buf_id;
1354 WORD32 i4_min_index;
Shivaansh Agrawal358b0932020-07-22 13:11:55 +0530[diff] [blame]1355 WORD64 i8_temp;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1356 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1357 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map;
1358
1359 i4_min_poc = 0x7fffffff;
Harish Mahendrakarffcf2a82019-12-17 15:42:03 -0800[diff] [blame]1360 i4_min_poc_buf_id = 0;
1361 i4_min_index = 0;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1362
1363 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1364
1365 for(j = 0; j < ps_dpb_mgr->i1_poc_buf_id_entries; j++)
1366 {
1367 i4_min_poc = 0x7fffffff;
1368 for(i = 0; i < MAX_FRAMES; i++)
1369 {
1370 if(i4_poc_buf_id_map[i][0] != -1)
1371 {
Harish Mahendrakarffcf2a82019-12-17 15:42:03 -0800[diff] [blame]1372 /* Checking for <= is necessary to handle cases where there is one
1373 valid buffer with poc set to 0x7FFFFFFF. */
1374 if(i4_poc_buf_id_map[i][1] <= i4_min_poc)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1375 {
1376 i4_min_poc = i4_poc_buf_id_map[i][1];
1377 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0];
1378 i4_min_index = i;
1379 }
1380 }
1381 }
1382
1383 if(DO_NOT_DISP != i4_min_poc_buf_id)
1384 {
1385 ps_dec->i4_cur_display_seq++;
1386 ih264_disp_mgr_add(
1387 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr,
1388 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq,
1389 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]);
1390 i4_poc_buf_id_map[i4_min_index][0] = -1;
1391 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff;
1392 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0;
1393 }
1394 else
1395 {
1396 i4_poc_buf_id_map[i4_min_index][0] = -1;
1397 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff;
1398 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0;
1399 }
1400 }
1401 ps_dpb_mgr->i1_poc_buf_id_entries = 0;
Shivaansh Agrawal358b0932020-07-22 13:11:55 +0530[diff] [blame]1402 i8_temp = (WORD64)ps_dec->i4_prev_max_display_seq + ps_dec->i4_max_poc
Ritu Baldwa49afc8f2018-04-10 18:20:17 +0530[diff] [blame]1403 + ps_dec->u1_max_dec_frame_buffering + 1;
1404 /*If i4_prev_max_display_seq overflows integer range, reset it */
Shivaansh Agrawal358b0932020-07-22 13:11:55 +0530[diff] [blame]1405 ps_dec->i4_prev_max_display_seq = IS_OUT_OF_RANGE_S32(i8_temp)?
1406 0 : i8_temp;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1407 ps_dec->i4_max_poc = 0;
1408}
1409
1410/*****************************************************************************/
1411/* */
1412/* Function Name : ih264d_assign_pic_num */
1413/* */
1414/* Description : This function assigns pic num to each reference frame */
1415/* depending on the cur_frame_num as speified in section */
1416/* 8.2.4.1 */
1417/* */
1418/* Inputs : ps_dec */
1419/* */
1420/* Globals : NO globals used */
1421/* */
1422/* Processing : for all ST pictures */
1423/* if( FrameNum > cur_frame_num) */
1424/* PicNum = FrameNum - MaxFrameNum */
1425/* else */
1426/* PicNum = FrameNum */
1427/* */
1428/* Returns : void */
1429/* */
1430/* Issues : NO */
1431/* */
1432/* Revision History: */
1433/* */
1434/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1435/* 13 07 2002 Jay Draft */
1436/* */
1437/*****************************************************************************/
1438
1439void ih264d_assign_pic_num(dec_struct_t *ps_dec)
1440{
1441 dpb_manager_t *ps_dpb_mgr;
1442 struct dpb_info_t *ps_next_dpb;
1443 WORD8 i;
1444 WORD32 i4_cur_frame_num, i4_max_frame_num;
1445 WORD32 i4_ref_frame_num;
1446 UWORD8 u1_fld_pic_flag = ps_dec->ps_cur_slice->u1_field_pic_flag;
1447
1448 i4_max_frame_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1;
1449 i4_cur_frame_num = ps_dec->ps_cur_pic->i4_frame_num;
1450 ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1451
1452 /* Start from ST head */
1453 ps_next_dpb = ps_dpb_mgr->ps_dpb_st_head;
1454 for(i = 0; i < ps_dpb_mgr->u1_num_st_ref_bufs; i++)
1455 {
1456 WORD32 i4_pic_num;
1457
1458 i4_ref_frame_num = ps_next_dpb->ps_pic_buf->i4_frame_num;
1459 if(i4_ref_frame_num > i4_cur_frame_num)
1460 {
1461 /* RefPic Buf frame_num is before Current frame_num in decode order */
1462 i4_pic_num = i4_ref_frame_num - i4_max_frame_num;
1463 }
1464 else
1465 {
1466 /* RefPic Buf frame_num is after Current frame_num in decode order */
1467 i4_pic_num = i4_ref_frame_num;
1468 }
1469
1470 ps_next_dpb->ps_pic_buf->i4_pic_num = i4_pic_num;
1471 ps_next_dpb->i4_frame_num = i4_pic_num;
1472 ps_next_dpb->ps_pic_buf->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1473 if(u1_fld_pic_flag)
1474 {
1475 /* Assign the pic num to top fields and bot fields */
1476
1477 ps_next_dpb->s_top_field.i4_pic_num = i4_pic_num * 2
1478 + !(ps_dec->ps_cur_slice->u1_bottom_field_flag);
1479 ps_next_dpb->s_bot_field.i4_pic_num = i4_pic_num * 2
1480 + ps_dec->ps_cur_slice->u1_bottom_field_flag;
1481 }
1482 /* Chase the next link */
1483 ps_next_dpb = ps_next_dpb->ps_prev_short;
1484 }
1485
1486 if(ps_dec->ps_cur_sps->u1_gaps_in_frame_num_value_allowed_flag
1487 && ps_dpb_mgr->u1_num_gaps)
1488 {
1489 WORD32 i4_start_frm, i4_end_frm;
1490 /* Assign pic numbers for gaps */
1491 for(i = 0; i < MAX_FRAMES; i++)
1492 {
1493 i4_start_frm = ps_dpb_mgr->ai4_gaps_start_frm_num[i];
1494 if(i4_start_frm != INVALID_FRAME_NUM)
1495 {
1496 if(i4_start_frm > i4_cur_frame_num)
1497 {
1498 /* gap's frame_num is before Current frame_num in
1499 decode order */
1500 i4_start_frm -= i4_max_frame_num;
1501 }
1502 ps_dpb_mgr->ai4_gaps_start_frm_num[i] = i4_start_frm;
1503 i4_end_frm = ps_dpb_mgr->ai4_gaps_end_frm_num[i];
1504
1505 if(i4_end_frm > i4_cur_frame_num)
1506 {
1507 /* gap's frame_num is before Current frame_num in
1508 decode order */
1509 i4_end_frm -= i4_max_frame_num;
1510 }
1511 ps_dpb_mgr->ai4_gaps_end_frm_num[i] = i4_end_frm;
1512 }
1513 }
1514 }
1515}
1516
1517/*!
1518 **************************************************************************
1519 * \if Function name : ih264d_update_qp \endif
1520 *
1521 * \brief
1522 * Updates the values of QP and its related entities
1523 *
1524 * \return
1525 * 0 on Success and Error code otherwise
1526 *
1527 **************************************************************************
1528 */
1529WORD32 ih264d_update_qp(dec_struct_t * ps_dec, const WORD8 i1_qp)
1530{
1531 WORD32 i_temp;
1532 i_temp = (ps_dec->u1_qp + i1_qp + 52) % 52;
1533
1534 if((i_temp < 0) || (i_temp > 51) || (i1_qp < -26) || (i1_qp > 25))
1535 return ERROR_INV_RANGE_QP_T;
1536
1537 ps_dec->u1_qp = i_temp;
1538 ps_dec->u1_qp_y_rem6 = ps_dec->u1_qp % 6;
1539 ps_dec->u1_qp_y_div6 = ps_dec->u1_qp / 6;
1540 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_chroma_qp_index_offset);
1541 ps_dec->u1_qp_u_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1542 ps_dec->u1_qp_u_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1543
1544 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_second_chroma_qp_index_offset);
1545 ps_dec->u1_qp_v_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1546 ps_dec->u1_qp_v_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1547
1548 ps_dec->pu2_quant_scale_y =
1549 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_y_rem6];
1550 ps_dec->pu2_quant_scale_u =
1551 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_u_rem6];
1552 ps_dec->pu2_quant_scale_v =
1553 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_v_rem6];
1554 return OK;
1555}
1556
1557/*****************************************************************************/
1558/* */
1559/* Function Name : ih264d_decode_gaps_in_frame_num */
1560/* */
1561/* Description : This function decodes gaps in frame number */
1562/* */
1563/* Inputs : ps_dec Decoder parameters */
1564/* u2_frame_num current frame number */
1565/* */
1566/* Globals : None */
1567/* Processing : This functionality needs to be implemented */
1568/* Outputs : None */
1569/* Returns : None */
1570/* */
1571/* Issues : Not implemented */
1572/* */
1573/* Revision History: */
1574/* */
1575/* DD MM YYYY Author(s) Changes (Describe the changes made) */
1576/* 06 05 2002 NS Draft */
1577/* */
1578/*****************************************************************************/
1579WORD32 ih264d_decode_gaps_in_frame_num(dec_struct_t *ps_dec,
1580 UWORD16 u2_frame_num)
1581{
1582 UWORD32 u4_next_frm_num, u4_start_frm_num;
1583 UWORD32 u4_max_frm_num;
1584 pocstruct_t s_tmp_poc;
1585 WORD32 i4_poc;
1586 dec_slice_params_t *ps_cur_slice;
1587
1588 dec_pic_params_t *ps_pic_params;
1589 WORD8 i1_gap_idx;
1590 WORD32 *i4_gaps_start_frm_num;
1591 dpb_manager_t *ps_dpb_mgr;
1592 WORD32 i4_frame_gaps;
1593 WORD8 *pi1_gaps_per_seq;
1594 WORD32 ret;
1595
1596 ps_cur_slice = ps_dec->ps_cur_slice;
1597 if(ps_cur_slice->u1_field_pic_flag)
1598 {
1599 if(ps_dec->u2_prev_ref_frame_num == u2_frame_num)
1600 return 0;
1601 }
1602
1603 u4_next_frm_num = ps_dec->u2_prev_ref_frame_num + 1;
1604 u4_max_frm_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1;
1605
1606 // check
1607 if(u4_next_frm_num >= u4_max_frm_num)
1608 {
1609 u4_next_frm_num -= u4_max_frm_num;
1610 }
1611
1612 if(u4_next_frm_num == u2_frame_num)
1613 {
1614 return (0);
1615 }
1616
1617 // check
1618 if((ps_dec->u1_nal_unit_type == IDR_SLICE_NAL)
1619 && (u4_next_frm_num >= u2_frame_num))
1620 {
1621 return (0);
1622 }
1623 u4_start_frm_num = u4_next_frm_num;
1624
1625 s_tmp_poc.i4_pic_order_cnt_lsb = 0;
1626 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0;
1627 s_tmp_poc.i4_pic_order_cnt_lsb = 0;
1628 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0;
1629 s_tmp_poc.i4_delta_pic_order_cnt[0] = 0;
1630 s_tmp_poc.i4_delta_pic_order_cnt[1] = 0;
1631
1632 ps_cur_slice = ps_dec->ps_cur_slice;
1633 ps_pic_params = ps_dec->ps_cur_pps;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1634
1635 i4_frame_gaps = 0;
1636 ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1637
1638 /* Find a empty slot to store gap seqn info */
1639 i4_gaps_start_frm_num = ps_dpb_mgr->ai4_gaps_start_frm_num;
1640 for(i1_gap_idx = 0; i1_gap_idx < MAX_FRAMES; i1_gap_idx++)
1641 {
1642 if(INVALID_FRAME_NUM == i4_gaps_start_frm_num[i1_gap_idx])
1643 break;
1644 }
1645 if(MAX_FRAMES == i1_gap_idx)
1646 {
1647 UWORD32 i4_error_code;
1648 i4_error_code = ERROR_DBP_MANAGER_T;
1649// i4_error_code |= 1<<IVD_CORRUPTEDDATA;
1650 return i4_error_code;
1651 }
1652
1653 i4_poc = 0;
1654 i4_gaps_start_frm_num[i1_gap_idx] = u4_start_frm_num;
1655 ps_dpb_mgr->ai4_gaps_end_frm_num[i1_gap_idx] = u2_frame_num - 1;
1656 pi1_gaps_per_seq = ps_dpb_mgr->ai1_gaps_per_seq;
1657 pi1_gaps_per_seq[i1_gap_idx] = 0;
1658 while(u4_next_frm_num != u2_frame_num)
1659 {
1660 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1661 if(ps_pic_params->ps_sps->u1_pic_order_cnt_type)
1662 {
1663 /* allocate a picture buffer and insert it as ST node */
1664 ret = ih264d_decode_pic_order_cnt(0, u4_next_frm_num,
1665 &ps_dec->s_prev_pic_poc,
1666 &s_tmp_poc, ps_cur_slice,
1667 ps_pic_params, 1, 0, 0,
1668 &i4_poc);
1669 if(ret != OK)
1670 return ret;
1671
1672 /* Display seq no calculations */
1673 if(i4_poc >= ps_dec->i4_max_poc)
1674 ps_dec->i4_max_poc = i4_poc;
1675 /* IDR Picture or POC wrap around */
1676 if(i4_poc == 0)
1677 {
Shivaansh Agrawal358b0932020-07-22 13:11:55 +0530[diff] [blame]1678 WORD64 i8_temp;
1679 i8_temp = (WORD64)ps_dec->i4_prev_max_display_seq
Ritu Baldwa49afc8f2018-04-10 18:20:17 +0530[diff] [blame]1680 + ps_dec->i4_max_poc
1681 + ps_dec->u1_max_dec_frame_buffering + 1;
1682 /*If i4_prev_max_display_seq overflows integer range, reset it */
Shivaansh Agrawal358b0932020-07-22 13:11:55 +0530[diff] [blame]1683 ps_dec->i4_prev_max_display_seq = IS_OUT_OF_RANGE_S32(i8_temp)?
1684 0 : i8_temp;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1685 ps_dec->i4_max_poc = 0;
1686 }
1687
1688 ps_cur_slice->u1_mmco_equalto5 = 0;
1689 ps_cur_slice->u2_frame_num = u4_next_frm_num;
1690 }
1691
1692 // check
1693 if(ps_dpb_mgr->i1_poc_buf_id_entries
1694 >= ps_dec->u1_max_dec_frame_buffering)
1695 {
1696 ret = ih264d_assign_display_seq(ps_dec);
1697 if(ret != OK)
1698 return ret;
1699 }
1700
Harish Mahendrakar1d672d22019-07-03 10:12:53 -0700[diff] [blame]1701 {
Shivaansh Agrawal358b0932020-07-22 13:11:55 +0530[diff] [blame]1702 WORD64 i8_display_poc;
1703 i8_display_poc = (WORD64)ps_dec->i4_prev_max_display_seq +
Harish Mahendrakar1d672d22019-07-03 10:12:53 -0700[diff] [blame]1704 i4_poc;
1705 if(IS_OUT_OF_RANGE_S32(i8_display_poc))
1706 {
1707 ps_dec->i4_prev_max_display_seq = 0;
1708 }
1709 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1710 ret = ih264d_insert_pic_in_display_list(
1711 ps_dec->ps_dpb_mgr, (WORD8) DO_NOT_DISP,
1712 (WORD32)(ps_dec->i4_prev_max_display_seq + i4_poc),
1713 u4_next_frm_num);
1714 if(ret != OK)
1715 return ret;
1716
1717 pi1_gaps_per_seq[i1_gap_idx]++;
1718 ret = ih264d_do_mmco_for_gaps(ps_dpb_mgr,
1719 ps_dec->ps_cur_sps->u1_num_ref_frames);
1720 if(ret != OK)
1721 return ret;
1722
1723 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1724
1725 u4_next_frm_num++;
1726 if(u4_next_frm_num >= u4_max_frm_num)
1727 {
1728 u4_next_frm_num -= u4_max_frm_num;
1729 }
1730
1731 i4_frame_gaps++;
1732 }
1733
1734 return OK;
1735}
1736
1737/*!
1738 **************************************************************************
1739 * \if Function name : ih264d_create_pic_buffers \endif
1740 *
1741 * \brief
1742 * This function creates Picture Buffers.
1743 *
1744 * \return
1745 * 0 on Success and -1 on error
1746 **************************************************************************
1747 */
1748WORD32 ih264d_create_pic_buffers(UWORD8 u1_num_of_buf,
1749 dec_struct_t *ps_dec)
1750{
1751 struct pic_buffer_t *ps_pic_buf;
1752 UWORD8 i;
1753 UWORD32 u4_luma_size, u4_chroma_size;
1754 UWORD8 u1_frm = ps_dec->ps_cur_sps->u1_frame_mbs_only_flag;
1755 WORD32 j;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1756 UWORD8 *pu1_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1757
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1758 ps_pic_buf = ps_dec->ps_pic_buf_base;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1759 ih264_disp_mgr_init((disp_mgr_t *)ps_dec->pv_disp_buf_mgr);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1760 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_pic_buf_mgr);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1761 u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y;
1762 u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv;
1763
1764 {
1765 if(ps_dec->u4_share_disp_buf == 1)
1766 {
1767 /* In case of buffers getting shared between application and library
1768 there is no need of reference memtabs. Instead of setting the i4_size
1769 to zero, it is reduced to a small i4_size to ensure that changes
1770 in the code are minimal */
1771 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
1772 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)
1773 || (ps_dec->u1_chroma_format == IV_YUV_420P))
1774 {
1775 u4_luma_size = 64;
1776 }
1777
1778 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1779 {
1780 u4_chroma_size = 64;
1781 }
1782
1783 }
1784 }
1785
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1786 pu1_buf = ps_dec->pu1_pic_buf_base;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1787
1788 /* Allocate memory for refernce buffers */
1789 for(i = 0; i < u1_num_of_buf; i++)
1790 {
1791 UWORD32 u4_offset;
1792 WORD32 buf_ret;
1793 UWORD8 *pu1_luma, *pu1_chroma;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1794 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1795
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1796 pu1_luma = pu1_buf;
1797 pu1_buf += ALIGN64(u4_luma_size);
1798 pu1_chroma = pu1_buf;
1799 pu1_buf += ALIGN64(u4_chroma_size);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1800
1801 /* Offset to the start of the pic from the top left corner of the frame
1802 buffer */
1803
1804 if((0 == ps_dec->u4_share_disp_buf)
1805 || (NULL == ps_dec->disp_bufs[i].buf[0]))
1806 {
1807 UWORD32 pad_len_h, pad_len_v;
1808
1809 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H;
1810 ps_pic_buf->pu1_buf1 = (UWORD8 *)(pu1_luma) + u4_offset;
1811
1812 pad_len_h = MAX(PAD_LEN_UV_H, (PAD_LEN_Y_H >> 1));
1813 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V);
1814
1815 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h;
1816
1817 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset;
1818 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset;
1819
1820 }
1821 else
1822 {
1823 UWORD32 pad_len_h, pad_len_v;
1824 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H;
1825 ps_pic_buf->pu1_buf1 = (UWORD8 *)ps_dec->disp_bufs[i].buf[0]
1826 + u4_offset;
1827
1828 ps_dec->disp_bufs[i].u4_ofst[0] = u4_offset;
1829
1830 if(ps_dec->u1_chroma_format == IV_YUV_420P)
1831 {
1832 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR,
1833 (PAD_LEN_Y_H >> 1));
1834 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V);
1835
1836 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h;
1837 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset;
1838 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset;
1839
1840 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset;
1841 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset;
1842
1843 }
1844 else
1845 {
1846 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR,
1847 (PAD_LEN_Y_H >> 1));
1848 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V);
1849
1850 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h;
1851 ps_pic_buf->pu1_buf2 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1])
1852 + u4_offset;
1853 ps_pic_buf->pu1_buf3 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1])
1854 + u4_offset;
1855
1856 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset;
1857 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1858 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1859 }
1860
1861 ps_pic_buf->u2_frm_ht_y = ps_dec->u2_frm_ht_y;
1862 ps_pic_buf->u2_frm_ht_uv = ps_dec->u2_frm_ht_uv;
1863 ps_pic_buf->u2_frm_wd_y = ps_dec->u2_frm_wd_y;
1864 ps_pic_buf->u2_frm_wd_uv = ps_dec->u2_frm_wd_uv;
1865
1866 ps_pic_buf->u1_pic_buf_id = i;
1867
1868 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
1869 ps_pic_buf, i);
1870 if(0 != buf_ret)
1871 {
1872 ps_dec->i4_error_code = ERROR_BUF_MGR;
1873 return ERROR_BUF_MGR;
1874 }
1875
1876 ps_dec->apv_buf_id_pic_buf_map[i] = (void *)ps_pic_buf;
1877 ps_pic_buf++;
1878 }
1879
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1880 if(1 == ps_dec->u4_share_disp_buf)
1881 {
1882 for(i = 0; i < u1_num_of_buf; i++)
1883 ps_dec->u4_disp_buf_mapping[i] = 1;
1884 }
1885 return OK;
1886}
1887
1888/*!
1889 **************************************************************************
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1890 * \if Function name : ih264d_allocate_dynamic_bufs \endif
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1891 *
1892 * \brief
1893 * This function allocates memory required by Decoder.
1894 *
1895 * \param ps_dec: Pointer to dec_struct_t.
1896 *
1897 * \return
1898 * Returns i4_status as returned by MemManager.
1899 *
1900 **************************************************************************
1901 */
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1902WORD16 ih264d_allocate_dynamic_bufs(dec_struct_t * ps_dec)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1903{
1904 struct MemReq s_MemReq;
1905 struct MemBlock *p_MemBlock;
1906
1907 pred_info_t *ps_pred_frame;
1908 dec_mb_info_t *ps_frm_mb_info;
1909 dec_slice_struct_t *ps_dec_slice_buf;
1910 UWORD8 *pu1_dec_mb_map, *pu1_recon_mb_map;
1911 UWORD16 *pu2_slice_num_map;
1912
1913 WORD16 *pi16_res_coeff;
1914 WORD16 i16_status = 0;
1915 UWORD8 uc_frmOrFld = (1 - ps_dec->ps_cur_sps->u1_frame_mbs_only_flag);
1916 UWORD16 u4_luma_wd = ps_dec->u2_frm_wd_y;
1917 UWORD16 u4_chroma_wd = ps_dec->u2_frm_wd_uv;
1918 WORD8 c_i = 0;
1919 dec_seq_params_t *ps_sps = ps_dec->ps_cur_sps;
1920 UWORD32 u4_total_mbs = ps_sps->u2_total_num_of_mbs << uc_frmOrFld;
1921 UWORD32 u4_wd_mbs = ps_dec->u2_frm_wd_in_mbs;
1922 UWORD32 u4_ht_mbs = ps_dec->u2_frm_ht_in_mbs;
1923 UWORD32 u4_blk_wd;
1924 UWORD32 ui_size = 0;
1925 UWORD32 u4_int_scratch_size = 0, u4_ref_pred_size = 0;
1926 UWORD8 *pu1_buf;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1927 WORD32 num_entries;
1928 WORD32 size;
1929 void *pv_buf;
1930 UWORD32 u4_num_bufs;
1931 UWORD32 u4_luma_size, u4_chroma_size;
1932 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1933
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1934 size = u4_total_mbs;
1935 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1936 RETURN_IF((NULL == pv_buf), IV_FAIL);
Rakesh Kumar590ff562018-08-08 12:30:55 +0530[diff] [blame]1937 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1938 ps_dec->pu1_dec_mb_map = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1939
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1940 size = u4_total_mbs;
1941 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1942 RETURN_IF((NULL == pv_buf), IV_FAIL);
Rakesh Kumar590ff562018-08-08 12:30:55 +0530[diff] [blame]1943 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1944 ps_dec->pu1_recon_mb_map = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1945
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1946 size = u4_total_mbs * sizeof(UWORD16);
1947 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1948 RETURN_IF((NULL == pv_buf), IV_FAIL);
Rakesh Kumar590ff562018-08-08 12:30:55 +0530[diff] [blame]1949 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1950 ps_dec->pu2_slice_num_map = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1951
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1952 /************************************************************/
1953 /* Post allocation Initialisations */
1954 /************************************************************/
1955 ps_dec->ps_parse_cur_slice = &(ps_dec->ps_dec_slice_buf[0]);
1956 ps_dec->ps_decode_cur_slice = &(ps_dec->ps_dec_slice_buf[0]);
1957 ps_dec->ps_computebs_cur_slice = &(ps_dec->ps_dec_slice_buf[0]);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]1958
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1959 ps_dec->ps_pred_start = ps_dec->ps_pred;
1960
1961 size = sizeof(parse_pmbarams_t) * (ps_dec->u1_recon_mb_grp);
1962 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1963 RETURN_IF((NULL == pv_buf), IV_FAIL);
Hamsalekha S2575ae62017-04-05 11:11:39 +0530[diff] [blame]1964 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1965 ps_dec->ps_parse_mb_data = pv_buf;
1966
1967 size = sizeof(parse_part_params_t)
1968 * ((ps_dec->u1_recon_mb_grp) << 4);
1969 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1970 RETURN_IF((NULL == pv_buf), IV_FAIL);
Rakesh Kumar590ff562018-08-08 12:30:55 +0530[diff] [blame]1971 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1972 ps_dec->ps_parse_part_params = pv_buf;
1973
1974 size = ((u4_wd_mbs * sizeof(deblkmb_neighbour_t)) << uc_frmOrFld);
1975 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1976 RETURN_IF((NULL == pv_buf), IV_FAIL);
Rakesh Kumar590ff562018-08-08 12:30:55 +0530[diff] [blame]1977 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1978 ps_dec->ps_deblk_top_mb = pv_buf;
1979
1980 size = ((sizeof(ctxt_inc_mb_info_t))
1981 * (((u4_wd_mbs + 1) << uc_frmOrFld) + 1));
1982 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1983 RETURN_IF((NULL == pv_buf), IV_FAIL);
Rakesh Kumar590ff562018-08-08 12:30:55 +0530[diff] [blame]1984 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1985 ps_dec->p_ctxt_inc_mb_map = pv_buf;
1986
Harish Mahendrakarbd67b742016-04-26 16:28:57 +0530[diff] [blame]1987 /* 0th entry of CtxtIncMbMap will be always be containing default values
1988 for CABAC context representing MB not available */
1989 ps_dec->p_ctxt_inc_mb_map += 1;
1990
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1991 size = (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp
1992 * 16);
1993 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1994 RETURN_IF((NULL == pv_buf), IV_FAIL);
Rakesh Kumar590ff562018-08-08 12:30:55 +0530[diff] [blame]1995 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]1996 ps_dec->ps_mv_p[0] = pv_buf;
1997
1998 size = (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp
1999 * 16);
2000 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2001 RETURN_IF((NULL == pv_buf), IV_FAIL);
Rakesh Kumar590ff562018-08-08 12:30:55 +0530[diff] [blame]2002 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2003 ps_dec->ps_mv_p[1] = pv_buf;
2004
2005 {
2006 UWORD8 i;
2007 for(i = 0; i < MV_SCRATCH_BUFS; i++)
2008 {
2009 size = (sizeof(mv_pred_t)
2010 * ps_dec->u1_recon_mb_grp * 4);
2011 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2012 RETURN_IF((NULL == pv_buf), IV_FAIL);
Rakesh Kumar590ff562018-08-08 12:30:55 +0530[diff] [blame]2013 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2014 ps_dec->ps_mv_top_p[i] = pv_buf;
2015 }
2016 }
2017
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]2018 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2019 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2020 RETURN_IF((NULL == pv_buf), IV_FAIL);
2021 ps_dec->pu1_y_intra_pred_line = pv_buf;
2022 memset(ps_dec->pu1_y_intra_pred_line, 0, size);
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]2023 ps_dec->pu1_y_intra_pred_line += MB_SIZE;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2024
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]2025 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2026 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2027 RETURN_IF((NULL == pv_buf), IV_FAIL);
2028 ps_dec->pu1_u_intra_pred_line = pv_buf;
2029 memset(ps_dec->pu1_u_intra_pred_line, 0, size);
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]2030 ps_dec->pu1_u_intra_pred_line += MB_SIZE;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2031
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]2032 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2033 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2034 RETURN_IF((NULL == pv_buf), IV_FAIL);
2035 ps_dec->pu1_v_intra_pred_line = pv_buf;
2036 memset(ps_dec->pu1_v_intra_pred_line, 0, size);
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]2037 ps_dec->pu1_v_intra_pred_line += MB_SIZE;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2038
2039 if(ps_dec->u1_separate_parse)
2040 {
Harish Mahendrakar9b095de2016-12-15 18:04:53 +0530[diff] [blame]2041 /* Needs one extra row of info, to hold top row data */
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2042 size = sizeof(mb_neigbour_params_t)
Harish Mahendrakar9b095de2016-12-15 18:04:53 +0530[diff] [blame]2043 * 2 * ((u4_wd_mbs + 2) * (u4_ht_mbs + 1));
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2044 }
2045 else
2046 {
2047 size = sizeof(mb_neigbour_params_t)
2048 * 2 * ((u4_wd_mbs + 2) << uc_frmOrFld);
2049 }
2050 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2051 RETURN_IF((NULL == pv_buf), IV_FAIL);
2052
2053 ps_dec->ps_nbr_mb_row = pv_buf;
2054 memset(ps_dec->ps_nbr_mb_row, 0, size);
2055
2056 /* Allocate deblock MB info */
2057 size = (u4_total_mbs + u4_wd_mbs) * sizeof(deblk_mb_t);
2058
2059 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2060 RETURN_IF((NULL == pv_buf), IV_FAIL);
2061 ps_dec->ps_deblk_pic = pv_buf;
2062
2063 memset(ps_dec->ps_deblk_pic, 0, size);
2064
2065 /* Allocate frame level mb info */
2066 size = sizeof(dec_mb_info_t) * u4_total_mbs;
2067 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2068 RETURN_IF((NULL == pv_buf), IV_FAIL);
2069 ps_dec->ps_frm_mb_info = pv_buf;
2070 memset(ps_dec->ps_frm_mb_info, 0, size);
2071
2072 /* Allocate memory for slice headers dec_slice_struct_t */
2073 num_entries = MAX_FRAMES;
2074 if((1 >= ps_dec->ps_cur_sps->u1_num_ref_frames) &&
2075 (0 == ps_dec->i4_display_delay))
2076 {
2077 num_entries = 1;
2078 }
2079 num_entries = ((2 * num_entries) + 1);
Hamsalekha Sa925a6b2017-04-21 11:01:52 +0530[diff] [blame]2080 num_entries *= 2;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2081
2082 size = num_entries * sizeof(void *);
2083 size += PAD_MAP_IDX_POC * sizeof(void *);
2084 size *= u4_total_mbs;
2085 size += sizeof(dec_slice_struct_t) * u4_total_mbs;
2086 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2087 RETURN_IF((NULL == pv_buf), IV_FAIL);
2088
2089 ps_dec->ps_dec_slice_buf = pv_buf;
2090 memset(ps_dec->ps_dec_slice_buf, 0, size);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2091 pu1_buf = (UWORD8 *)ps_dec->ps_dec_slice_buf;
2092 pu1_buf += sizeof(dec_slice_struct_t) * u4_total_mbs;
2093 ps_dec->pv_map_ref_idx_to_poc_buf = (void *)pu1_buf;
2094
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2095 /* Allocate memory for packed pred info */
2096 num_entries = u4_total_mbs;
Hamsalekha S9008aed2017-05-08 17:21:56 +0530[diff] [blame]2097 num_entries *= 16 * 2;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2098
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2099 size = sizeof(pred_info_pkd_t) * num_entries;
2100 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2101 RETURN_IF((NULL == pv_buf), IV_FAIL);
Rakesh Kumar590ff562018-08-08 12:30:55 +0530[diff] [blame]2102 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2103 ps_dec->ps_pred_pkd = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2104
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2105 /* Allocate memory for coeff data */
2106 size = MB_LUM_SIZE * sizeof(WORD16);
2107 /*For I16x16 MBs, 16 4x4 AC coeffs and 1 4x4 DC coeff TU blocks will be sent
2108 For all MBs along with 8 4x4 AC coeffs 2 2x2 DC coeff TU blocks will be sent
2109 So use 17 4x4 TU blocks for luma and 9 4x4 TU blocks for chroma */
2110 size += u4_total_mbs * (MAX(17 * sizeof(tu_sblk4x4_coeff_data_t),4 * sizeof(tu_blk8x8_coeff_data_t))
2111 + 9 * sizeof(tu_sblk4x4_coeff_data_t));
2112 //32 bytes for each mb to store u1_prev_intra4x4_pred_mode and u1_rem_intra4x4_pred_mode data
2113 size += u4_total_mbs * 32;
2114 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2115 RETURN_IF((NULL == pv_buf), IV_FAIL);
Rakesh Kumar590ff562018-08-08 12:30:55 +0530[diff] [blame]2116 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2117
2118 ps_dec->pi2_coeff_data = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2119
2120 ps_dec->pv_pic_tu_coeff_data = (void *)(ps_dec->pi2_coeff_data + MB_LUM_SIZE);
2121
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2122 /* Allocate MV bank buffer */
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2123 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2124 UWORD32 col_flag_buffer_size, mvpred_buffer_size;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2125
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2126 col_flag_buffer_size = ((ps_dec->u2_pic_wd * ps_dec->u2_pic_ht) >> 4);
2127 mvpred_buffer_size = sizeof(mv_pred_t)
2128 * ((ps_dec->u2_pic_wd * (ps_dec->u2_pic_ht + PAD_MV_BANK_ROW)) >> 4);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2129
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2130 u4_num_bufs = ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2131
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2132 u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs);
2133 u4_num_bufs = MAX(u4_num_bufs, 2);
2134 size = ALIGN64(mvpred_buffer_size) + ALIGN64(col_flag_buffer_size);
2135 size *= u4_num_bufs;
2136 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2137 RETURN_IF((NULL == pv_buf), IV_FAIL);
Rakesh Kumar590ff562018-08-08 12:30:55 +0530[diff] [blame]2138 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2139 ps_dec->pu1_mv_bank_buf_base = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2140 }
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2141
2142 /* Allocate Pic buffer */
2143 u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y;
2144 u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv;
2145
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2146 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2147 if(ps_dec->u4_share_disp_buf == 1)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2148 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2149 /* In case of buffers getting shared between application and library
2150 there is no need of reference memtabs. Instead of setting the i4_size
2151 to zero, it is reduced to a small i4_size to ensure that changes
2152 in the code are minimal */
2153 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
2154 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)
2155 || (ps_dec->u1_chroma_format == IV_YUV_420P))
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2156 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2157 u4_luma_size = 64;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2158 }
2159
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2160 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2161 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2162 u4_chroma_size = 64;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2163 }
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2164
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2165 }
2166 }
2167
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2168 size = ALIGN64(u4_luma_size) + ALIGN64(u4_chroma_size);
2169 size *= ps_dec->u1_pic_bufs;
2170 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2171 RETURN_IF((NULL == pv_buf), IV_FAIL);
Rakesh Kumar590ff562018-08-08 12:30:55 +0530[diff] [blame]2172 memset(pv_buf, 0, size);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2173 ps_dec->pu1_pic_buf_base = pv_buf;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2174
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2175 /* Post allocation Increment Actions */
2176
2177 /***************************************************************************/
2178 /*Initialize cabac context pointers for every SE that has fixed contextIdx */
2179 /***************************************************************************/
2180 {
2181 bin_ctxt_model_t * const p_cabac_ctxt_table_t =
2182 ps_dec->p_cabac_ctxt_table_t;
2183 bin_ctxt_model_t * * p_coeff_abs_level_minus1_t =
2184 ps_dec->p_coeff_abs_level_minus1_t;
2185 bin_ctxt_model_t * * p_cbf_t = ps_dec->p_cbf_t;
2186
2187 ps_dec->p_mb_field_dec_flag_t = p_cabac_ctxt_table_t
2188 + MB_FIELD_DECODING_FLAG;
2189 ps_dec->p_prev_intra4x4_pred_mode_flag_t = p_cabac_ctxt_table_t
2190 + PREV_INTRA4X4_PRED_MODE_FLAG;
2191 ps_dec->p_rem_intra4x4_pred_mode_t = p_cabac_ctxt_table_t
2192 + REM_INTRA4X4_PRED_MODE;
2193 ps_dec->p_intra_chroma_pred_mode_t = p_cabac_ctxt_table_t
2194 + INTRA_CHROMA_PRED_MODE;
2195 ps_dec->p_mb_qp_delta_t = p_cabac_ctxt_table_t + MB_QP_DELTA;
2196 ps_dec->p_ref_idx_t = p_cabac_ctxt_table_t + REF_IDX;
2197 ps_dec->p_mvd_x_t = p_cabac_ctxt_table_t + MVD_X;
2198 ps_dec->p_mvd_y_t = p_cabac_ctxt_table_t + MVD_Y;
2199 p_cbf_t[0] = p_cabac_ctxt_table_t + CBF + 0;
2200 p_cbf_t[1] = p_cabac_ctxt_table_t + CBF + 4;
2201 p_cbf_t[2] = p_cabac_ctxt_table_t + CBF + 8;
2202 p_cbf_t[3] = p_cabac_ctxt_table_t + CBF + 12;
2203 p_cbf_t[4] = p_cabac_ctxt_table_t + CBF + 16;
2204 ps_dec->p_cbp_luma_t = p_cabac_ctxt_table_t + CBP_LUMA;
2205 ps_dec->p_cbp_chroma_t = p_cabac_ctxt_table_t + CBP_CHROMA;
2206
2207 p_coeff_abs_level_minus1_t[LUMA_DC_CTXCAT] = p_cabac_ctxt_table_t
2208 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_0_OFFSET;
2209
2210 p_coeff_abs_level_minus1_t[LUMA_AC_CTXCAT] = p_cabac_ctxt_table_t
2211 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_1_OFFSET;
2212
2213 p_coeff_abs_level_minus1_t[LUMA_4X4_CTXCAT] = p_cabac_ctxt_table_t
2214 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_2_OFFSET;
2215
2216 p_coeff_abs_level_minus1_t[CHROMA_DC_CTXCAT] = p_cabac_ctxt_table_t
2217 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_3_OFFSET;
2218
2219 p_coeff_abs_level_minus1_t[CHROMA_AC_CTXCAT] = p_cabac_ctxt_table_t
2220 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_4_OFFSET;
2221
2222 p_coeff_abs_level_minus1_t[LUMA_8X8_CTXCAT] = p_cabac_ctxt_table_t
2223 + COEFF_ABS_LEVEL_MINUS1_8X8
2224 + COEFF_ABS_LEVEL_CAT_5_OFFSET;
2225
2226 /********************************************************/
2227 /* context for the high profile related syntax elements */
2228 /* This is maintained seperately in s_high_profile */
2229 /********************************************************/
2230 {
2231
2232 ps_dec->s_high_profile.ps_transform8x8_flag = p_cabac_ctxt_table_t
2233 + TRANSFORM_SIZE_8X8_FLAG;
2234
2235 ps_dec->s_high_profile.ps_sigcoeff_8x8_frame = p_cabac_ctxt_table_t
2236 + SIGNIFICANT_COEFF_FLAG_8X8_FRAME;
2237
2238 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_frame =
2239 p_cabac_ctxt_table_t
2240 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FRAME;
2241
2242 ps_dec->s_high_profile.ps_coeff_abs_levelminus1 =
2243 p_cabac_ctxt_table_t + COEFF_ABS_LEVEL_MINUS1_8X8;
2244
2245 ps_dec->s_high_profile.ps_sigcoeff_8x8_field = p_cabac_ctxt_table_t
2246 + SIGNIFICANT_COEFF_FLAG_8X8_FIELD;
2247
2248 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_field =
2249 p_cabac_ctxt_table_t
2250 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FIELD;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2251 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2252 }
2253 return (i16_status);
2254}
2255
2256/*!
2257 **************************************************************************
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2258 * \if Function name : ih264d_free_dynamic_bufs \endif
2259 *
2260 * \brief
2261 * This function frees dynamic memory allocated by Decoder.
2262 *
2263 * \param ps_dec: Pointer to dec_struct_t.
2264 *
2265 * \return
2266 * Returns i4_status as returned by MemManager.
2267 *
2268 **************************************************************************
2269 */
2270WORD16 ih264d_free_dynamic_bufs(dec_struct_t * ps_dec)
2271{
2272 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_dynamic);
2273
2274 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_pic);
2275 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_dec_mb_map);
2276 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_recon_mb_map);
2277 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu2_slice_num_map);
2278 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_slice_buf);
2279 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_frm_mb_info);
2280 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_coeff_data);
2281 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_mb_data);
2282 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_part_params);
2283 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_top_mb);
2284
2285 if(ps_dec->p_ctxt_inc_mb_map)
2286 {
2287 ps_dec->p_ctxt_inc_mb_map -= 1;
2288 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_ctxt_inc_mb_map);
2289 }
2290
2291 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[0]);
2292 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[1]);
2293 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred_pkd);
2294 {
2295 UWORD8 i;
2296 for(i = 0; i < MV_SCRATCH_BUFS; i++)
2297 {
2298 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_top_p[i]);
2299 }
2300 }
2301
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]2302 if(ps_dec->pu1_y_intra_pred_line)
2303 {
2304 ps_dec->pu1_y_intra_pred_line -= MB_SIZE;
2305 }
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2306 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_y_intra_pred_line);
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]2307
2308 if(ps_dec->pu1_u_intra_pred_line)
2309 {
2310 ps_dec->pu1_u_intra_pred_line -= MB_SIZE;
2311 }
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2312 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_u_intra_pred_line);
Harish Mahendrakar07ae78b2015-08-26 08:58:53 +0530[diff] [blame]2313
2314 if(ps_dec->pu1_v_intra_pred_line)
2315 {
2316 ps_dec->pu1_v_intra_pred_line -= MB_SIZE;
2317 }
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2318 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_v_intra_pred_line);
2319 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_nbr_mb_row);
2320 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_mv_bank_buf_base);
2321 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_pic_buf_base);
2322 return 0;
2323}
2324
2325/*!
2326 **************************************************************************
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2327 * \if Function name : ih264d_create_mv_bank \endif
2328 *
2329 * \brief
2330 * This function creates MV bank.
2331 *
2332 * \param memType : Type of memory being handled
2333 * 0: Display Buffer
2334 * 1: Decoder Buffer
2335 * 2: Internal Buffer
2336 * \param u1_num_of_buf: Number of decode or display buffers.
2337 * \param u4_wd : Frame width.
2338 * \param u4_ht : Frame Height.
2339 * \param ps_pic_buf_api : Pointer to Picture Buffer API.
2340 * \param ih264d_dec_mem_manager : Memory manager utility supplied by system.
2341 *
2342 * \return
2343 * 0 on Success and -1 on error
2344 *
2345 **************************************************************************
2346 */
2347WORD32 ih264d_create_mv_bank(void *pv_dec,
2348 UWORD32 ui_width,
2349 UWORD32 ui_height)
2350{
2351 UWORD8 i;
2352 UWORD32 col_flag_buffer_size, mvpred_buffer_size;
2353 UWORD8 *pu1_mv_buf_mgr_base, *pu1_mv_bank_base;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2354 col_mv_buf_t *ps_col_mv;
2355 mv_pred_t *ps_mv;
2356 UWORD8 *pu1_col_zero_flag_buf;
2357 dec_struct_t *ps_dec = (dec_struct_t *)pv_dec;
2358 WORD32 buf_ret;
Hamsalekha S8a503282015-07-28 14:41:24 +0530[diff] [blame]2359 UWORD32 u4_num_bufs;
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2360 UWORD8 *pu1_buf;
2361 WORD32 size;
2362 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2363
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2364 col_flag_buffer_size = ((ui_width * ui_height) >> 4);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2365 mvpred_buffer_size = sizeof(mv_pred_t)
2366 * ((ui_width * (ui_height + PAD_MV_BANK_ROW)) >> 4);
2367
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2368 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_mv_buf_mgr);
2369
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2370 ps_col_mv = ps_dec->ps_col_mv_base;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2371
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2372 u4_num_bufs = ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
Hamsalekha S8a503282015-07-28 14:41:24 +0530[diff] [blame]2373
2374 u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs);
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2375 u4_num_bufs = MAX(u4_num_bufs, 2);
2376 pu1_buf = ps_dec->pu1_mv_bank_buf_base;
Hamsalekha S8a503282015-07-28 14:41:24 +0530[diff] [blame]2377 for(i = 0 ; i < u4_num_bufs ; i++)
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2378 {
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2379 pu1_col_zero_flag_buf = pu1_buf;
2380 pu1_buf += ALIGN64(col_flag_buffer_size);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2381
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2382 ps_mv = (mv_pred_t *)pu1_buf;
2383 pu1_buf += ALIGN64(mvpred_buffer_size);
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2384
Harish Mahendrakar251b0072015-08-04 09:55:15 +0530[diff] [blame]2385 memset(ps_mv, 0, ((ui_width * OFFSET_MV_BANK_ROW) >> 4) * sizeof(mv_pred_t));
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2386 ps_mv += (ui_width*OFFSET_MV_BANK_ROW) >> 4;
2387
2388 ps_col_mv->pv_col_zero_flag = (void *)pu1_col_zero_flag_buf;
2389 ps_col_mv->pv_mv = (void *)ps_mv;
2390 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_mv_buf_mgr, ps_col_mv, i);
2391 if(0 != buf_ret)
2392 {
2393 ps_dec->i4_error_code = ERROR_BUF_MGR;
2394 return ERROR_BUF_MGR;
2395 }
2396 ps_col_mv++;
2397 }
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2398 return OK;
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2399}
2400
Hamsalekha S8d3d3032015-03-13 21:24:58 +0530[diff] [blame]2401void ih264d_unpack_coeff4x4_dc_4x4blk(tu_sblk4x4_coeff_data_t *ps_tu_4x4,
2402 WORD16 *pi2_out_coeff_data,
2403 UWORD8 *pu1_inv_scan)
2404{
2405 UWORD16 u2_sig_coeff_map = ps_tu_4x4->u2_sig_coeff_map;
2406 WORD32 idx;
2407 WORD16 *pi2_coeff_data = &ps_tu_4x4->ai2_level[0];
2408
2409 while(u2_sig_coeff_map)
2410 {
2411 idx = CLZ(u2_sig_coeff_map);
2412
2413 idx = 31 - idx;
2414 RESET_BIT(u2_sig_coeff_map,idx);
2415
2416 idx = pu1_inv_scan[idx];
2417 pi2_out_coeff_data[idx] = *pi2_coeff_data++;
2418
2419 }
2420}