license.bot | f003cfe | 2008-08-24 09:55:55 +0900 | [diff] [blame] | 1 | // Copyright (c) 2006-2008 The Chromium Authors. All rights reserved. |
| 2 | // Use of this source code is governed by a BSD-style license that can be |
| 3 | // found in the LICENSE file. |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 4 | |
| 5 | // This file is an internal atomic implementation, use base/atomicops.h instead. |
| 6 | |
| 7 | #ifndef BASE_ATOMICOPS_INTERNALS_X86_MSVC_H_ |
| 8 | #define BASE_ATOMICOPS_INTERNALS_X86_MSVC_H_ |
| 9 | |
Bruce Dawson | 052dd80 | 2018-01-04 05:32:36 +0900 | [diff] [blame] | 10 | #include "base/win/windows_types.h" |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 11 | |
sebmarchand@chromium.org | e41fbd7 | 2014-06-13 01:17:26 +0900 | [diff] [blame] | 12 | #include <intrin.h> |
| 13 | |
ctruta@blackberry.com | 83bafe8 | 2014-02-08 13:59:55 +0900 | [diff] [blame] | 14 | #include "base/macros.h" |
avi | a6a6a68 | 2015-12-27 07:15:14 +0900 | [diff] [blame] | 15 | #include "build/build_config.h" |
ctruta@blackberry.com | 83bafe8 | 2014-02-08 13:59:55 +0900 | [diff] [blame] | 16 | |
scottmg@chromium.org | 80f6b33 | 2013-01-15 17:51:28 +0900 | [diff] [blame] | 17 | #if defined(ARCH_CPU_64_BITS) |
| 18 | // windows.h #defines this (only on x64). This causes problems because the |
| 19 | // public API also uses MemoryBarrier at the public name for this fence. So, on |
| 20 | // X64, undef it, and call its documented |
| 21 | // (http://msdn.microsoft.com/en-us/library/windows/desktop/ms684208.aspx) |
| 22 | // implementation directly. |
| 23 | #undef MemoryBarrier |
| 24 | #endif |
| 25 | |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 26 | namespace base { |
| 27 | namespace subtle { |
| 28 | |
| 29 | inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr, |
| 30 | Atomic32 old_value, |
| 31 | Atomic32 new_value) { |
sebmarchand@chromium.org | e41fbd7 | 2014-06-13 01:17:26 +0900 | [diff] [blame] | 32 | LONG result = _InterlockedCompareExchange( |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 33 | reinterpret_cast<volatile LONG*>(ptr), |
| 34 | static_cast<LONG>(new_value), |
| 35 | static_cast<LONG>(old_value)); |
| 36 | return static_cast<Atomic32>(result); |
| 37 | } |
| 38 | |
| 39 | inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr, |
| 40 | Atomic32 new_value) { |
sebmarchand@chromium.org | e41fbd7 | 2014-06-13 01:17:26 +0900 | [diff] [blame] | 41 | LONG result = _InterlockedExchange( |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 42 | reinterpret_cast<volatile LONG*>(ptr), |
| 43 | static_cast<LONG>(new_value)); |
| 44 | return static_cast<Atomic32>(result); |
| 45 | } |
| 46 | |
| 47 | inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr, |
| 48 | Atomic32 increment) { |
sebmarchand@chromium.org | e41fbd7 | 2014-06-13 01:17:26 +0900 | [diff] [blame] | 49 | return _InterlockedExchangeAdd( |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 50 | reinterpret_cast<volatile LONG*>(ptr), |
| 51 | static_cast<LONG>(increment)) + increment; |
| 52 | } |
| 53 | |
| 54 | inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr, |
| 55 | Atomic32 increment) { |
| 56 | return Barrier_AtomicIncrement(ptr, increment); |
| 57 | } |
| 58 | |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 59 | inline void MemoryBarrier() { |
scottmg@chromium.org | 80f6b33 | 2013-01-15 17:51:28 +0900 | [diff] [blame] | 60 | #if defined(ARCH_CPU_64_BITS) |
| 61 | // See #undef and note at the top of this file. |
| 62 | __faststorefence(); |
| 63 | #else |
Bruce Dawson | 052dd80 | 2018-01-04 05:32:36 +0900 | [diff] [blame] | 64 | // We use the implementation of MemoryBarrier from WinNT.h |
| 65 | LONG barrier; |
| 66 | |
| 67 | _InterlockedOr(&barrier, 0); |
scottmg@chromium.org | 80f6b33 | 2013-01-15 17:51:28 +0900 | [diff] [blame] | 68 | #endif |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 69 | } |
| 70 | |
| 71 | inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr, |
| 72 | Atomic32 old_value, |
| 73 | Atomic32 new_value) { |
| 74 | return NoBarrier_CompareAndSwap(ptr, old_value, new_value); |
| 75 | } |
| 76 | |
| 77 | inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr, |
| 78 | Atomic32 old_value, |
| 79 | Atomic32 new_value) { |
| 80 | return NoBarrier_CompareAndSwap(ptr, old_value, new_value); |
| 81 | } |
| 82 | |
| 83 | inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) { |
| 84 | *ptr = value; |
| 85 | } |
| 86 | |
| 87 | inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) { |
| 88 | NoBarrier_AtomicExchange(ptr, value); |
| 89 | // acts as a barrier in this implementation |
| 90 | } |
| 91 | |
| 92 | inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) { |
| 93 | *ptr = value; // works w/o barrier for current Intel chips as of June 2005 |
| 94 | // See comments in Atomic64 version of Release_Store() below. |
| 95 | } |
| 96 | |
| 97 | inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) { |
| 98 | return *ptr; |
| 99 | } |
| 100 | |
| 101 | inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) { |
| 102 | Atomic32 value = *ptr; |
| 103 | return value; |
| 104 | } |
| 105 | |
| 106 | inline Atomic32 Release_Load(volatile const Atomic32* ptr) { |
| 107 | MemoryBarrier(); |
| 108 | return *ptr; |
| 109 | } |
| 110 | |
| 111 | #if defined(_WIN64) |
| 112 | |
| 113 | // 64-bit low-level operations on 64-bit platform. |
| 114 | |
avi | 486c61f | 2015-11-24 23:26:24 +0900 | [diff] [blame] | 115 | static_assert(sizeof(Atomic64) == sizeof(PVOID), "atomic word is atomic"); |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 116 | |
| 117 | inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr, |
| 118 | Atomic64 old_value, |
| 119 | Atomic64 new_value) { |
Bruce Dawson | 052dd80 | 2018-01-04 05:32:36 +0900 | [diff] [blame] | 120 | PVOID result = _InterlockedCompareExchangePointer( |
| 121 | reinterpret_cast<volatile PVOID*>(ptr), |
| 122 | reinterpret_cast<PVOID>(new_value), reinterpret_cast<PVOID>(old_value)); |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 123 | return reinterpret_cast<Atomic64>(result); |
| 124 | } |
| 125 | |
| 126 | inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr, |
| 127 | Atomic64 new_value) { |
Bruce Dawson | 052dd80 | 2018-01-04 05:32:36 +0900 | [diff] [blame] | 128 | PVOID result = |
| 129 | _InterlockedExchangePointer(reinterpret_cast<volatile PVOID*>(ptr), |
| 130 | reinterpret_cast<PVOID>(new_value)); |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 131 | return reinterpret_cast<Atomic64>(result); |
| 132 | } |
| 133 | |
| 134 | inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr, |
| 135 | Atomic64 increment) { |
Bruce Dawson | 052dd80 | 2018-01-04 05:32:36 +0900 | [diff] [blame] | 136 | return _InterlockedExchangeAdd64(reinterpret_cast<volatile LONGLONG*>(ptr), |
| 137 | static_cast<LONGLONG>(increment)) + |
| 138 | increment; |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr, |
| 142 | Atomic64 increment) { |
| 143 | return Barrier_AtomicIncrement(ptr, increment); |
| 144 | } |
| 145 | |
| 146 | inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) { |
| 147 | *ptr = value; |
| 148 | } |
| 149 | |
| 150 | inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) { |
| 151 | NoBarrier_AtomicExchange(ptr, value); |
| 152 | // acts as a barrier in this implementation |
| 153 | } |
| 154 | |
| 155 | inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) { |
| 156 | *ptr = value; // works w/o barrier for current Intel chips as of June 2005 |
| 157 | |
| 158 | // When new chips come out, check: |
| 159 | // IA-32 Intel Architecture Software Developer's Manual, Volume 3: |
| 160 | // System Programming Guide, Chatper 7: Multiple-processor management, |
| 161 | // Section 7.2, Memory Ordering. |
| 162 | // Last seen at: |
| 163 | // http://developer.intel.com/design/pentium4/manuals/index_new.htm |
| 164 | } |
| 165 | |
| 166 | inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) { |
| 167 | return *ptr; |
| 168 | } |
| 169 | |
| 170 | inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) { |
| 171 | Atomic64 value = *ptr; |
| 172 | return value; |
| 173 | } |
| 174 | |
| 175 | inline Atomic64 Release_Load(volatile const Atomic64* ptr) { |
| 176 | MemoryBarrier(); |
| 177 | return *ptr; |
| 178 | } |
| 179 | |
gregoryd@google.com | 3734a87 | 2009-11-07 08:24:09 +0900 | [diff] [blame] | 180 | inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr, |
| 181 | Atomic64 old_value, |
| 182 | Atomic64 new_value) { |
| 183 | return NoBarrier_CompareAndSwap(ptr, old_value, new_value); |
| 184 | } |
| 185 | |
| 186 | inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr, |
| 187 | Atomic64 old_value, |
| 188 | Atomic64 new_value) { |
| 189 | return NoBarrier_CompareAndSwap(ptr, old_value, new_value); |
| 190 | } |
| 191 | |
| 192 | |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 193 | #endif // defined(_WIN64) |
| 194 | |
danakj | 651c3e2 | 2015-03-07 10:51:42 +0900 | [diff] [blame] | 195 | } // namespace subtle |
deanm@google.com | 1579ec7 | 2008-08-05 18:57:36 +0900 | [diff] [blame] | 196 | } // namespace base |
| 197 | |
| 198 | #endif // BASE_ATOMICOPS_INTERNALS_X86_MSVC_H_ |