Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright © 2014 Advanced Micro Devices, Inc. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #ifndef _AMDGPU_INTERNAL_H_ |
| 25 | #define _AMDGPU_INTERNAL_H_ |
| 26 | |
| 27 | #ifdef HAVE_CONFIG_H |
| 28 | #include "config.h" |
| 29 | #endif |
| 30 | |
| 31 | #include <assert.h> |
| 32 | #include <pthread.h> |
| 33 | #include "xf86atomic.h" |
| 34 | #include "amdgpu.h" |
| 35 | #include "util_double_list.h" |
| 36 | |
| 37 | #define AMDGPU_CS_MAX_RINGS 8 |
| 38 | |
| 39 | struct amdgpu_bo_va_hole { |
| 40 | struct list_head list; |
| 41 | uint64_t offset; |
| 42 | uint64_t size; |
| 43 | }; |
| 44 | |
| 45 | struct amdgpu_bo_va_mgr { |
| 46 | /* the start virtual address */ |
| 47 | uint64_t va_offset; |
| 48 | struct list_head va_holes; |
| 49 | pthread_mutex_t bo_va_mutex; |
| 50 | uint32_t va_alignment; |
| 51 | }; |
| 52 | |
| 53 | struct amdgpu_device { |
| 54 | atomic_t refcount; |
| 55 | int fd; |
| 56 | int flink_fd; |
| 57 | unsigned major_version; |
| 58 | unsigned minor_version; |
| 59 | |
| 60 | /** List of buffer handles. Protected by bo_table_mutex. */ |
| 61 | struct util_hash_table *bo_handles; |
| 62 | /** List of buffer GEM flink names. Protected by bo_table_mutex. */ |
| 63 | struct util_hash_table *bo_flink_names; |
| 64 | /** List of buffer virtual memory ranges. Protected by bo_table_mutex. */ |
| 65 | struct util_hash_table *bo_vas; |
| 66 | /** This protects all hash tables. */ |
| 67 | pthread_mutex_t bo_table_mutex; |
| 68 | struct amdgpu_bo_va_mgr vamgr; |
| 69 | struct drm_amdgpu_info_device dev_info; |
| 70 | struct amdgpu_gpu_info info; |
| 71 | }; |
| 72 | |
| 73 | struct amdgpu_bo { |
| 74 | atomic_t refcount; |
| 75 | struct amdgpu_device *dev; |
| 76 | |
| 77 | uint64_t alloc_size; |
| 78 | uint64_t virtual_mc_base_address; |
| 79 | |
| 80 | uint32_t handle; |
| 81 | uint32_t flink_name; |
| 82 | |
| 83 | pthread_mutex_t cpu_access_mutex; |
| 84 | void *cpu_ptr; |
| 85 | int cpu_map_count; |
| 86 | }; |
| 87 | |
| 88 | /* |
| 89 | * There are three mutexes. |
| 90 | * To avoid deadlock, only hold the mutexes in this order: |
| 91 | * sequence_mutex -> pendings_mutex -> pool_mutex. |
| 92 | */ |
| 93 | struct amdgpu_context { |
| 94 | /** Mutex for accessing fences and to maintain command submissions |
| 95 | and pending lists in good sequence. */ |
| 96 | pthread_mutex_t sequence_mutex; |
| 97 | /** Buffer for user fences */ |
| 98 | struct amdgpu_ib *fence_ib; |
| 99 | /** The newest expired fence for the ring of the ip blocks. */ |
| 100 | uint64_t expired_fences[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS]; |
| 101 | /** Mutex for accessing pendings list. */ |
| 102 | pthread_mutex_t pendings_mutex; |
| 103 | /** Pending IBs. */ |
| 104 | struct list_head pendings[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS]; |
| 105 | /** Freed IBs not yet in pool */ |
| 106 | struct list_head freed; |
| 107 | /** Mutex for accessing free ib pool. */ |
| 108 | pthread_mutex_t pool_mutex; |
| 109 | /** Internal free IB pools. */ |
| 110 | struct list_head ib_pools[AMDGPU_CS_IB_SIZE_NUM]; |
| 111 | /* context id*/ |
| 112 | uint32_t id; |
| 113 | }; |
| 114 | |
| 115 | struct amdgpu_ib { |
| 116 | struct list_head list_node; |
| 117 | amdgpu_bo_handle buf_handle; |
| 118 | void *cpu; |
| 119 | uint64_t virtual_mc_base_address; |
| 120 | enum amdgpu_cs_ib_size ib_size; |
| 121 | uint64_t cs_handle; |
| 122 | }; |
| 123 | |
| 124 | /** |
| 125 | * Functions. |
| 126 | */ |
| 127 | |
| 128 | void amdgpu_device_free_internal(amdgpu_device_handle dev); |
| 129 | |
| 130 | void amdgpu_bo_free_internal(amdgpu_bo_handle bo); |
| 131 | |
| 132 | void amdgpu_vamgr_init(struct amdgpu_device *dev); |
| 133 | |
| 134 | uint64_t amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, |
| 135 | uint64_t size, uint64_t alignment); |
| 136 | |
| 137 | void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va, |
| 138 | uint64_t size); |
| 139 | |
| 140 | int amdgpu_query_gpu_info_init(amdgpu_device_handle dev); |
| 141 | |
| 142 | uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout); |
| 143 | |
| 144 | /** |
| 145 | * Inline functions. |
| 146 | */ |
| 147 | |
| 148 | /** |
| 149 | * Increment src and decrement dst as if we were updating references |
| 150 | * for an assignment between 2 pointers of some objects. |
| 151 | * |
| 152 | * \return true if dst is 0 |
| 153 | */ |
| 154 | static inline bool update_references(atomic_t *dst, atomic_t *src) |
| 155 | { |
| 156 | if (dst != src) { |
| 157 | /* bump src first */ |
| 158 | if (src) { |
| 159 | assert(atomic_read(src) > 0); |
| 160 | atomic_inc(src); |
| 161 | } |
| 162 | if (dst) { |
| 163 | assert(atomic_read(dst) > 0); |
| 164 | return atomic_dec_and_test(dst); |
| 165 | } |
| 166 | } |
| 167 | return false; |
| 168 | } |
| 169 | |
| 170 | /** |
| 171 | * Assignment between two amdgpu_bo pointers with reference counting. |
| 172 | * |
| 173 | * Usage: |
| 174 | * struct amdgpu_bo *dst = ... , *src = ...; |
| 175 | * |
| 176 | * dst = src; |
| 177 | * // No reference counting. Only use this when you need to move |
| 178 | * // a reference from one pointer to another. |
| 179 | * |
| 180 | * amdgpu_bo_reference(&dst, src); |
| 181 | * // Reference counters are updated. dst is decremented and src is |
| 182 | * // incremented. dst is freed if its reference counter is 0. |
| 183 | */ |
| 184 | static inline void amdgpu_bo_reference(struct amdgpu_bo **dst, |
| 185 | struct amdgpu_bo *src) |
| 186 | { |
| 187 | if (update_references(&(*dst)->refcount, &src->refcount)) |
| 188 | amdgpu_bo_free_internal(*dst); |
| 189 | *dst = src; |
| 190 | } |
| 191 | |
| 192 | /** |
| 193 | * Assignment between two amdgpu_device pointers with reference counting. |
| 194 | * |
| 195 | * Usage: |
| 196 | * struct amdgpu_device *dst = ... , *src = ...; |
| 197 | * |
| 198 | * dst = src; |
| 199 | * // No reference counting. Only use this when you need to move |
| 200 | * // a reference from one pointer to another. |
| 201 | * |
| 202 | * amdgpu_device_reference(&dst, src); |
| 203 | * // Reference counters are updated. dst is decremented and src is |
| 204 | * // incremented. dst is freed if its reference counter is 0. |
| 205 | */ |
| 206 | void amdgpu_device_reference(struct amdgpu_device **dst, |
| 207 | struct amdgpu_device *src); |
| 208 | #endif |