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gerrit-public.fairphone.software / platform / external / libdrm / 353f073bc134a94d13fe82e4f3d983efe3cf70ad / . / radeon / r600_pci_ids.h
blob: ccc3ea5c714a39fb7208173fbe1c1f349e755a73 [file] [log] [blame]
Jerome Glissec51f7f02011-12-09 21:07:15 -0500[diff] [blame]1CHIPSET(0x9400, R600_9400, R600)
2CHIPSET(0x9401, R600_9401, R600)
3CHIPSET(0x9402, R600_9402, R600)
4CHIPSET(0x9403, R600_9403, R600)
5CHIPSET(0x9405, R600_9405, R600)
6CHIPSET(0x940A, R600_940A, R600)
7CHIPSET(0x940B, R600_940B, R600)
8CHIPSET(0x940F, R600_940F, R600)
9
10CHIPSET(0x94C0, RV610_94C0, RV610)
11CHIPSET(0x94C1, RV610_94C1, RV610)
12CHIPSET(0x94C3, RV610_94C3, RV610)
13CHIPSET(0x94C4, RV610_94C4, RV610)
14CHIPSET(0x94C5, RV610_94C5, RV610)
15CHIPSET(0x94C6, RV610_94C6, RV610)
16CHIPSET(0x94C7, RV610_94C7, RV610)
17CHIPSET(0x94C8, RV610_94C8, RV610)
18CHIPSET(0x94C9, RV610_94C9, RV610)
19CHIPSET(0x94CB, RV610_94CB, RV610)
20CHIPSET(0x94CC, RV610_94CC, RV610)
21CHIPSET(0x94CD, RV610_94CD, RV610)
22
23CHIPSET(0x9580, RV630_9580, RV630)
24CHIPSET(0x9581, RV630_9581, RV630)
25CHIPSET(0x9583, RV630_9583, RV630)
26CHIPSET(0x9586, RV630_9586, RV630)
27CHIPSET(0x9587, RV630_9587, RV630)
28CHIPSET(0x9588, RV630_9588, RV630)
29CHIPSET(0x9589, RV630_9589, RV630)
30CHIPSET(0x958A, RV630_958A, RV630)
31CHIPSET(0x958B, RV630_958B, RV630)
32CHIPSET(0x958C, RV630_958C, RV630)
33CHIPSET(0x958D, RV630_958D, RV630)
34CHIPSET(0x958E, RV630_958E, RV630)
35CHIPSET(0x958F, RV630_958F, RV630)
36
37CHIPSET(0x9500, RV670_9500, RV670)
38CHIPSET(0x9501, RV670_9501, RV670)
39CHIPSET(0x9504, RV670_9504, RV670)
40CHIPSET(0x9505, RV670_9505, RV670)
41CHIPSET(0x9506, RV670_9506, RV670)
42CHIPSET(0x9507, RV670_9507, RV670)
43CHIPSET(0x9508, RV670_9508, RV670)
44CHIPSET(0x9509, RV670_9509, RV670)
45CHIPSET(0x950F, RV670_950F, RV670)
46CHIPSET(0x9511, RV670_9511, RV670)
47CHIPSET(0x9515, RV670_9515, RV670)
48CHIPSET(0x9517, RV670_9517, RV670)
49CHIPSET(0x9519, RV670_9519, RV670)
50
51CHIPSET(0x95C0, RV620_95C0, RV620)
52CHIPSET(0x95C2, RV620_95C2, RV620)
53CHIPSET(0x95C4, RV620_95C4, RV620)
54CHIPSET(0x95C5, RV620_95C5, RV620)
55CHIPSET(0x95C6, RV620_95C6, RV620)
56CHIPSET(0x95C7, RV620_95C7, RV620)
57CHIPSET(0x95C9, RV620_95C9, RV620)
58CHIPSET(0x95CC, RV620_95CC, RV620)
59CHIPSET(0x95CD, RV620_95CD, RV620)
60CHIPSET(0x95CE, RV620_95CE, RV620)
61CHIPSET(0x95CF, RV620_95CF, RV620)
62
63CHIPSET(0x9590, RV635_9590, RV635)
64CHIPSET(0x9591, RV635_9591, RV635)
65CHIPSET(0x9593, RV635_9593, RV635)
66CHIPSET(0x9595, RV635_9595, RV635)
67CHIPSET(0x9596, RV635_9596, RV635)
68CHIPSET(0x9597, RV635_9597, RV635)
69CHIPSET(0x9598, RV635_9598, RV635)
70CHIPSET(0x9599, RV635_9599, RV635)
71CHIPSET(0x959B, RV635_959B, RV635)
72
73CHIPSET(0x9610, RS780_9610, RS780)
74CHIPSET(0x9611, RS780_9611, RS780)
75CHIPSET(0x9612, RS780_9612, RS780)
76CHIPSET(0x9613, RS780_9613, RS780)
77CHIPSET(0x9614, RS780_9614, RS780)
78CHIPSET(0x9615, RS780_9615, RS780)
79CHIPSET(0x9616, RS780_9616, RS780)
80
81CHIPSET(0x9710, RS880_9710, RS880)
82CHIPSET(0x9711, RS880_9711, RS880)
83CHIPSET(0x9712, RS880_9712, RS880)
84CHIPSET(0x9713, RS880_9713, RS880)
85CHIPSET(0x9714, RS880_9714, RS880)
86CHIPSET(0x9715, RS880_9715, RS880)
87
88CHIPSET(0x9440, RV770_9440, RV770)
89CHIPSET(0x9441, RV770_9441, RV770)
90CHIPSET(0x9442, RV770_9442, RV770)
91CHIPSET(0x9443, RV770_9443, RV770)
92CHIPSET(0x9444, RV770_9444, RV770)
93CHIPSET(0x9446, RV770_9446, RV770)
94CHIPSET(0x944A, RV770_944A, RV770)
95CHIPSET(0x944B, RV770_944B, RV770)
96CHIPSET(0x944C, RV770_944C, RV770)
97CHIPSET(0x944E, RV770_944E, RV770)
98CHIPSET(0x9450, RV770_9450, RV770)
99CHIPSET(0x9452, RV770_9452, RV770)
100CHIPSET(0x9456, RV770_9456, RV770)
101CHIPSET(0x945A, RV770_945A, RV770)
102CHIPSET(0x945B, RV770_945B, RV770)
103CHIPSET(0x945E, RV770_945E, RV770)
104CHIPSET(0x9460, RV790_9460, RV770)
105CHIPSET(0x9462, RV790_9462, RV770)
106CHIPSET(0x946A, RV770_946A, RV770)
107CHIPSET(0x946B, RV770_946B, RV770)
108CHIPSET(0x947A, RV770_947A, RV770)
109CHIPSET(0x947B, RV770_947B, RV770)
110
111CHIPSET(0x9480, RV730_9480, RV730)
112CHIPSET(0x9487, RV730_9487, RV730)
113CHIPSET(0x9488, RV730_9488, RV730)
114CHIPSET(0x9489, RV730_9489, RV730)
115CHIPSET(0x948A, RV730_948A, RV730)
116CHIPSET(0x948F, RV730_948F, RV730)
117CHIPSET(0x9490, RV730_9490, RV730)
118CHIPSET(0x9491, RV730_9491, RV730)
119CHIPSET(0x9495, RV730_9495, RV730)
120CHIPSET(0x9498, RV730_9498, RV730)
121CHIPSET(0x949C, RV730_949C, RV730)
122CHIPSET(0x949E, RV730_949E, RV730)
123CHIPSET(0x949F, RV730_949F, RV730)
124
125CHIPSET(0x9540, RV710_9540, RV710)
126CHIPSET(0x9541, RV710_9541, RV710)
127CHIPSET(0x9542, RV710_9542, RV710)
128CHIPSET(0x954E, RV710_954E, RV710)
129CHIPSET(0x954F, RV710_954F, RV710)
130CHIPSET(0x9552, RV710_9552, RV710)
131CHIPSET(0x9553, RV710_9553, RV710)
132CHIPSET(0x9555, RV710_9555, RV710)
133CHIPSET(0x9557, RV710_9557, RV710)
134CHIPSET(0x955F, RV710_955F, RV710)
135
136CHIPSET(0x94A0, RV740_94A0, RV740)
137CHIPSET(0x94A1, RV740_94A1, RV740)
138CHIPSET(0x94A3, RV740_94A3, RV740)
139CHIPSET(0x94B1, RV740_94B1, RV740)
140CHIPSET(0x94B3, RV740_94B3, RV740)
141CHIPSET(0x94B4, RV740_94B4, RV740)
142CHIPSET(0x94B5, RV740_94B5, RV740)
143CHIPSET(0x94B9, RV740_94B9, RV740)
144
145CHIPSET(0x68E0, CEDAR_68E0, CEDAR)
146CHIPSET(0x68E1, CEDAR_68E1, CEDAR)
147CHIPSET(0x68E4, CEDAR_68E4, CEDAR)
148CHIPSET(0x68E5, CEDAR_68E5, CEDAR)
149CHIPSET(0x68E8, CEDAR_68E8, CEDAR)
150CHIPSET(0x68E9, CEDAR_68E9, CEDAR)
151CHIPSET(0x68F1, CEDAR_68F1, CEDAR)
152CHIPSET(0x68F2, CEDAR_68F2, CEDAR)
153CHIPSET(0x68F8, CEDAR_68F8, CEDAR)
154CHIPSET(0x68F9, CEDAR_68F9, CEDAR)
Anisse Astiercf7cc622012-05-10 17:56:14 +0200[diff] [blame]155CHIPSET(0x68FA, CEDAR_68FA, CEDAR)
Jerome Glissec51f7f02011-12-09 21:07:15 -0500[diff] [blame]156CHIPSET(0x68FE, CEDAR_68FE, CEDAR)
157
158CHIPSET(0x68C0, REDWOOD_68C0, REDWOOD)
159CHIPSET(0x68C1, REDWOOD_68C1, REDWOOD)
Alex Deucherdd944a02012-08-06 10:29:24 -0400[diff] [blame]160CHIPSET(0x68C7, REDWOOD_68C7, REDWOOD)
Jerome Glissec51f7f02011-12-09 21:07:15 -0500[diff] [blame]161CHIPSET(0x68C8, REDWOOD_68C8, REDWOOD)
162CHIPSET(0x68C9, REDWOOD_68C9, REDWOOD)
163CHIPSET(0x68D8, REDWOOD_68D8, REDWOOD)
164CHIPSET(0x68D9, REDWOOD_68D9, REDWOOD)
165CHIPSET(0x68DA, REDWOOD_68DA, REDWOOD)
166CHIPSET(0x68DE, REDWOOD_68DE, REDWOOD)
167
168CHIPSET(0x68A0, JUNIPER_68A0, JUNIPER)
169CHIPSET(0x68A1, JUNIPER_68A1, JUNIPER)
170CHIPSET(0x68A8, JUNIPER_68A8, JUNIPER)
171CHIPSET(0x68A9, JUNIPER_68A9, JUNIPER)
172CHIPSET(0x68B0, JUNIPER_68B0, JUNIPER)
173CHIPSET(0x68B8, JUNIPER_68B8, JUNIPER)
174CHIPSET(0x68B9, JUNIPER_68B9, JUNIPER)
175CHIPSET(0x68BA, JUNIPER_68BA, JUNIPER)
176CHIPSET(0x68BE, JUNIPER_68BE, JUNIPER)
177CHIPSET(0x68BF, JUNIPER_68BF, JUNIPER)
178
179CHIPSET(0x6880, CYPRESS_6880, CYPRESS)
180CHIPSET(0x6888, CYPRESS_6888, CYPRESS)
181CHIPSET(0x6889, CYPRESS_6889, CYPRESS)
182CHIPSET(0x688A, CYPRESS_688A, CYPRESS)
Alex Deucherdd944a02012-08-06 10:29:24 -0400[diff] [blame]183CHIPSET(0x688C, CYPRESS_688C, CYPRESS)
184CHIPSET(0x688D, CYPRESS_688D, CYPRESS)
Jerome Glissec51f7f02011-12-09 21:07:15 -0500[diff] [blame]185CHIPSET(0x6898, CYPRESS_6898, CYPRESS)
186CHIPSET(0x6899, CYPRESS_6899, CYPRESS)
187CHIPSET(0x689B, CYPRESS_689B, CYPRESS)
188CHIPSET(0x689E, CYPRESS_689E, CYPRESS)
189
190CHIPSET(0x689C, HEMLOCK_689C, HEMLOCK)
191CHIPSET(0x689D, HEMLOCK_689D, HEMLOCK)
192
193CHIPSET(0x9802, PALM_9802, PALM)
194CHIPSET(0x9803, PALM_9803, PALM)
195CHIPSET(0x9804, PALM_9804, PALM)
196CHIPSET(0x9805, PALM_9805, PALM)
197CHIPSET(0x9806, PALM_9806, PALM)
198CHIPSET(0x9807, PALM_9807, PALM)
Anisse Astiercf7cc622012-05-10 17:56:14 +0200[diff] [blame]199CHIPSET(0x9808, PALM_9808, PALM)
200CHIPSET(0x9809, PALM_9809, PALM)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]201CHIPSET(0x980A, PALM_980A, PALM)
Jerome Glissec51f7f02011-12-09 21:07:15 -0500[diff] [blame]202
203CHIPSET(0x9640, SUMO_9640, SUMO)
204CHIPSET(0x9641, SUMO_9641, SUMO)
205CHIPSET(0x9642, SUMO2_9642, SUMO2)
206CHIPSET(0x9643, SUMO2_9643, SUMO2)
207CHIPSET(0x9644, SUMO2_9644, SUMO2)
208CHIPSET(0x9645, SUMO2_9645, SUMO2)
209CHIPSET(0x9647, SUMO_9647, SUMO)
210CHIPSET(0x9648, SUMO_9648, SUMO)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]211CHIPSET(0x9649, SUMO_9649, SUMO)
Jerome Glissec51f7f02011-12-09 21:07:15 -0500[diff] [blame]212CHIPSET(0x964a, SUMO_964A, SUMO)
Anisse Astiercf7cc622012-05-10 17:56:14 +0200[diff] [blame]213CHIPSET(0x964b, SUMO_964B, SUMO)
214CHIPSET(0x964c, SUMO_964C, SUMO)
Jerome Glissec51f7f02011-12-09 21:07:15 -0500[diff] [blame]215CHIPSET(0x964e, SUMO_964E, SUMO)
216CHIPSET(0x964f, SUMO_964F, SUMO)
217
218CHIPSET(0x6700, CAYMAN_6700, CAYMAN)
219CHIPSET(0x6701, CAYMAN_6701, CAYMAN)
220CHIPSET(0x6702, CAYMAN_6702, CAYMAN)
221CHIPSET(0x6703, CAYMAN_6703, CAYMAN)
222CHIPSET(0x6704, CAYMAN_6704, CAYMAN)
223CHIPSET(0x6705, CAYMAN_6705, CAYMAN)
224CHIPSET(0x6706, CAYMAN_6706, CAYMAN)
225CHIPSET(0x6707, CAYMAN_6707, CAYMAN)
226CHIPSET(0x6708, CAYMAN_6708, CAYMAN)
227CHIPSET(0x6709, CAYMAN_6709, CAYMAN)
228CHIPSET(0x6718, CAYMAN_6718, CAYMAN)
229CHIPSET(0x6719, CAYMAN_6719, CAYMAN)
230CHIPSET(0x671C, CAYMAN_671C, CAYMAN)
231CHIPSET(0x671D, CAYMAN_671D, CAYMAN)
232CHIPSET(0x671F, CAYMAN_671F, CAYMAN)
233
234CHIPSET(0x6720, BARTS_6720, BARTS)
235CHIPSET(0x6721, BARTS_6721, BARTS)
236CHIPSET(0x6722, BARTS_6722, BARTS)
237CHIPSET(0x6723, BARTS_6723, BARTS)
238CHIPSET(0x6724, BARTS_6724, BARTS)
239CHIPSET(0x6725, BARTS_6725, BARTS)
240CHIPSET(0x6726, BARTS_6726, BARTS)
241CHIPSET(0x6727, BARTS_6727, BARTS)
242CHIPSET(0x6728, BARTS_6728, BARTS)
243CHIPSET(0x6729, BARTS_6729, BARTS)
244CHIPSET(0x6738, BARTS_6738, BARTS)
245CHIPSET(0x6739, BARTS_6739, BARTS)
246CHIPSET(0x673E, BARTS_673E, BARTS)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]247
Jerome Glissec51f7f02011-12-09 21:07:15 -0500[diff] [blame]248CHIPSET(0x6740, TURKS_6740, TURKS)
249CHIPSET(0x6741, TURKS_6741, TURKS)
250CHIPSET(0x6742, TURKS_6742, TURKS)
251CHIPSET(0x6743, TURKS_6743, TURKS)
252CHIPSET(0x6744, TURKS_6744, TURKS)
253CHIPSET(0x6745, TURKS_6745, TURKS)
254CHIPSET(0x6746, TURKS_6746, TURKS)
255CHIPSET(0x6747, TURKS_6747, TURKS)
256CHIPSET(0x6748, TURKS_6748, TURKS)
257CHIPSET(0x6749, TURKS_6749, TURKS)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]258CHIPSET(0x674A, TURKS_674A, TURKS)
Jerome Glissec51f7f02011-12-09 21:07:15 -0500[diff] [blame]259CHIPSET(0x6750, TURKS_6750, TURKS)
Anisse Astiercf7cc622012-05-10 17:56:14 +0200[diff] [blame]260CHIPSET(0x6751, TURKS_6751, TURKS)
Jerome Glissec51f7f02011-12-09 21:07:15 -0500[diff] [blame]261CHIPSET(0x6758, TURKS_6758, TURKS)
262CHIPSET(0x6759, TURKS_6759, TURKS)
Anisse Astiercf7cc622012-05-10 17:56:14 +0200[diff] [blame]263CHIPSET(0x675B, TURKS_675B, TURKS)
264CHIPSET(0x675D, TURKS_675D, TURKS)
Jerome Glissec51f7f02011-12-09 21:07:15 -0500[diff] [blame]265CHIPSET(0x675F, TURKS_675F, TURKS)
266CHIPSET(0x6840, TURKS_6840, TURKS)
267CHIPSET(0x6841, TURKS_6841, TURKS)
268CHIPSET(0x6842, TURKS_6842, TURKS)
269CHIPSET(0x6843, TURKS_6843, TURKS)
270CHIPSET(0x6849, TURKS_6849, TURKS)
271CHIPSET(0x6850, TURKS_6850, TURKS)
272CHIPSET(0x6858, TURKS_6858, TURKS)
273CHIPSET(0x6859, TURKS_6859, TURKS)
274
275CHIPSET(0x6760, CAICOS_6760, CAICOS)
276CHIPSET(0x6761, CAICOS_6761, CAICOS)
277CHIPSET(0x6762, CAICOS_6762, CAICOS)
278CHIPSET(0x6763, CAICOS_6763, CAICOS)
279CHIPSET(0x6764, CAICOS_6764, CAICOS)
280CHIPSET(0x6765, CAICOS_6765, CAICOS)
281CHIPSET(0x6766, CAICOS_6766, CAICOS)
282CHIPSET(0x6767, CAICOS_6767, CAICOS)
283CHIPSET(0x6768, CAICOS_6768, CAICOS)
284CHIPSET(0x6770, CAICOS_6770, CAICOS)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]285CHIPSET(0x6771, CAICOS_6771, CAICOS)
Anisse Astiercf7cc622012-05-10 17:56:14 +0200[diff] [blame]286CHIPSET(0x6772, CAICOS_6772, CAICOS)
Jerome Glissec51f7f02011-12-09 21:07:15 -0500[diff] [blame]287CHIPSET(0x6778, CAICOS_6778, CAICOS)
288CHIPSET(0x6779, CAICOS_6779, CAICOS)
Anisse Astiercf7cc622012-05-10 17:56:14 +0200[diff] [blame]289CHIPSET(0x677B, CAICOS_677B, CAICOS)
Alex Deucherc50cc242012-02-14 11:32:17 -0500[diff] [blame]290
291CHIPSET(0x9900, ARUBA_9900, ARUBA)
292CHIPSET(0x9901, ARUBA_9901, ARUBA)
293CHIPSET(0x9903, ARUBA_9903, ARUBA)
294CHIPSET(0x9904, ARUBA_9904, ARUBA)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]295CHIPSET(0x9905, ARUBA_9905, ARUBA)
296CHIPSET(0x9906, ARUBA_9906, ARUBA)
297CHIPSET(0x9907, ARUBA_9907, ARUBA)
298CHIPSET(0x9908, ARUBA_9908, ARUBA)
299CHIPSET(0x9909, ARUBA_9909, ARUBA)
300CHIPSET(0x990A, ARUBA_990A, ARUBA)
Alex Deucherc50cc242012-02-14 11:32:17 -0500[diff] [blame]301CHIPSET(0x990F, ARUBA_990F, ARUBA)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]302CHIPSET(0x9910, ARUBA_9910, ARUBA)
303CHIPSET(0x9913, ARUBA_9913, ARUBA)
304CHIPSET(0x9917, ARUBA_9917, ARUBA)
305CHIPSET(0x9918, ARUBA_9918, ARUBA)
306CHIPSET(0x9919, ARUBA_9919, ARUBA)
Alex Deucherc50cc242012-02-14 11:32:17 -0500[diff] [blame]307CHIPSET(0x9990, ARUBA_9990, ARUBA)
308CHIPSET(0x9991, ARUBA_9991, ARUBA)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]309CHIPSET(0x9992, ARUBA_9992, ARUBA)
310CHIPSET(0x9993, ARUBA_9993, ARUBA)
311CHIPSET(0x9994, ARUBA_9994, ARUBA)
312CHIPSET(0x99A0, ARUBA_99A0, ARUBA)
313CHIPSET(0x99A2, ARUBA_99A2, ARUBA)
314CHIPSET(0x99A4, ARUBA_99A4, ARUBA)
Michel Dänzer481234f2012-05-16 18:49:18 +0200[diff] [blame]315
316CHIPSET(0x6780, TAHITI_6780, TAHITI)
317CHIPSET(0x6784, TAHITI_6784, TAHITI)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]318CHIPSET(0x6788, TAHITI_6788, TAHITI)
Michel Dänzer481234f2012-05-16 18:49:18 +0200[diff] [blame]319CHIPSET(0x678A, TAHITI_678A, TAHITI)
320CHIPSET(0x6790, TAHITI_6790, TAHITI)
Alex Deuchera4cb7232012-10-16 12:58:39 -0400[diff] [blame]321CHIPSET(0x6791, TAHITI_6791, TAHITI)
322CHIPSET(0x6792, TAHITI_6792, TAHITI)
Michel Dänzer481234f2012-05-16 18:49:18 +0200[diff] [blame]323CHIPSET(0x6798, TAHITI_6798, TAHITI)
324CHIPSET(0x6799, TAHITI_6799, TAHITI)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]325CHIPSET(0x679A, TAHITI_679A, TAHITI)
Alex Deucher171666e2012-11-21 18:45:14 -0500[diff] [blame]326CHIPSET(0x679B, TAHITI_679B, TAHITI)
Michel Dänzer481234f2012-05-16 18:49:18 +0200[diff] [blame]327CHIPSET(0x679E, TAHITI_679E, TAHITI)
328CHIPSET(0x679F, TAHITI_679F, TAHITI)
329
330CHIPSET(0x6800, PITCAIRN_6800, PITCAIRN)
331CHIPSET(0x6801, PITCAIRN_6801, PITCAIRN)
332CHIPSET(0x6802, PITCAIRN_6802, PITCAIRN)
Alex Deucher9f823ca2012-08-06 10:32:19 -0400[diff] [blame]333CHIPSET(0x6806, PITCAIRN_6806, PITCAIRN)
Michel Dänzer481234f2012-05-16 18:49:18 +0200[diff] [blame]334CHIPSET(0x6808, PITCAIRN_6808, PITCAIRN)
335CHIPSET(0x6809, PITCAIRN_6809, PITCAIRN)
336CHIPSET(0x6810, PITCAIRN_6810, PITCAIRN)
Alex Deuchera4cb7232012-10-16 12:58:39 -0400[diff] [blame]337CHIPSET(0x6811, PITCAIRN_6811, PITCAIRN)
Alex Deucher9f823ca2012-08-06 10:32:19 -0400[diff] [blame]338CHIPSET(0x6816, PITCAIRN_6816, PITCAIRN)
339CHIPSET(0x6817, PITCAIRN_6817, PITCAIRN)
Michel Dänzer481234f2012-05-16 18:49:18 +0200[diff] [blame]340CHIPSET(0x6818, PITCAIRN_6818, PITCAIRN)
341CHIPSET(0x6819, PITCAIRN_6819, PITCAIRN)
342CHIPSET(0x684C, PITCAIRN_684C, PITCAIRN)
343
344CHIPSET(0x6820, VERDE_6820, VERDE)
345CHIPSET(0x6821, VERDE_6821, VERDE)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]346CHIPSET(0x6823, VERDE_6823, VERDE)
Michel Dänzer481234f2012-05-16 18:49:18 +0200[diff] [blame]347CHIPSET(0x6824, VERDE_6824, VERDE)
348CHIPSET(0x6825, VERDE_6825, VERDE)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]349CHIPSET(0x6826, VERDE_6826, VERDE)
Michel Dänzer481234f2012-05-16 18:49:18 +0200[diff] [blame]350CHIPSET(0x6827, VERDE_6827, VERDE)
351CHIPSET(0x6828, VERDE_6828, VERDE)
352CHIPSET(0x6829, VERDE_6829, VERDE)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]353CHIPSET(0x682B, VERDE_682B, VERDE)
Michel Dänzer481234f2012-05-16 18:49:18 +0200[diff] [blame]354CHIPSET(0x682D, VERDE_682D, VERDE)
355CHIPSET(0x682F, VERDE_682F, VERDE)
356CHIPSET(0x6830, VERDE_6830, VERDE)
357CHIPSET(0x6831, VERDE_6831, VERDE)
Alex Deucherc563db02012-06-05 10:07:15 -0400[diff] [blame]358CHIPSET(0x6837, VERDE_6837, VERDE)
Michel Dänzer481234f2012-05-16 18:49:18 +0200[diff] [blame]359CHIPSET(0x6838, VERDE_6838, VERDE)
360CHIPSET(0x6839, VERDE_6839, VERDE)
361CHIPSET(0x683B, VERDE_683B, VERDE)
362CHIPSET(0x683D, VERDE_683D, VERDE)
363CHIPSET(0x683F, VERDE_683F, VERDE)
Alex Deucher353f0732013-01-24 17:53:37 -0500[diff] [blame^]364
365CHIPSET(0x6600, OLAND_6600, OLAND)
366CHIPSET(0x6601, OLAND_6601, OLAND)
367CHIPSET(0x6602, OLAND_6602, OLAND)
368CHIPSET(0x6603, OLAND_6603, OLAND)
369CHIPSET(0x6606, OLAND_6606, OLAND)
370CHIPSET(0x6607, OLAND_6607, OLAND)
371CHIPSET(0x6610, OLAND_6610, OLAND)
372CHIPSET(0x6611, OLAND_6611, OLAND)
373CHIPSET(0x6613, OLAND_6613, OLAND)
374CHIPSET(0x6620, OLAND_6620, OLAND)
375CHIPSET(0x6621, OLAND_6621, OLAND)
376CHIPSET(0x6623, OLAND_6623, OLAND)
377CHIPSET(0x6631, OLAND_6631, OLAND)