Eric Anholt | cbdd627 | 2009-01-27 17:16:11 -0800 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the |
| 8 | * "Software"), to deal in the Software without restriction, including |
| 9 | * without limitation the rights to use, copy, modify, merge, publish, |
| 10 | * distribute, sub license, and/or sell copies of the Software, and to |
| 11 | * permit persons to whom the Software is furnished to do so, subject to |
| 12 | * the following conditions: |
| 13 | * |
| 14 | * The above copyright notice and this permission notice (including the |
| 15 | * next paragraph) shall be included in all copies or substantial portions |
| 16 | * of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #ifndef _INTEL_CHIPSET_H |
| 29 | #define _INTEL_CHIPSET_H |
| 30 | |
Ben Widawsky | 36d1821 | 2012-12-03 17:43:29 -0800 | [diff] [blame] | 31 | #define PCI_CHIP_I810 0x7121 |
| 32 | #define PCI_CHIP_I810_DC100 0x7123 |
| 33 | #define PCI_CHIP_I810_E 0x7125 |
| 34 | #define PCI_CHIP_I815 0x1132 |
| 35 | |
| 36 | #define PCI_CHIP_I830_M 0x3577 |
| 37 | #define PCI_CHIP_845_G 0x2562 |
| 38 | #define PCI_CHIP_I855_GM 0x3582 |
| 39 | #define PCI_CHIP_I865_G 0x2572 |
| 40 | |
| 41 | #define PCI_CHIP_I915_G 0x2582 |
| 42 | #define PCI_CHIP_E7221_G 0x258A |
| 43 | #define PCI_CHIP_I915_GM 0x2592 |
| 44 | #define PCI_CHIP_I945_G 0x2772 |
| 45 | #define PCI_CHIP_I945_GM 0x27A2 |
| 46 | #define PCI_CHIP_I945_GME 0x27AE |
| 47 | |
| 48 | #define PCI_CHIP_Q35_G 0x29B2 |
| 49 | #define PCI_CHIP_G33_G 0x29C2 |
| 50 | #define PCI_CHIP_Q33_G 0x29D2 |
| 51 | |
| 52 | #define PCI_CHIP_IGD_GM 0xA011 |
| 53 | #define PCI_CHIP_IGD_G 0xA001 |
| 54 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 55 | #define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM) |
| 56 | #define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G) |
| 57 | #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) |
Ben Widawsky | 36d1821 | 2012-12-03 17:43:29 -0800 | [diff] [blame] | 58 | |
| 59 | #define PCI_CHIP_I965_G 0x29A2 |
| 60 | #define PCI_CHIP_I965_Q 0x2992 |
| 61 | #define PCI_CHIP_I965_G_1 0x2982 |
| 62 | #define PCI_CHIP_I946_GZ 0x2972 |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 63 | #define PCI_CHIP_I965_GM 0x2A02 |
| 64 | #define PCI_CHIP_I965_GME 0x2A12 |
Ben Widawsky | 36d1821 | 2012-12-03 17:43:29 -0800 | [diff] [blame] | 65 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 66 | #define PCI_CHIP_GM45_GM 0x2A42 |
Ben Widawsky | 36d1821 | 2012-12-03 17:43:29 -0800 | [diff] [blame] | 67 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 68 | #define PCI_CHIP_IGD_E_G 0x2E02 |
| 69 | #define PCI_CHIP_Q45_G 0x2E12 |
| 70 | #define PCI_CHIP_G45_G 0x2E22 |
| 71 | #define PCI_CHIP_G41_G 0x2E32 |
Ben Widawsky | 36d1821 | 2012-12-03 17:43:29 -0800 | [diff] [blame] | 72 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 73 | #define PCI_CHIP_ILD_G 0x0042 |
| 74 | #define PCI_CHIP_ILM_G 0x0046 |
Eric Anholt | 1d318e2 | 2011-12-20 13:03:37 -0800 | [diff] [blame] | 75 | |
| 76 | #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */ |
| 77 | #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 |
| 78 | #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 |
| 79 | #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */ |
| 80 | #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 |
| 81 | #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 |
| 82 | #define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */ |
| 83 | |
| 84 | #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */ |
| 85 | #define PCI_CHIP_IVYBRIDGE_GT2 0x0162 |
| 86 | #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */ |
| 87 | #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 |
| 88 | #define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */ |
Eugeni Dodonov | e057a56 | 2012-03-29 21:03:29 -0300 | [diff] [blame] | 89 | #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */ |
Eric Anholt | 1d318e2 | 2011-12-20 13:03:37 -0800 | [diff] [blame] | 90 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 91 | #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ |
| 92 | #define PCI_CHIP_HASWELL_GT2 0x0412 |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 93 | #define PCI_CHIP_HASWELL_GT3 0x0422 |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 94 | #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ |
| 95 | #define PCI_CHIP_HASWELL_M_GT2 0x0416 |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 96 | #define PCI_CHIP_HASWELL_M_GT3 0x0426 |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 97 | #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ |
| 98 | #define PCI_CHIP_HASWELL_S_GT2 0x041A |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 99 | #define PCI_CHIP_HASWELL_S_GT3 0x042A |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 100 | #define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */ |
| 101 | #define PCI_CHIP_HASWELL_B_GT2 0x041B |
| 102 | #define PCI_CHIP_HASWELL_B_GT3 0x042B |
| 103 | #define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */ |
| 104 | #define PCI_CHIP_HASWELL_E_GT2 0x041E |
| 105 | #define PCI_CHIP_HASWELL_E_GT3 0x042E |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 106 | #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ |
| 107 | #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 108 | #define PCI_CHIP_HASWELL_SDV_GT3 0x0C22 |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 109 | #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ |
| 110 | #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 111 | #define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26 |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 112 | #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ |
| 113 | #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 114 | #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 115 | #define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */ |
| 116 | #define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B |
| 117 | #define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B |
| 118 | #define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */ |
| 119 | #define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E |
| 120 | #define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 121 | #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ |
| 122 | #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 123 | #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 124 | #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ |
| 125 | #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 126 | #define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 127 | #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ |
| 128 | #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 129 | #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 130 | #define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */ |
| 131 | #define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B |
| 132 | #define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B |
| 133 | #define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */ |
| 134 | #define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E |
| 135 | #define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E |
Kenneth Graunke | ca678bc | 2013-03-01 15:37:01 -0800 | [diff] [blame] | 136 | #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ |
| 137 | #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 138 | #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 |
Kenneth Graunke | ca678bc | 2013-03-01 15:37:01 -0800 | [diff] [blame] | 139 | #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ |
| 140 | #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 141 | #define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 |
Kenneth Graunke | ca678bc | 2013-03-01 15:37:01 -0800 | [diff] [blame] | 142 | #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ |
| 143 | #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 144 | #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 145 | #define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */ |
| 146 | #define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B |
| 147 | #define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B |
| 148 | #define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */ |
| 149 | #define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E |
| 150 | #define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E |
Ben Widawsky | 6ea20a0 | 2012-12-04 13:56:14 -0800 | [diff] [blame] | 151 | #define BDW_SPARE 0x2 |
| 152 | #define BDW_ULT 0x6 |
| 153 | #define BDW_SERVER 0xa |
| 154 | #define BDW_IRIS 0xb |
| 155 | #define BDW_WORKSTATION 0xd |
| 156 | #define BDW_ULX 0xe |
Kenneth Graunke | 6172133 | 2012-03-19 13:55:19 -0700 | [diff] [blame] | 157 | |
Ben Widawsky | 36d1821 | 2012-12-03 17:43:29 -0800 | [diff] [blame] | 158 | #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */ |
Jesse Barnes | ef866c7 | 2013-02-02 11:10:24 +0100 | [diff] [blame] | 159 | #define PCI_CHIP_VALLEYVIEW_1 0x0f31 |
| 160 | #define PCI_CHIP_VALLEYVIEW_2 0x0f32 |
| 161 | #define PCI_CHIP_VALLEYVIEW_3 0x0f33 |
Jesse Barnes | 9d9cb85 | 2012-03-18 16:51:18 -0500 | [diff] [blame] | 162 | |
Ville Syrjälä | bb1f426 | 2013-02-13 23:05:45 +0200 | [diff] [blame] | 163 | #define PCI_CHIP_CHERRYVIEW_0 0x22b0 |
| 164 | #define PCI_CHIP_CHERRYVIEW_1 0x22b1 |
| 165 | #define PCI_CHIP_CHERRYVIEW_2 0x22b2 |
| 166 | #define PCI_CHIP_CHERRYVIEW_3 0x22b3 |
| 167 | |
Damien Lespiau | c19a986 | 2014-01-20 19:40:39 +0000 | [diff] [blame] | 168 | #define PCI_CHIP_SKYLAKE_DT_GT1 0x1902 |
Ben Widawsky | 4309bfd | 2015-10-22 12:06:59 -0700 | [diff] [blame] | 169 | #define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 |
| 170 | #define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */ |
Michał Winiarski | e3623d3 | 2016-02-17 11:40:19 +0100 | [diff] [blame] | 171 | #define PCI_CHIP_SKYLAKE_H_GT1 0x190B |
Ben Widawsky | 4309bfd | 2015-10-22 12:06:59 -0700 | [diff] [blame] | 172 | #define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */ |
| 173 | #define PCI_CHIP_SKYLAKE_DT_GT2 0x1912 |
| 174 | #define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */ |
| 175 | #define PCI_CHIP_SKYLAKE_FUSED1_GT2 0x1915 /* Reserved */ |
| 176 | #define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916 |
| 177 | #define PCI_CHIP_SKYLAKE_FUSED2_GT2 0x1917 /* Reserved */ |
| 178 | #define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A /* Reserved */ |
Damien Lespiau | c19a986 | 2014-01-20 19:40:39 +0000 | [diff] [blame] | 179 | #define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B |
Damien Lespiau | c19a986 | 2014-01-20 19:40:39 +0000 | [diff] [blame] | 180 | #define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D |
Ben Widawsky | 4309bfd | 2015-10-22 12:06:59 -0700 | [diff] [blame] | 181 | #define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E |
| 182 | #define PCI_CHIP_SKYLAKE_MOBILE_GT2 0x1921 /* Reserved */ |
Michał Winiarski | e3623d3 | 2016-02-17 11:40:19 +0100 | [diff] [blame] | 183 | #define PCI_CHIP_SKYLAKE_ULT_GT3_0 0x1923 |
| 184 | #define PCI_CHIP_SKYLAKE_ULT_GT3_1 0x1926 |
| 185 | #define PCI_CHIP_SKYLAKE_ULT_GT3_2 0x1927 |
Ben Widawsky | cad0e03 | 2015-10-22 12:15:50 -0700 | [diff] [blame] | 186 | #define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A |
Michał Winiarski | e3623d3 | 2016-02-17 11:40:19 +0100 | [diff] [blame] | 187 | #define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */ |
| 188 | #define PCI_CHIP_SKYLAKE_SRV_GT3 0x192D |
Ben Widawsky | cad0e03 | 2015-10-22 12:15:50 -0700 | [diff] [blame] | 189 | #define PCI_CHIP_SKYLAKE_DT_GT4 0x1932 |
| 190 | #define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A |
| 191 | #define PCI_CHIP_SKYLAKE_H_GT4 0x193B |
| 192 | #define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D |
Damien Lespiau | c19a986 | 2014-01-20 19:40:39 +0000 | [diff] [blame] | 193 | |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 194 | #define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 |
| 195 | #define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913 |
| 196 | #define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 |
Rodrigo Vivi | 22b6e33 | 2016-06-23 14:01:33 -0700 | [diff] [blame] | 197 | #define PCI_CHIP_KABYLAKE_ULT_GT3_0 0x5923 |
| 198 | #define PCI_CHIP_KABYLAKE_ULT_GT3_1 0x5926 |
| 199 | #define PCI_CHIP_KABYLAKE_ULT_GT3_2 0x5927 |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 200 | #define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 |
| 201 | #define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 |
| 202 | #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E |
| 203 | #define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E |
| 204 | #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 |
Anuj Phogat | 7c71188 | 2017-09-20 12:11:03 -0700 | [diff] [blame] | 205 | #define PCI_CHIP_KABYLAKE_M_GT2 0x5917 |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 206 | #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 207 | #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B |
| 208 | #define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B |
Rodrigo Vivi | 22b6e33 | 2016-06-23 14:01:33 -0700 | [diff] [blame] | 209 | #define PCI_CHIP_KABYLAKE_HALO_GT1_0 0x5908 |
| 210 | #define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 211 | #define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 212 | #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 213 | #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 214 | |
Damien Lespiau | e9ea1f4 | 2015-05-15 19:34:12 +0100 | [diff] [blame] | 215 | #define PCI_CHIP_BROXTON_0 0x0A84 |
| 216 | #define PCI_CHIP_BROXTON_1 0x1A84 |
| 217 | #define PCI_CHIP_BROXTON_2 0x5A84 |
Rodrigo Vivi | ea07de9 | 2016-03-01 17:07:04 -0800 | [diff] [blame] | 218 | #define PCI_CHIP_BROXTON_3 0x1A85 |
| 219 | #define PCI_CHIP_BROXTON_4 0x5A85 |
Damien Lespiau | e9ea1f4 | 2015-05-15 19:34:12 +0100 | [diff] [blame] | 220 | |
Ben Widawsky | 3e81f8b | 2016-11-10 10:28:02 -0800 | [diff] [blame] | 221 | #define PCI_CHIP_GLK 0x3184 |
| 222 | #define PCI_CHIP_GLK_2X6 0x3185 |
| 223 | |
Anusha Srivatsa | 0733f37 | 2017-06-21 11:17:35 -0700 | [diff] [blame] | 224 | #define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90 |
| 225 | #define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93 |
| 226 | #define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 |
| 227 | #define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 |
| 228 | #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 |
Anusha Srivatsa | 2b48faf | 2017-06-21 11:17:36 -0700 | [diff] [blame] | 229 | #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B |
| 230 | #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 |
Anusha Srivatsa | 4c98652 | 2017-06-21 11:17:37 -0700 | [diff] [blame] | 231 | #define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5 |
| 232 | #define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6 |
| 233 | #define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 |
| 234 | #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8 |
Anusha Srivatsa | 0733f37 | 2017-06-21 11:17:35 -0700 | [diff] [blame] | 235 | |
Rodrigo Vivi | 6b624bf | 2016-12-12 16:06:02 -0800 | [diff] [blame] | 236 | #define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52 |
| 237 | #define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A |
| 238 | #define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42 |
| 239 | #define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A |
Rodrigo Vivi | 80201d7 | 2016-12-12 16:06:03 -0800 | [diff] [blame] | 240 | #define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51 |
| 241 | #define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59 |
| 242 | #define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41 |
| 243 | #define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49 |
| 244 | #define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71 |
| 245 | #define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79 |
Rodrigo Vivi | 6b624bf | 2016-12-12 16:06:02 -0800 | [diff] [blame] | 246 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 247 | #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ |
| 248 | (devid) == PCI_CHIP_I915_GM || \ |
| 249 | (devid) == PCI_CHIP_I945_GM || \ |
| 250 | (devid) == PCI_CHIP_I945_GME || \ |
| 251 | (devid) == PCI_CHIP_I965_GM || \ |
| 252 | (devid) == PCI_CHIP_I965_GME || \ |
| 253 | (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \ |
| 254 | (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ |
| 255 | (devid) == PCI_CHIP_IVYBRIDGE_M_GT2) |
Eric Anholt | cbdd627 | 2009-01-27 17:16:11 -0800 | [diff] [blame] | 256 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 257 | #define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \ |
| 258 | (devid) == PCI_CHIP_Q45_G || \ |
| 259 | (devid) == PCI_CHIP_G45_G || \ |
| 260 | (devid) == PCI_CHIP_G41_G) |
| 261 | #define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM) |
Ben Widawsky | 36d1821 | 2012-12-03 17:43:29 -0800 | [diff] [blame] | 262 | #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) |
Eric Anholt | f6dc964 | 2009-10-22 16:37:56 -0700 | [diff] [blame] | 263 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 264 | #define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G) |
| 265 | #define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G) |
Eric Anholt | f6dc964 | 2009-10-22 16:37:56 -0700 | [diff] [blame] | 266 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 267 | #define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \ |
| 268 | (devid) == PCI_CHIP_E7221_G || \ |
| 269 | (devid) == PCI_CHIP_I915_GM) |
Eric Anholt | f6dc964 | 2009-10-22 16:37:56 -0700 | [diff] [blame] | 270 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 271 | #define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \ |
| 272 | (devid) == PCI_CHIP_I945_GME) |
Eric Anholt | f6dc964 | 2009-10-22 16:37:56 -0700 | [diff] [blame] | 273 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 274 | #define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \ |
| 275 | (devid) == PCI_CHIP_I945_GM || \ |
| 276 | (devid) == PCI_CHIP_I945_GME || \ |
Ben Widawsky | 36d1821 | 2012-12-03 17:43:29 -0800 | [diff] [blame] | 277 | IS_G33(devid)) |
Eric Anholt | f6dc964 | 2009-10-22 16:37:56 -0700 | [diff] [blame] | 278 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 279 | #define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \ |
| 280 | (devid) == PCI_CHIP_Q33_G || \ |
| 281 | (devid) == PCI_CHIP_Q35_G || IS_IGD(devid)) |
Eric Anholt | f6dc964 | 2009-10-22 16:37:56 -0700 | [diff] [blame] | 282 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 283 | #define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \ |
| 284 | (devid) == PCI_CHIP_845_G || \ |
| 285 | (devid) == PCI_CHIP_I855_GM || \ |
| 286 | (devid) == PCI_CHIP_I865_G) |
Eric Anholt | cbdd627 | 2009-01-27 17:16:11 -0800 | [diff] [blame] | 287 | |
Ben Widawsky | 36d1821 | 2012-12-03 17:43:29 -0800 | [diff] [blame] | 288 | #define IS_GEN3(devid) (IS_945(devid) || IS_915(devid)) |
Eric Anholt | cbdd627 | 2009-01-27 17:16:11 -0800 | [diff] [blame] | 289 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 290 | #define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \ |
| 291 | (devid) == PCI_CHIP_I965_Q || \ |
| 292 | (devid) == PCI_CHIP_I965_G_1 || \ |
| 293 | (devid) == PCI_CHIP_I965_GM || \ |
| 294 | (devid) == PCI_CHIP_I965_GME || \ |
| 295 | (devid) == PCI_CHIP_I946_GZ || \ |
Ben Widawsky | 36d1821 | 2012-12-03 17:43:29 -0800 | [diff] [blame] | 296 | IS_G4X(devid)) |
Jesse Barnes | 9d9cb85 | 2012-03-18 16:51:18 -0500 | [diff] [blame] | 297 | |
Ben Widawsky | 36d1821 | 2012-12-03 17:43:29 -0800 | [diff] [blame] | 298 | #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid)) |
Eric Anholt | f6dc964 | 2009-10-22 16:37:56 -0700 | [diff] [blame] | 299 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 300 | #define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \ |
| 301 | (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \ |
| 302 | (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \ |
| 303 | (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \ |
| 304 | (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \ |
| 305 | (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \ |
| 306 | (devid) == PCI_CHIP_SANDYBRIDGE_S) |
Eric Anholt | 1d318e2 | 2011-12-20 13:03:37 -0800 | [diff] [blame] | 307 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 308 | #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ |
Ville Syrjälä | 93d1259 | 2013-02-18 20:50:01 +0200 | [diff] [blame] | 309 | IS_HASWELL(devid) || \ |
| 310 | IS_VALLEYVIEW(devid)) |
Kenneth Graunke | 6172133 | 2012-03-19 13:55:19 -0700 | [diff] [blame] | 311 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 312 | #define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \ |
| 313 | (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \ |
| 314 | (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ |
| 315 | (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \ |
| 316 | (devid) == PCI_CHIP_IVYBRIDGE_S || \ |
Ville Syrjälä | 93d1259 | 2013-02-18 20:50:01 +0200 | [diff] [blame] | 317 | (devid) == PCI_CHIP_IVYBRIDGE_S_GT2) |
Ben Widawsky | 36d1821 | 2012-12-03 17:43:29 -0800 | [diff] [blame] | 318 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 319 | #define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \ |
| 320 | (devid) == PCI_CHIP_VALLEYVIEW_1 || \ |
| 321 | (devid) == PCI_CHIP_VALLEYVIEW_2 || \ |
| 322 | (devid) == PCI_CHIP_VALLEYVIEW_3) |
Kenneth Graunke | 6172133 | 2012-03-19 13:55:19 -0700 | [diff] [blame] | 323 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 324 | #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ |
| 325 | (devid) == PCI_CHIP_HASWELL_M_GT1 || \ |
| 326 | (devid) == PCI_CHIP_HASWELL_S_GT1 || \ |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 327 | (devid) == PCI_CHIP_HASWELL_B_GT1 || \ |
| 328 | (devid) == PCI_CHIP_HASWELL_E_GT1 || \ |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 329 | (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \ |
| 330 | (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \ |
| 331 | (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \ |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 332 | (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \ |
| 333 | (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \ |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 334 | (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \ |
| 335 | (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \ |
| 336 | (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \ |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 337 | (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \ |
| 338 | (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \ |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 339 | (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \ |
| 340 | (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \ |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 341 | (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \ |
| 342 | (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \ |
| 343 | (devid) == PCI_CHIP_HASWELL_CRW_E_GT1) |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 344 | #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \ |
| 345 | (devid) == PCI_CHIP_HASWELL_M_GT2 || \ |
| 346 | (devid) == PCI_CHIP_HASWELL_S_GT2 || \ |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 347 | (devid) == PCI_CHIP_HASWELL_B_GT2 || \ |
| 348 | (devid) == PCI_CHIP_HASWELL_E_GT2 || \ |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 349 | (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \ |
| 350 | (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \ |
| 351 | (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \ |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 352 | (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \ |
| 353 | (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \ |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 354 | (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \ |
| 355 | (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \ |
| 356 | (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \ |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 357 | (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \ |
| 358 | (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \ |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 359 | (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \ |
| 360 | (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \ |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 361 | (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \ |
| 362 | (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \ |
| 363 | (devid) == PCI_CHIP_HASWELL_CRW_E_GT2) |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 364 | #define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \ |
| 365 | (devid) == PCI_CHIP_HASWELL_M_GT3 || \ |
| 366 | (devid) == PCI_CHIP_HASWELL_S_GT3 || \ |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 367 | (devid) == PCI_CHIP_HASWELL_B_GT3 || \ |
| 368 | (devid) == PCI_CHIP_HASWELL_E_GT3 || \ |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 369 | (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \ |
| 370 | (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \ |
| 371 | (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \ |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 372 | (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \ |
| 373 | (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \ |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 374 | (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \ |
| 375 | (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \ |
| 376 | (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \ |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 377 | (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \ |
| 378 | (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \ |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 379 | (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \ |
| 380 | (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \ |
Rodrigo Vivi | 1669a67 | 2013-05-13 17:48:40 -0300 | [diff] [blame] | 381 | (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \ |
| 382 | (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \ |
| 383 | (devid) == PCI_CHIP_HASWELL_CRW_E_GT3) |
Kenneth Graunke | 6172133 | 2012-03-19 13:55:19 -0700 | [diff] [blame] | 384 | |
Ville Syrjälä | 6e55fd7 | 2013-02-18 20:22:21 +0200 | [diff] [blame] | 385 | #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ |
Rodrigo Vivi | 150c355 | 2013-05-13 17:48:39 -0300 | [diff] [blame] | 386 | IS_HSW_GT2(devid) || \ |
| 387 | IS_HSW_GT3(devid)) |
Eric Anholt | 1d318e2 | 2011-12-20 13:03:37 -0800 | [diff] [blame] | 388 | |
Ben Widawsky | 6ea20a0 | 2012-12-04 13:56:14 -0800 | [diff] [blame] | 389 | #define IS_BROADWELL(devid) (((devid & 0xff00) != 0x1600) ? 0 : \ |
| 390 | (((devid & 0x00f0) >> 4) > 3) ? 0 : \ |
| 391 | ((devid & 0x000f) == BDW_SPARE) ? 1 : \ |
| 392 | ((devid & 0x000f) == BDW_ULT) ? 1 : \ |
| 393 | ((devid & 0x000f) == BDW_IRIS) ? 1 : \ |
| 394 | ((devid & 0x000f) == BDW_SERVER) ? 1 : \ |
| 395 | ((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \ |
| 396 | ((devid & 0x000f) == BDW_ULX) ? 1 : 0) |
| 397 | |
Ville Syrjälä | bb1f426 | 2013-02-13 23:05:45 +0200 | [diff] [blame] | 398 | #define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \ |
| 399 | (devid) == PCI_CHIP_CHERRYVIEW_1 || \ |
| 400 | (devid) == PCI_CHIP_CHERRYVIEW_2 || \ |
| 401 | (devid) == PCI_CHIP_CHERRYVIEW_3) |
Ben Widawsky | 6ea20a0 | 2012-12-04 13:56:14 -0800 | [diff] [blame] | 402 | |
Ville Syrjälä | bb1f426 | 2013-02-13 23:05:45 +0200 | [diff] [blame] | 403 | #define IS_GEN8(devid) (IS_BROADWELL(devid) || \ |
| 404 | IS_CHERRYVIEW(devid)) |
Ben Widawsky | 6ea20a0 | 2012-12-04 13:56:14 -0800 | [diff] [blame] | 405 | |
Michał Winiarski | e3623d3 | 2016-02-17 11:40:19 +0100 | [diff] [blame] | 406 | #define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ |
| 407 | (devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \ |
| 408 | (devid) == PCI_CHIP_SKYLAKE_SRV_GT1 || \ |
| 409 | (devid) == PCI_CHIP_SKYLAKE_H_GT1 || \ |
| 410 | (devid) == PCI_CHIP_SKYLAKE_ULX_GT1) |
Damien Lespiau | c19a986 | 2014-01-20 19:40:39 +0000 | [diff] [blame] | 411 | |
Ben Widawsky | 4309bfd | 2015-10-22 12:06:59 -0700 | [diff] [blame] | 412 | #define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \ |
| 413 | (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \ |
| 414 | (devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2 || \ |
| 415 | (devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \ |
| 416 | (devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2 || \ |
Damien Lespiau | c19a986 | 2014-01-20 19:40:39 +0000 | [diff] [blame] | 417 | (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \ |
Ben Widawsky | 4309bfd | 2015-10-22 12:06:59 -0700 | [diff] [blame] | 418 | (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \ |
| 419 | (devid) == PCI_CHIP_SKYLAKE_WKS_GT2 || \ |
| 420 | (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \ |
| 421 | (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2) |
Damien Lespiau | c19a986 | 2014-01-20 19:40:39 +0000 | [diff] [blame] | 422 | |
Michał Winiarski | e3623d3 | 2016-02-17 11:40:19 +0100 | [diff] [blame] | 423 | #define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0 || \ |
| 424 | (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1 || \ |
| 425 | (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2 || \ |
| 426 | (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \ |
| 427 | (devid) == PCI_CHIP_SKYLAKE_SRV_GT3) |
Ben Widawsky | cad0e03 | 2015-10-22 12:15:50 -0700 | [diff] [blame] | 428 | |
| 429 | #define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4 || \ |
| 430 | (devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \ |
| 431 | (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \ |
| 432 | (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ |
| 433 | (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) |
Damien Lespiau | c19a986 | 2014-01-20 19:40:39 +0000 | [diff] [blame] | 434 | |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 435 | #define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ |
| 436 | (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 437 | (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ |
| 438 | (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ |
| 439 | (devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \ |
Rodrigo Vivi | 22b6e33 | 2016-06-23 14:01:33 -0700 | [diff] [blame] | 440 | (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0 || \ |
| 441 | (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1 || \ |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 442 | (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) |
| 443 | |
| 444 | #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ |
| 445 | (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ |
| 446 | (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ |
| 447 | (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ |
Anuj Phogat | 7c71188 | 2017-09-20 12:11:03 -0700 | [diff] [blame] | 448 | (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 449 | (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ |
| 450 | (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ |
| 451 | (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) |
| 452 | |
Rodrigo Vivi | 22b6e33 | 2016-06-23 14:01:33 -0700 | [diff] [blame] | 453 | #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ |
| 454 | (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ |
Rodrigo Vivi | 7996a87 | 2016-06-27 17:02:34 -0700 | [diff] [blame] | 455 | (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2) |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 456 | |
Rodrigo Vivi | 7996a87 | 2016-06-27 17:02:34 -0700 | [diff] [blame] | 457 | #define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) |
Rodrigo Vivi | 242f77c | 2015-09-18 11:26:39 -0700 | [diff] [blame] | 458 | |
| 459 | #define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ |
| 460 | IS_KBL_GT2(devid) || \ |
| 461 | IS_KBL_GT3(devid) || \ |
| 462 | IS_KBL_GT4(devid)) |
| 463 | |
Damien Lespiau | c19a986 | 2014-01-20 19:40:39 +0000 | [diff] [blame] | 464 | #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ |
| 465 | IS_SKL_GT2(devid) || \ |
Ben Widawsky | cad0e03 | 2015-10-22 12:15:50 -0700 | [diff] [blame] | 466 | IS_SKL_GT3(devid) || \ |
| 467 | IS_SKL_GT4(devid)) |
Damien Lespiau | c19a986 | 2014-01-20 19:40:39 +0000 | [diff] [blame] | 468 | |
Damien Lespiau | e9ea1f4 | 2015-05-15 19:34:12 +0100 | [diff] [blame] | 469 | #define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \ |
| 470 | (devid) == PCI_CHIP_BROXTON_1 || \ |
Rodrigo Vivi | ea07de9 | 2016-03-01 17:07:04 -0800 | [diff] [blame] | 471 | (devid) == PCI_CHIP_BROXTON_2 || \ |
| 472 | (devid) == PCI_CHIP_BROXTON_3 || \ |
| 473 | (devid) == PCI_CHIP_BROXTON_4) |
Damien Lespiau | e9ea1f4 | 2015-05-15 19:34:12 +0100 | [diff] [blame] | 474 | |
Ben Widawsky | 3e81f8b | 2016-11-10 10:28:02 -0800 | [diff] [blame] | 475 | #define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \ |
| 476 | (devid) == PCI_CHIP_GLK_2X6) |
| 477 | |
Anusha Srivatsa | 0733f37 | 2017-06-21 11:17:35 -0700 | [diff] [blame] | 478 | #define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \ |
| 479 | (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \ |
| 480 | (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \ |
| 481 | (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \ |
| 482 | (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3) |
| 483 | |
Anusha Srivatsa | 2b48faf | 2017-06-21 11:17:36 -0700 | [diff] [blame] | 484 | #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ |
| 485 | (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) |
| 486 | |
Anusha Srivatsa | 4c98652 | 2017-06-21 11:17:37 -0700 | [diff] [blame] | 487 | #define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ |
| 488 | (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ |
| 489 | (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ |
| 490 | (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4) |
| 491 | |
Anusha Srivatsa | 2b48faf | 2017-06-21 11:17:36 -0700 | [diff] [blame] | 492 | #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ |
Anusha Srivatsa | 4c98652 | 2017-06-21 11:17:37 -0700 | [diff] [blame] | 493 | IS_CFL_H(devid) || \ |
| 494 | IS_CFL_U(devid)) |
Anusha Srivatsa | 0733f37 | 2017-06-21 11:17:35 -0700 | [diff] [blame] | 495 | |
Ben Widawsky | 3e81f8b | 2016-11-10 10:28:02 -0800 | [diff] [blame] | 496 | #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ |
| 497 | IS_BROXTON(devid) || \ |
| 498 | IS_KABYLAKE(devid) || \ |
Anusha Srivatsa | 0733f37 | 2017-06-21 11:17:35 -0700 | [diff] [blame] | 499 | IS_GEMINILAKE(devid) || \ |
| 500 | IS_COFFEELAKE(devid)) |
Damien Lespiau | c19a986 | 2014-01-20 19:40:39 +0000 | [diff] [blame] | 501 | |
Rodrigo Vivi | 80201d7 | 2016-12-12 16:06:03 -0800 | [diff] [blame] | 502 | #define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \ |
| 503 | (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \ |
| 504 | (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \ |
| 505 | (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \ |
| 506 | (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \ |
| 507 | (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5) |
| 508 | |
Rodrigo Vivi | 6b624bf | 2016-12-12 16:06:02 -0800 | [diff] [blame] | 509 | #define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \ |
| 510 | (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \ |
| 511 | (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \ |
| 512 | (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3) |
| 513 | |
Rodrigo Vivi | 80201d7 | 2016-12-12 16:06:03 -0800 | [diff] [blame] | 514 | #define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \ |
| 515 | IS_CNL_Y(devid)) |
Rodrigo Vivi | 6b624bf | 2016-12-12 16:06:02 -0800 | [diff] [blame] | 516 | |
| 517 | #define IS_GEN10(devid) (IS_CANNONLAKE(devid)) |
Eric Anholt | cbdd627 | 2009-01-27 17:16:11 -0800 | [diff] [blame] | 518 | |
Rodrigo Vivi | 68da781 | 2017-06-30 14:24:55 -0700 | [diff] [blame] | 519 | #define IS_9XX(dev) (IS_GEN3(dev) || \ |
| 520 | IS_GEN4(dev) || \ |
| 521 | IS_GEN5(dev) || \ |
| 522 | IS_GEN6(dev) || \ |
| 523 | IS_GEN7(dev) || \ |
| 524 | IS_GEN8(dev) || \ |
| 525 | IS_GEN9(dev) || \ |
| 526 | IS_GEN10(dev)) |
| 527 | |
Eric Anholt | cbdd627 | 2009-01-27 17:16:11 -0800 | [diff] [blame] | 528 | #endif /* _INTEL_CHIPSET_H */ |