Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
| 2 | * |
| 3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. |
| 4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. |
| 5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 6 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 7 | * |
| 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 9 | * copy of this software and associated documentation files (the "Software"), |
| 10 | * to deal in the Software without restriction, including without limitation |
| 11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 12 | * and/or sell copies of the Software, and to permit persons to whom the |
| 13 | * Software is furnished to do so, subject to the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice shall be included in |
| 16 | * all copies or substantial portions of the Software. |
| 17 | * |
| 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 24 | * OTHER DEALINGS IN THE SOFTWARE. |
| 25 | * |
| 26 | * Authors: |
| 27 | * Kevin E. Martin <martin@valinux.com> |
| 28 | * Gareth Hughes <gareth@valinux.com> |
| 29 | * Keith Whitwell <keith@tungstengraphics.com> |
| 30 | */ |
| 31 | |
| 32 | #ifndef __AMDGPU_DRM_H__ |
| 33 | #define __AMDGPU_DRM_H__ |
| 34 | |
Alexandr Akulich | 399ac8b | 2015-07-17 01:19:12 +0500 | [diff] [blame] | 35 | #include "drm.h" |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 36 | |
Marek Olšák | 77bc69a | 2016-08-19 16:10:58 +0200 | [diff] [blame] | 37 | #if defined(__cplusplus) |
| 38 | extern "C" { |
| 39 | #endif |
| 40 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 41 | #define DRM_AMDGPU_GEM_CREATE 0x00 |
| 42 | #define DRM_AMDGPU_GEM_MMAP 0x01 |
| 43 | #define DRM_AMDGPU_CTX 0x02 |
| 44 | #define DRM_AMDGPU_BO_LIST 0x03 |
| 45 | #define DRM_AMDGPU_CS 0x04 |
| 46 | #define DRM_AMDGPU_INFO 0x05 |
| 47 | #define DRM_AMDGPU_GEM_METADATA 0x06 |
| 48 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 |
| 49 | #define DRM_AMDGPU_GEM_VA 0x08 |
| 50 | #define DRM_AMDGPU_WAIT_CS 0x09 |
| 51 | #define DRM_AMDGPU_GEM_OP 0x10 |
| 52 | #define DRM_AMDGPU_GEM_USERPTR 0x11 |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 53 | #define DRM_AMDGPU_WAIT_FENCES 0x12 |
Dave Airlie | 92b5b30 | 2017-06-27 12:56:25 +1000 | [diff] [blame] | 54 | #define DRM_AMDGPU_VM 0x13 |
Marek Olšák | ad4df73 | 2017-10-12 20:31:44 +0200 | [diff] [blame] | 55 | #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 |
Andres Rodriguez | bcae722 | 2017-10-20 10:57:58 -0400 | [diff] [blame] | 56 | #define DRM_AMDGPU_SCHED 0x15 |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 57 | |
| 58 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) |
| 59 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) |
| 60 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) |
| 61 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) |
| 62 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) |
| 63 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) |
| 64 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) |
| 65 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) |
Christian König | 933091e | 2015-06-08 15:05:07 +0200 | [diff] [blame] | 66 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 67 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
| 68 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) |
| 69 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 70 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) |
Dave Airlie | 92b5b30 | 2017-06-27 12:56:25 +1000 | [diff] [blame] | 71 | #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) |
Marek Olšák | ad4df73 | 2017-10-12 20:31:44 +0200 | [diff] [blame] | 72 | #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) |
Andres Rodriguez | bcae722 | 2017-10-20 10:57:58 -0400 | [diff] [blame] | 73 | #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 74 | |
| 75 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 |
| 76 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 |
| 77 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 |
| 78 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 |
| 79 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 |
| 80 | #define AMDGPU_GEM_DOMAIN_OA 0x20 |
| 81 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 82 | /* Flag that CPU access will be required for the case of VRAM domain */ |
| 83 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) |
| 84 | /* Flag that CPU access will not work, this VRAM domain is invisible */ |
| 85 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 86 | /* Flag that USWC attributes should be used for GTT */ |
Jammy Zhou | a4c8321 | 2015-05-06 18:45:57 +0800 | [diff] [blame] | 87 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
Flora Cui | 4462303 | 2016-07-22 11:56:52 +0800 | [diff] [blame] | 88 | /* Flag that the memory should be in VRAM and cleared */ |
| 89 | #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 90 | /* Flag that create shadow bo(GTT) while allocating vram bo */ |
| 91 | #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) |
| 92 | /* Flag that allocating the BO should use linear VRAM */ |
| 93 | #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) |
Marek Olšák | ad4df73 | 2017-10-12 20:31:44 +0200 | [diff] [blame] | 94 | /* Flag that BO is always valid in this VM */ |
| 95 | #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) |
Andres Rodriguez | bcae722 | 2017-10-20 10:57:58 -0400 | [diff] [blame] | 96 | /* Flag that BO sharing will be explicitly synchronized */ |
| 97 | #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 98 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 99 | struct drm_amdgpu_gem_create_in { |
| 100 | /** the requested memory size */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 101 | __u64 bo_size; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 102 | /** physical start_addr alignment in bytes for some HW requirements */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 103 | __u64 alignment; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 104 | /** the requested memory domains */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 105 | __u64 domains; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 106 | /** allocation flags */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 107 | __u64 domain_flags; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 108 | }; |
| 109 | |
| 110 | struct drm_amdgpu_gem_create_out { |
| 111 | /** returned GEM object handle */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 112 | __u32 handle; |
| 113 | __u32 _pad; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 114 | }; |
| 115 | |
| 116 | union drm_amdgpu_gem_create { |
| 117 | struct drm_amdgpu_gem_create_in in; |
| 118 | struct drm_amdgpu_gem_create_out out; |
| 119 | }; |
| 120 | |
| 121 | /** Opcode to create new residency list. */ |
| 122 | #define AMDGPU_BO_LIST_OP_CREATE 0 |
| 123 | /** Opcode to destroy previously created residency list */ |
| 124 | #define AMDGPU_BO_LIST_OP_DESTROY 1 |
| 125 | /** Opcode to update resource information in the list */ |
| 126 | #define AMDGPU_BO_LIST_OP_UPDATE 2 |
| 127 | |
| 128 | struct drm_amdgpu_bo_list_in { |
| 129 | /** Type of operation */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 130 | __u32 operation; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 131 | /** Handle of list or 0 if we want to create one */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 132 | __u32 list_handle; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 133 | /** Number of BOs in list */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 134 | __u32 bo_number; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 135 | /** Size of each element describing BO */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 136 | __u32 bo_info_size; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 137 | /** Pointer to array describing BOs */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 138 | __u64 bo_info_ptr; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 139 | }; |
| 140 | |
| 141 | struct drm_amdgpu_bo_list_entry { |
| 142 | /** Handle of BO */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 143 | __u32 bo_handle; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 144 | /** New (if specified) BO priority to be used during migration */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 145 | __u32 bo_priority; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 146 | }; |
| 147 | |
| 148 | struct drm_amdgpu_bo_list_out { |
| 149 | /** Handle of resource list */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 150 | __u32 list_handle; |
| 151 | __u32 _pad; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 152 | }; |
| 153 | |
| 154 | union drm_amdgpu_bo_list { |
| 155 | struct drm_amdgpu_bo_list_in in; |
| 156 | struct drm_amdgpu_bo_list_out out; |
| 157 | }; |
| 158 | |
| 159 | /* context related */ |
| 160 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 |
| 161 | #define AMDGPU_CTX_OP_FREE_CTX 2 |
| 162 | #define AMDGPU_CTX_OP_QUERY_STATE 3 |
Daniel Stone | 8e535dd | 2018-03-30 13:04:30 +0100 | [diff] [blame] | 163 | #define AMDGPU_CTX_OP_QUERY_STATE2 4 |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 164 | |
Marek Olšák | 4b39a8e | 2015-05-05 21:23:02 +0200 | [diff] [blame] | 165 | /* GPU reset status */ |
| 166 | #define AMDGPU_CTX_NO_RESET 0 |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 167 | /* this the context caused it */ |
| 168 | #define AMDGPU_CTX_GUILTY_RESET 1 |
| 169 | /* some other context caused it */ |
| 170 | #define AMDGPU_CTX_INNOCENT_RESET 2 |
| 171 | /* unknown cause */ |
| 172 | #define AMDGPU_CTX_UNKNOWN_RESET 3 |
Marek Olšák | 4b39a8e | 2015-05-05 21:23:02 +0200 | [diff] [blame] | 173 | |
Daniel Stone | 8e535dd | 2018-03-30 13:04:30 +0100 | [diff] [blame] | 174 | /* indicate gpu reset occured after ctx created */ |
| 175 | #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) |
| 176 | /* indicate vram lost occured after ctx created */ |
| 177 | #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) |
| 178 | /* indicate some job from this context once cause gpu hang */ |
| 179 | #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) |
| 180 | |
Andres Rodriguez | bcae722 | 2017-10-20 10:57:58 -0400 | [diff] [blame] | 181 | /* Context priority level */ |
| 182 | #define AMDGPU_CTX_PRIORITY_UNSET -2048 |
| 183 | #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 |
| 184 | #define AMDGPU_CTX_PRIORITY_LOW -512 |
| 185 | #define AMDGPU_CTX_PRIORITY_NORMAL 0 |
| 186 | /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */ |
| 187 | #define AMDGPU_CTX_PRIORITY_HIGH 512 |
| 188 | #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 |
| 189 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 190 | struct drm_amdgpu_ctx_in { |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 191 | /** AMDGPU_CTX_OP_* */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 192 | __u32 op; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 193 | /** For future use, no flags defined so far */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 194 | __u32 flags; |
| 195 | __u32 ctx_id; |
Andres Rodriguez | bcae722 | 2017-10-20 10:57:58 -0400 | [diff] [blame] | 196 | __s32 priority; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 197 | }; |
| 198 | |
| 199 | union drm_amdgpu_ctx_out { |
| 200 | struct { |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 201 | __u32 ctx_id; |
| 202 | __u32 _pad; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 203 | } alloc; |
| 204 | |
| 205 | struct { |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 206 | /** For future use, no flags defined so far */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 207 | __u64 flags; |
Marek Olšák | 4b39a8e | 2015-05-05 21:23:02 +0200 | [diff] [blame] | 208 | /** Number of resets caused by this context so far. */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 209 | __u32 hangs; |
Marek Olšák | 4b39a8e | 2015-05-05 21:23:02 +0200 | [diff] [blame] | 210 | /** Reset status since the last call of the ioctl. */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 211 | __u32 reset_status; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 212 | } state; |
| 213 | }; |
| 214 | |
| 215 | union drm_amdgpu_ctx { |
| 216 | struct drm_amdgpu_ctx_in in; |
| 217 | union drm_amdgpu_ctx_out out; |
| 218 | }; |
| 219 | |
Dave Airlie | 92b5b30 | 2017-06-27 12:56:25 +1000 | [diff] [blame] | 220 | /* vm ioctl */ |
| 221 | #define AMDGPU_VM_OP_RESERVE_VMID 1 |
| 222 | #define AMDGPU_VM_OP_UNRESERVE_VMID 2 |
| 223 | |
| 224 | struct drm_amdgpu_vm_in { |
| 225 | /** AMDGPU_VM_OP_* */ |
| 226 | __u32 op; |
| 227 | __u32 flags; |
| 228 | }; |
| 229 | |
| 230 | struct drm_amdgpu_vm_out { |
| 231 | /** For future use, no flags defined so far */ |
| 232 | __u64 flags; |
| 233 | }; |
| 234 | |
| 235 | union drm_amdgpu_vm { |
| 236 | struct drm_amdgpu_vm_in in; |
| 237 | struct drm_amdgpu_vm_out out; |
| 238 | }; |
| 239 | |
Andres Rodriguez | bcae722 | 2017-10-20 10:57:58 -0400 | [diff] [blame] | 240 | /* sched ioctl */ |
| 241 | #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 |
| 242 | |
| 243 | struct drm_amdgpu_sched_in { |
| 244 | /* AMDGPU_SCHED_OP_* */ |
| 245 | __u32 op; |
| 246 | __u32 fd; |
| 247 | __s32 priority; |
| 248 | __u32 flags; |
| 249 | }; |
| 250 | |
| 251 | union drm_amdgpu_sched { |
| 252 | struct drm_amdgpu_sched_in in; |
| 253 | }; |
| 254 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 255 | /* |
| 256 | * This is not a reliable API and you should expect it to fail for any |
| 257 | * number of reasons and have fallback path that do not use userptr to |
| 258 | * perform any operation. |
| 259 | */ |
| 260 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) |
| 261 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) |
| 262 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) |
| 263 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) |
| 264 | |
| 265 | struct drm_amdgpu_gem_userptr { |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 266 | __u64 addr; |
| 267 | __u64 size; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 268 | /* AMDGPU_GEM_USERPTR_* */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 269 | __u32 flags; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 270 | /* Resulting GEM handle */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 271 | __u32 handle; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 272 | }; |
| 273 | |
Marek Olšák | c34b28a | 2017-03-21 20:14:45 +0100 | [diff] [blame] | 274 | /* SI-CI-VI: */ |
Marek Olšák | 7c50f0d | 2015-05-15 00:16:41 +0200 | [diff] [blame] | 275 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
| 276 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 |
| 277 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf |
| 278 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 |
| 279 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f |
| 280 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 |
| 281 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 |
| 282 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 |
| 283 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 |
| 284 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 |
| 285 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 |
| 286 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 |
| 287 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 |
| 288 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 |
| 289 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 |
| 290 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 |
| 291 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 |
| 292 | |
Marek Olšák | c34b28a | 2017-03-21 20:14:45 +0100 | [diff] [blame] | 293 | /* GFX9 and later: */ |
| 294 | #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 |
| 295 | #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f |
| 296 | |
Nicolai Hähnle | f104148 | 2017-04-03 10:22:59 +0200 | [diff] [blame] | 297 | /* Set/Get helpers for tiling flags. */ |
Marek Olšák | 7c50f0d | 2015-05-15 00:16:41 +0200 | [diff] [blame] | 298 | #define AMDGPU_TILING_SET(field, value) \ |
Marek Olšák | c34b28a | 2017-03-21 20:14:45 +0100 | [diff] [blame] | 299 | (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) |
Marek Olšák | 7c50f0d | 2015-05-15 00:16:41 +0200 | [diff] [blame] | 300 | #define AMDGPU_TILING_GET(value, field) \ |
Marek Olšák | c34b28a | 2017-03-21 20:14:45 +0100 | [diff] [blame] | 301 | (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 302 | |
| 303 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 |
| 304 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 |
| 305 | |
| 306 | /** The same structure is shared for input/output */ |
| 307 | struct drm_amdgpu_gem_metadata { |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 308 | /** GEM Object handle */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 309 | __u32 handle; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 310 | /** Do we want get or set metadata */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 311 | __u32 op; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 312 | struct { |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 313 | /** For future use, no flags defined so far */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 314 | __u64 flags; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 315 | /** family specific tiling info */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 316 | __u64 tiling_info; |
| 317 | __u32 data_size_bytes; |
| 318 | __u32 data[64]; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 319 | } data; |
| 320 | }; |
| 321 | |
| 322 | struct drm_amdgpu_gem_mmap_in { |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 323 | /** the GEM object handle */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 324 | __u32 handle; |
| 325 | __u32 _pad; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 326 | }; |
| 327 | |
| 328 | struct drm_amdgpu_gem_mmap_out { |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 329 | /** mmap offset from the vma offset manager */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 330 | __u64 addr_ptr; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 331 | }; |
| 332 | |
| 333 | union drm_amdgpu_gem_mmap { |
| 334 | struct drm_amdgpu_gem_mmap_in in; |
| 335 | struct drm_amdgpu_gem_mmap_out out; |
| 336 | }; |
| 337 | |
| 338 | struct drm_amdgpu_gem_wait_idle_in { |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 339 | /** GEM object handle */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 340 | __u32 handle; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 341 | /** For future use, no flags defined so far */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 342 | __u32 flags; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 343 | /** Absolute timeout to wait */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 344 | __u64 timeout; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 345 | }; |
| 346 | |
| 347 | struct drm_amdgpu_gem_wait_idle_out { |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 348 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 349 | __u32 status; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 350 | /** Returned current memory domain */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 351 | __u32 domain; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 352 | }; |
| 353 | |
| 354 | union drm_amdgpu_gem_wait_idle { |
| 355 | struct drm_amdgpu_gem_wait_idle_in in; |
| 356 | struct drm_amdgpu_gem_wait_idle_out out; |
| 357 | }; |
| 358 | |
| 359 | struct drm_amdgpu_wait_cs_in { |
Dave Airlie | 92b5b30 | 2017-06-27 12:56:25 +1000 | [diff] [blame] | 360 | /* Command submission handle |
| 361 | * handle equals 0 means none to wait for |
| 362 | * handle equals ~0ull means wait for the latest sequence number |
| 363 | */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 364 | __u64 handle; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 365 | /** Absolute timeout to wait */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 366 | __u64 timeout; |
| 367 | __u32 ip_type; |
| 368 | __u32 ip_instance; |
| 369 | __u32 ring; |
| 370 | __u32 ctx_id; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 371 | }; |
| 372 | |
| 373 | struct drm_amdgpu_wait_cs_out { |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 374 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 375 | __u64 status; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 376 | }; |
| 377 | |
| 378 | union drm_amdgpu_wait_cs { |
| 379 | struct drm_amdgpu_wait_cs_in in; |
| 380 | struct drm_amdgpu_wait_cs_out out; |
| 381 | }; |
| 382 | |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 383 | struct drm_amdgpu_fence { |
| 384 | __u32 ctx_id; |
| 385 | __u32 ip_type; |
| 386 | __u32 ip_instance; |
| 387 | __u32 ring; |
| 388 | __u64 seq_no; |
| 389 | }; |
| 390 | |
| 391 | struct drm_amdgpu_wait_fences_in { |
| 392 | /** This points to uint64_t * which points to fences */ |
| 393 | __u64 fences; |
| 394 | __u32 fence_count; |
| 395 | __u32 wait_all; |
| 396 | __u64 timeout_ns; |
| 397 | }; |
| 398 | |
| 399 | struct drm_amdgpu_wait_fences_out { |
| 400 | __u32 status; |
| 401 | __u32 first_signaled; |
| 402 | }; |
| 403 | |
| 404 | union drm_amdgpu_wait_fences { |
| 405 | struct drm_amdgpu_wait_fences_in in; |
| 406 | struct drm_amdgpu_wait_fences_out out; |
| 407 | }; |
| 408 | |
Marek Olšák | 7450813 | 2015-05-27 14:31:12 +0200 | [diff] [blame] | 409 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
| 410 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 411 | |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 412 | /* Sets or returns a value associated with a buffer. */ |
| 413 | struct drm_amdgpu_gem_op { |
| 414 | /** GEM object handle */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 415 | __u32 handle; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 416 | /** AMDGPU_GEM_OP_* */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 417 | __u32 op; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 418 | /** Input or return value */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 419 | __u64 value; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 420 | }; |
| 421 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 422 | #define AMDGPU_VA_OP_MAP 1 |
| 423 | #define AMDGPU_VA_OP_UNMAP 2 |
Nicolai Hähnle | f104148 | 2017-04-03 10:22:59 +0200 | [diff] [blame] | 424 | #define AMDGPU_VA_OP_CLEAR 3 |
| 425 | #define AMDGPU_VA_OP_REPLACE 4 |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 426 | |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 427 | /* Delay the page table update till the next CS */ |
| 428 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) |
| 429 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 430 | /* Mapping flags */ |
| 431 | /* readable mapping */ |
| 432 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) |
| 433 | /* writable mapping */ |
| 434 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) |
| 435 | /* executable mapping, new for VI */ |
| 436 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) |
Nicolai Hähnle | f104148 | 2017-04-03 10:22:59 +0200 | [diff] [blame] | 437 | /* partially resident texture */ |
| 438 | #define AMDGPU_VM_PAGE_PRT (1 << 4) |
| 439 | /* MTYPE flags use bit 5 to 8 */ |
| 440 | #define AMDGPU_VM_MTYPE_MASK (0xf << 5) |
| 441 | /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ |
| 442 | #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) |
| 443 | /* Use NC MTYPE instead of default MTYPE */ |
| 444 | #define AMDGPU_VM_MTYPE_NC (1 << 5) |
| 445 | /* Use WC MTYPE instead of default MTYPE */ |
| 446 | #define AMDGPU_VM_MTYPE_WC (2 << 5) |
| 447 | /* Use CC MTYPE instead of default MTYPE */ |
| 448 | #define AMDGPU_VM_MTYPE_CC (3 << 5) |
| 449 | /* Use UC MTYPE instead of default MTYPE */ |
| 450 | #define AMDGPU_VM_MTYPE_UC (4 << 5) |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 451 | |
Christian König | 933091e | 2015-06-08 15:05:07 +0200 | [diff] [blame] | 452 | struct drm_amdgpu_gem_va { |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 453 | /** GEM object handle */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 454 | __u32 handle; |
| 455 | __u32 _pad; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 456 | /** AMDGPU_VA_OP_* */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 457 | __u32 operation; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 458 | /** AMDGPU_VM_PAGE_* */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 459 | __u32 flags; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 460 | /** va address to assign . Must be correctly aligned.*/ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 461 | __u64 va_address; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 462 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 463 | __u64 offset_in_bo; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 464 | /** Specify mapping size. Must be correctly aligned. */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 465 | __u64 map_size; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 466 | }; |
| 467 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 468 | #define AMDGPU_HW_IP_GFX 0 |
| 469 | #define AMDGPU_HW_IP_COMPUTE 1 |
| 470 | #define AMDGPU_HW_IP_DMA 2 |
| 471 | #define AMDGPU_HW_IP_UVD 3 |
| 472 | #define AMDGPU_HW_IP_VCE 4 |
Leo Liu | c7b5aae | 2017-03-23 10:43:40 -0400 | [diff] [blame] | 473 | #define AMDGPU_HW_IP_UVD_ENC 5 |
Leo Liu | 5faee77 | 2017-02-07 11:10:48 -0500 | [diff] [blame] | 474 | #define AMDGPU_HW_IP_VCN_DEC 6 |
Leo Liu | eeb51df | 2017-02-21 11:14:09 -0500 | [diff] [blame] | 475 | #define AMDGPU_HW_IP_VCN_ENC 7 |
| 476 | #define AMDGPU_HW_IP_NUM 8 |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 477 | |
| 478 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 |
| 479 | |
| 480 | #define AMDGPU_CHUNK_ID_IB 0x01 |
| 481 | #define AMDGPU_CHUNK_ID_FENCE 0x02 |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 482 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
Dave Airlie | 92b5b30 | 2017-06-27 12:56:25 +1000 | [diff] [blame] | 483 | #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 |
| 484 | #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 485 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 486 | struct drm_amdgpu_cs_chunk { |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 487 | __u32 chunk_id; |
| 488 | __u32 length_dw; |
| 489 | __u64 chunk_data; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 490 | }; |
| 491 | |
| 492 | struct drm_amdgpu_cs_in { |
| 493 | /** Rendering context id */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 494 | __u32 ctx_id; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 495 | /** Handle of resource list associated with CS */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 496 | __u32 bo_list_handle; |
| 497 | __u32 num_chunks; |
| 498 | __u32 _pad; |
| 499 | /** this points to __u64 * which point to cs chunks */ |
| 500 | __u64 chunks; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 501 | }; |
| 502 | |
| 503 | struct drm_amdgpu_cs_out { |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 504 | __u64 handle; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 505 | }; |
| 506 | |
| 507 | union drm_amdgpu_cs { |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 508 | struct drm_amdgpu_cs_in in; |
| 509 | struct drm_amdgpu_cs_out out; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 510 | }; |
| 511 | |
| 512 | /* Specify flags to be used for IB */ |
| 513 | |
| 514 | /* This IB should be submitted to CE */ |
| 515 | #define AMDGPU_IB_FLAG_CE (1<<0) |
| 516 | |
Nicolai Hähnle | f104148 | 2017-04-03 10:22:59 +0200 | [diff] [blame] | 517 | /* Preamble flag, which means the IB could be dropped if no context switch */ |
Jammy Zhou | d273d84 | 2015-06-06 05:07:56 +0800 | [diff] [blame] | 518 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
Jammy Zhou | db126d1 | 2015-05-11 23:02:09 +0800 | [diff] [blame] | 519 | |
Nicolai Hähnle | f104148 | 2017-04-03 10:22:59 +0200 | [diff] [blame] | 520 | /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ |
| 521 | #define AMDGPU_IB_FLAG_PREEMPT (1<<2) |
| 522 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 523 | struct drm_amdgpu_cs_chunk_ib { |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 524 | __u32 _pad; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 525 | /** AMDGPU_IB_FLAG_* */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 526 | __u32 flags; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 527 | /** Virtual address to begin IB execution */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 528 | __u64 va_start; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 529 | /** Size of submission */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 530 | __u32 ib_bytes; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 531 | /** HW IP to submit to */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 532 | __u32 ip_type; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 533 | /** HW IP index of the same type to submit to */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 534 | __u32 ip_instance; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 535 | /** Ring index to submit to */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 536 | __u32 ring; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 537 | }; |
| 538 | |
| 539 | struct drm_amdgpu_cs_chunk_dep { |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 540 | __u32 ip_type; |
| 541 | __u32 ip_instance; |
| 542 | __u32 ring; |
| 543 | __u32 ctx_id; |
| 544 | __u64 handle; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 545 | }; |
| 546 | |
| 547 | struct drm_amdgpu_cs_chunk_fence { |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 548 | __u32 handle; |
| 549 | __u32 offset; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 550 | }; |
| 551 | |
Dave Airlie | 92b5b30 | 2017-06-27 12:56:25 +1000 | [diff] [blame] | 552 | struct drm_amdgpu_cs_chunk_sem { |
| 553 | __u32 handle; |
| 554 | }; |
| 555 | |
Marek Olšák | ad4df73 | 2017-10-12 20:31:44 +0200 | [diff] [blame] | 556 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 |
| 557 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 |
| 558 | #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 |
| 559 | |
| 560 | union drm_amdgpu_fence_to_handle { |
| 561 | struct { |
| 562 | struct drm_amdgpu_fence fence; |
| 563 | __u32 what; |
Marek Olšák | f579747 | 2017-10-21 00:19:52 +0200 | [diff] [blame] | 564 | __u32 pad; |
Marek Olšák | ad4df73 | 2017-10-12 20:31:44 +0200 | [diff] [blame] | 565 | } in; |
| 566 | struct { |
| 567 | __u32 handle; |
| 568 | } out; |
| 569 | }; |
| 570 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 571 | struct drm_amdgpu_cs_chunk_data { |
| 572 | union { |
| 573 | struct drm_amdgpu_cs_chunk_ib ib_data; |
| 574 | struct drm_amdgpu_cs_chunk_fence fence_data; |
| 575 | }; |
| 576 | }; |
| 577 | |
| 578 | /** |
| 579 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU |
| 580 | * |
| 581 | */ |
| 582 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 583 | #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 584 | |
| 585 | /* indicate if acceleration can be working */ |
| 586 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 |
| 587 | /* get the crtc_id from the mode object id? */ |
| 588 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 |
| 589 | /* query hw IP info */ |
| 590 | #define AMDGPU_INFO_HW_IP_INFO 0x02 |
| 591 | /* query hw IP instance count for the specified type */ |
| 592 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 |
| 593 | /* timestamp for GL_ARB_timer_query */ |
| 594 | #define AMDGPU_INFO_TIMESTAMP 0x05 |
| 595 | /* Query the firmware version */ |
| 596 | #define AMDGPU_INFO_FW_VERSION 0x0e |
| 597 | /* Subquery id: Query VCE firmware version */ |
| 598 | #define AMDGPU_INFO_FW_VCE 0x1 |
| 599 | /* Subquery id: Query UVD firmware version */ |
| 600 | #define AMDGPU_INFO_FW_UVD 0x2 |
| 601 | /* Subquery id: Query GMC firmware version */ |
| 602 | #define AMDGPU_INFO_FW_GMC 0x03 |
| 603 | /* Subquery id: Query GFX ME firmware version */ |
| 604 | #define AMDGPU_INFO_FW_GFX_ME 0x04 |
| 605 | /* Subquery id: Query GFX PFP firmware version */ |
| 606 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 |
| 607 | /* Subquery id: Query GFX CE firmware version */ |
| 608 | #define AMDGPU_INFO_FW_GFX_CE 0x06 |
| 609 | /* Subquery id: Query GFX RLC firmware version */ |
| 610 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 |
| 611 | /* Subquery id: Query GFX MEC firmware version */ |
| 612 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 |
| 613 | /* Subquery id: Query SMC firmware version */ |
| 614 | #define AMDGPU_INFO_FW_SMC 0x0a |
| 615 | /* Subquery id: Query SDMA firmware version */ |
| 616 | #define AMDGPU_INFO_FW_SDMA 0x0b |
Nicolai Hähnle | f104148 | 2017-04-03 10:22:59 +0200 | [diff] [blame] | 617 | /* Subquery id: Query PSP SOS firmware version */ |
| 618 | #define AMDGPU_INFO_FW_SOS 0x0c |
| 619 | /* Subquery id: Query PSP ASD firmware version */ |
| 620 | #define AMDGPU_INFO_FW_ASD 0x0d |
Daniel Stone | 8e535dd | 2018-03-30 13:04:30 +0100 | [diff] [blame] | 621 | /* Subquery id: Query VCN firmware version */ |
| 622 | #define AMDGPU_INFO_FW_VCN 0x0e |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 623 | /* number of bytes moved for TTM migration */ |
| 624 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f |
| 625 | /* the used VRAM size */ |
| 626 | #define AMDGPU_INFO_VRAM_USAGE 0x10 |
| 627 | /* the used GTT size */ |
| 628 | #define AMDGPU_INFO_GTT_USAGE 0x11 |
| 629 | /* Information about GDS, etc. resource configuration */ |
| 630 | #define AMDGPU_INFO_GDS_CONFIG 0x13 |
| 631 | /* Query information about VRAM and GTT domains */ |
| 632 | #define AMDGPU_INFO_VRAM_GTT 0x14 |
| 633 | /* Query information about register in MMR address space*/ |
| 634 | #define AMDGPU_INFO_READ_MMR_REG 0x15 |
| 635 | /* Query information about device: rev id, family, etc. */ |
| 636 | #define AMDGPU_INFO_DEV_INFO 0x16 |
| 637 | /* visible vram usage */ |
| 638 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 639 | /* number of TTM buffer evictions */ |
| 640 | #define AMDGPU_INFO_NUM_EVICTIONS 0x18 |
| 641 | /* Query memory about VRAM and GTT domains */ |
| 642 | #define AMDGPU_INFO_MEMORY 0x19 |
| 643 | /* Query vce clock table */ |
| 644 | #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A |
| 645 | /* Query vbios related information */ |
| 646 | #define AMDGPU_INFO_VBIOS 0x1B |
| 647 | /* Subquery id: Query vbios size */ |
| 648 | #define AMDGPU_INFO_VBIOS_SIZE 0x1 |
| 649 | /* Subquery id: Query vbios image */ |
| 650 | #define AMDGPU_INFO_VBIOS_IMAGE 0x2 |
| 651 | /* Query UVD handles */ |
| 652 | #define AMDGPU_INFO_NUM_HANDLES 0x1C |
Nicolai Hähnle | f104148 | 2017-04-03 10:22:59 +0200 | [diff] [blame] | 653 | /* Query sensor related information */ |
| 654 | #define AMDGPU_INFO_SENSOR 0x1D |
| 655 | /* Subquery id: Query GPU shader clock */ |
| 656 | #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 |
| 657 | /* Subquery id: Query GPU memory clock */ |
| 658 | #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 |
| 659 | /* Subquery id: Query GPU temperature */ |
| 660 | #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 |
| 661 | /* Subquery id: Query GPU load */ |
| 662 | #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 |
| 663 | /* Subquery id: Query average GPU power */ |
| 664 | #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 |
| 665 | /* Subquery id: Query northbridge voltage */ |
| 666 | #define AMDGPU_INFO_SENSOR_VDDNB 0x6 |
| 667 | /* Subquery id: Query graphics voltage */ |
| 668 | #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 |
Rex Zhu | 2fa58c7 | 2018-03-20 14:08:09 +0800 | [diff] [blame] | 669 | /* Subquery id: Query GPU stable pstate shader clock */ |
| 670 | #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 |
| 671 | /* Subquery id: Query GPU stable pstate memory clock */ |
| 672 | #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 |
Dave Airlie | 92b5b30 | 2017-06-27 12:56:25 +1000 | [diff] [blame] | 673 | /* Number of VRAM page faults on CPU access. */ |
| 674 | #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E |
Andres Rodriguez | bcae722 | 2017-10-20 10:57:58 -0400 | [diff] [blame] | 675 | #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 676 | |
| 677 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 |
| 678 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff |
| 679 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 |
| 680 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff |
| 681 | |
Marek Olšák | 77bc69a | 2016-08-19 16:10:58 +0200 | [diff] [blame] | 682 | struct drm_amdgpu_query_fw { |
| 683 | /** AMDGPU_INFO_FW_* */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 684 | __u32 fw_type; |
Marek Olšák | 77bc69a | 2016-08-19 16:10:58 +0200 | [diff] [blame] | 685 | /** |
| 686 | * Index of the IP if there are more IPs of |
| 687 | * the same type. |
| 688 | */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 689 | __u32 ip_instance; |
Marek Olšák | 77bc69a | 2016-08-19 16:10:58 +0200 | [diff] [blame] | 690 | /** |
| 691 | * Index of the engine. Whether this is used depends |
| 692 | * on the firmware type. (e.g. MEC, SDMA) |
| 693 | */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 694 | __u32 index; |
| 695 | __u32 _pad; |
Marek Olšák | 77bc69a | 2016-08-19 16:10:58 +0200 | [diff] [blame] | 696 | }; |
| 697 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 698 | /* Input structure for the INFO ioctl */ |
| 699 | struct drm_amdgpu_info { |
| 700 | /* Where the return value will be stored */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 701 | __u64 return_pointer; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 702 | /* The size of the return value. Just like "size" in "snprintf", |
| 703 | * it limits how many bytes the kernel can write. */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 704 | __u32 return_size; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 705 | /* The query request id. */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 706 | __u32 query; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 707 | |
| 708 | union { |
| 709 | struct { |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 710 | __u32 id; |
| 711 | __u32 _pad; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 712 | } mode_crtc; |
| 713 | |
| 714 | struct { |
| 715 | /** AMDGPU_HW_IP_* */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 716 | __u32 type; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 717 | /** |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 718 | * Index of the IP if there are more IPs of the same |
| 719 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 720 | */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 721 | __u32 ip_instance; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 722 | } query_hw_ip; |
| 723 | |
| 724 | struct { |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 725 | __u32 dword_offset; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 726 | /** number of registers to read */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 727 | __u32 count; |
| 728 | __u32 instance; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 729 | /** For future use, no flags defined so far */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 730 | __u32 flags; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 731 | } read_mmr_reg; |
| 732 | |
Marek Olšák | 77bc69a | 2016-08-19 16:10:58 +0200 | [diff] [blame] | 733 | struct drm_amdgpu_query_fw query_fw; |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 734 | |
| 735 | struct { |
| 736 | __u32 type; |
| 737 | __u32 offset; |
| 738 | } vbios_info; |
Nicolai Hähnle | f104148 | 2017-04-03 10:22:59 +0200 | [diff] [blame] | 739 | |
| 740 | struct { |
| 741 | __u32 type; |
| 742 | } sensor_info; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 743 | }; |
| 744 | }; |
| 745 | |
| 746 | struct drm_amdgpu_info_gds { |
| 747 | /** GDS GFX partition size */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 748 | __u32 gds_gfx_partition_size; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 749 | /** GDS compute partition size */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 750 | __u32 compute_partition_size; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 751 | /** total GDS memory size */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 752 | __u32 gds_total_size; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 753 | /** GWS size per GFX partition */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 754 | __u32 gws_per_gfx_partition; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 755 | /** GSW size per compute partition */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 756 | __u32 gws_per_compute_partition; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 757 | /** OA size per GFX partition */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 758 | __u32 oa_per_gfx_partition; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 759 | /** OA size per compute partition */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 760 | __u32 oa_per_compute_partition; |
| 761 | __u32 _pad; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 762 | }; |
| 763 | |
| 764 | struct drm_amdgpu_info_vram_gtt { |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 765 | __u64 vram_size; |
| 766 | __u64 vram_cpu_accessible_size; |
| 767 | __u64 gtt_size; |
| 768 | }; |
| 769 | |
| 770 | struct drm_amdgpu_heap_info { |
| 771 | /** max. physical memory */ |
| 772 | __u64 total_heap_size; |
| 773 | |
| 774 | /** Theoretical max. available memory in the given heap */ |
| 775 | __u64 usable_heap_size; |
| 776 | |
| 777 | /** |
| 778 | * Number of bytes allocated in the heap. This includes all processes |
| 779 | * and private allocations in the kernel. It changes when new buffers |
| 780 | * are allocated, freed, and moved. It cannot be larger than |
| 781 | * heap_size. |
| 782 | */ |
| 783 | __u64 heap_usage; |
| 784 | |
| 785 | /** |
| 786 | * Theoretical possible max. size of buffer which |
| 787 | * could be allocated in the given heap |
| 788 | */ |
| 789 | __u64 max_allocation; |
| 790 | }; |
| 791 | |
| 792 | struct drm_amdgpu_memory_info { |
| 793 | struct drm_amdgpu_heap_info vram; |
| 794 | struct drm_amdgpu_heap_info cpu_accessible_vram; |
| 795 | struct drm_amdgpu_heap_info gtt; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 796 | }; |
| 797 | |
| 798 | struct drm_amdgpu_info_firmware { |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 799 | __u32 ver; |
| 800 | __u32 feature; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 801 | }; |
| 802 | |
Ken Wang | 4bf2941 | 2015-06-03 17:15:29 +0800 | [diff] [blame] | 803 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
| 804 | #define AMDGPU_VRAM_TYPE_GDDR1 1 |
| 805 | #define AMDGPU_VRAM_TYPE_DDR2 2 |
| 806 | #define AMDGPU_VRAM_TYPE_GDDR3 3 |
| 807 | #define AMDGPU_VRAM_TYPE_GDDR4 4 |
| 808 | #define AMDGPU_VRAM_TYPE_GDDR5 5 |
| 809 | #define AMDGPU_VRAM_TYPE_HBM 6 |
| 810 | #define AMDGPU_VRAM_TYPE_DDR3 7 |
Daniel Stone | 8e535dd | 2018-03-30 13:04:30 +0100 | [diff] [blame] | 811 | #define AMDGPU_VRAM_TYPE_DDR4 8 |
Ken Wang | 4bf2941 | 2015-06-03 17:15:29 +0800 | [diff] [blame] | 812 | |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 813 | struct drm_amdgpu_info_device { |
| 814 | /** PCI Device ID */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 815 | __u32 device_id; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 816 | /** Internal chip revision: A0, A1, etc.) */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 817 | __u32 chip_rev; |
| 818 | __u32 external_rev; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 819 | /** Revision id in PCI Config space */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 820 | __u32 pci_rev; |
| 821 | __u32 family; |
| 822 | __u32 num_shader_engines; |
| 823 | __u32 num_shader_arrays_per_engine; |
Alex Deucher | cf56460 | 2015-06-29 12:02:47 -0400 | [diff] [blame] | 824 | /* in KHz */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 825 | __u32 gpu_counter_freq; |
| 826 | __u64 max_engine_clock; |
| 827 | __u64 max_memory_clock; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 828 | /* cu information */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 829 | __u32 cu_active_number; |
Marek Olšák | ad4df73 | 2017-10-12 20:31:44 +0200 | [diff] [blame] | 830 | /* NOTE: cu_ao_mask is INVALID, DON'T use it */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 831 | __u32 cu_ao_mask; |
| 832 | __u32 cu_bitmap[4][4]; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 833 | /** Render backend pipe mask. One render backend is CB+DB. */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 834 | __u32 enabled_rb_pipes_mask; |
| 835 | __u32 num_rb_pipes; |
| 836 | __u32 num_hw_gfx_contexts; |
| 837 | __u32 _pad; |
| 838 | __u64 ids_flags; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 839 | /** Starting virtual address for UMDs. */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 840 | __u64 virtual_address_offset; |
Jammy Zhou | 241cf6d | 2015-05-13 01:14:11 +0800 | [diff] [blame] | 841 | /** The maximum virtual address */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 842 | __u64 virtual_address_max; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 843 | /** Required alignment of virtual addresses. */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 844 | __u32 virtual_address_alignment; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 845 | /** Page table entry - fragment size */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 846 | __u32 pte_fragment_size; |
| 847 | __u32 gart_page_size; |
Jammy Zhou | d273d84 | 2015-06-06 05:07:56 +0800 | [diff] [blame] | 848 | /** constant engine ram size*/ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 849 | __u32 ce_ram_size; |
Jammy Zhou | d273d84 | 2015-06-06 05:07:56 +0800 | [diff] [blame] | 850 | /** video memory type info*/ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 851 | __u32 vram_type; |
Ken Wang | 4bf2941 | 2015-06-03 17:15:29 +0800 | [diff] [blame] | 852 | /** video memory bit width*/ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 853 | __u32 vram_bit_width; |
Leo Liu | d2cbe9e | 2015-07-13 12:51:34 -0400 | [diff] [blame] | 854 | /* vce harvesting instance */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 855 | __u32 vce_harvest_config; |
Nicolai Hähnle | f104148 | 2017-04-03 10:22:59 +0200 | [diff] [blame] | 856 | /* gfx double offchip LDS buffers */ |
| 857 | __u32 gc_double_offchip_lds_buf; |
| 858 | /* NGG Primitive Buffer */ |
| 859 | __u64 prim_buf_gpu_addr; |
| 860 | /* NGG Position Buffer */ |
| 861 | __u64 pos_buf_gpu_addr; |
| 862 | /* NGG Control Sideband */ |
| 863 | __u64 cntl_sb_buf_gpu_addr; |
| 864 | /* NGG Parameter Cache */ |
| 865 | __u64 param_buf_gpu_addr; |
Dave Airlie | 92b5b30 | 2017-06-27 12:56:25 +1000 | [diff] [blame] | 866 | __u32 prim_buf_size; |
| 867 | __u32 pos_buf_size; |
| 868 | __u32 cntl_sb_buf_size; |
| 869 | __u32 param_buf_size; |
| 870 | /* wavefront size*/ |
| 871 | __u32 wave_front_size; |
| 872 | /* shader visible vgprs*/ |
| 873 | __u32 num_shader_visible_vgprs; |
| 874 | /* CU per shader array*/ |
| 875 | __u32 num_cu_per_sh; |
| 876 | /* number of tcc blocks*/ |
| 877 | __u32 num_tcc_blocks; |
| 878 | /* gs vgt table depth*/ |
| 879 | __u32 gs_vgt_table_depth; |
| 880 | /* gs primitive buffer depth*/ |
| 881 | __u32 gs_prim_buffer_depth; |
| 882 | /* max gs wavefront per vgt*/ |
| 883 | __u32 max_gs_waves_per_vgt; |
| 884 | __u32 _pad1; |
Marek Olšák | ad4df73 | 2017-10-12 20:31:44 +0200 | [diff] [blame] | 885 | /* always on cu bitmap */ |
| 886 | __u32 cu_ao_bitmap[4][4]; |
Christian König | 0a3c01f | 2017-11-07 15:31:45 +0100 | [diff] [blame] | 887 | /** Starting high virtual address for UMDs. */ |
| 888 | __u64 high_va_offset; |
| 889 | /** The maximum high virtual address */ |
| 890 | __u64 high_va_max; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 891 | }; |
| 892 | |
| 893 | struct drm_amdgpu_info_hw_ip { |
| 894 | /** Version of h/w IP */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 895 | __u32 hw_ip_version_major; |
| 896 | __u32 hw_ip_version_minor; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 897 | /** Capabilities */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 898 | __u64 capabilities_flags; |
Ken Wang | ef9aa37 | 2015-06-03 17:23:37 +0800 | [diff] [blame] | 899 | /** command buffer address start alignment*/ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 900 | __u32 ib_start_alignment; |
Ken Wang | ef9aa37 | 2015-06-03 17:23:37 +0800 | [diff] [blame] | 901 | /** command buffer size alignment*/ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 902 | __u32 ib_size_alignment; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 903 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 904 | __u32 available_rings; |
| 905 | __u32 _pad; |
| 906 | }; |
| 907 | |
| 908 | struct drm_amdgpu_info_num_handles { |
| 909 | /** Max handles as supported by firmware for UVD */ |
| 910 | __u32 uvd_max_handles; |
| 911 | /** Handles currently in use for UVD */ |
| 912 | __u32 uvd_used_handles; |
| 913 | }; |
| 914 | |
| 915 | #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 |
| 916 | |
| 917 | struct drm_amdgpu_info_vce_clock_table_entry { |
| 918 | /** System clock */ |
| 919 | __u32 sclk; |
| 920 | /** Memory clock */ |
| 921 | __u32 mclk; |
| 922 | /** VCE clock */ |
| 923 | __u32 eclk; |
| 924 | __u32 pad; |
| 925 | }; |
| 926 | |
| 927 | struct drm_amdgpu_info_vce_clock_table { |
| 928 | struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; |
| 929 | __u32 num_valid_entries; |
| 930 | __u32 pad; |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 931 | }; |
| 932 | |
| 933 | /* |
| 934 | * Supported GPU families |
| 935 | */ |
| 936 | #define AMDGPU_FAMILY_UNKNOWN 0 |
Marek Olšák | 3dc002d | 2017-03-21 20:31:53 +0100 | [diff] [blame] | 937 | #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 938 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ |
| 939 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ |
| 940 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ |
Marek Olšák | 77bc69a | 2016-08-19 16:10:58 +0200 | [diff] [blame] | 941 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ |
Marek Olšák | c34b28a | 2017-03-21 20:14:45 +0100 | [diff] [blame] | 942 | #define AMDGPU_FAMILY_AI 141 /* Vega10 */ |
Hawking Zhang | 3f457d2 | 2017-01-05 02:24:53 +0800 | [diff] [blame] | 943 | #define AMDGPU_FAMILY_RV 142 /* Raven */ |
Marek Olšák | 77bc69a | 2016-08-19 16:10:58 +0200 | [diff] [blame] | 944 | |
| 945 | #if defined(__cplusplus) |
| 946 | } |
| 947 | #endif |
Alex Deucher | 0936139 | 2015-04-20 12:04:22 -0400 | [diff] [blame] | 948 | |
| 949 | #endif |