Blame - shared-core/nouveau_reg.h - platform/external/libdrm

2006-08-27 08:55:02 +1000

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#define NV03_BOOT_0 0x00100000

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# define NV03_BOOT_0_RAM_AMOUNT 0x00000003

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# define NV03_BOOT_0_RAM_AMOUNT_8MB 0x00000000

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# define NV03_BOOT_0_RAM_AMOUNT_2MB 0x00000001

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# define NV03_BOOT_0_RAM_AMOUNT_4MB 0x00000002

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# define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM 0x00000003

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# define NV04_BOOT_0_RAM_AMOUNT_32MB 0x00000000

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# define NV04_BOOT_0_RAM_AMOUNT_4MB 0x00000001

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# define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002

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# define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003

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#define NV04_FIFO_DATA 0x0010020c

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# define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000

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# define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20

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#define NV03_PGRAPH_STATUS 0x004006b0

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#define NV04_PGRAPH_STATUS 0x00400700

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#define NV_RAMIN 0x00700000

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#define NV_RAMHT_HANDLE_OFFSET 0

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#define NV_RAMHT_CONTEXT_OFFSET 4

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# define NV_RAMHT_CONTEXT_VALID (1<<31)

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# define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24

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# define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16

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# define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0

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# define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1

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# define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0

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# define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23

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# define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20

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# define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0

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Ben Skeggs

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/* DMA object defines */

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#define NV_DMA_ACCESS_RW 0

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#define NV_DMA_ACCESS_RO 1

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#define NV_DMA_ACCESS_WO 2

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#define NV_DMA_TARGET_VIDMEM 0

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#define NV_DMA_TARGET_PCI 2

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#define NV_DMA_TARGET_AGP 3

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/*The following is not a real value used by nvidia cards, it's changed by nouveau_object_dma_create*/

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#define NV_DMA_TARGET_PCI_NONLINEAR 8

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Ben Skeggs

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/* Some object classes we care about in the drm */

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#define NV_CLASS_DMA_FROM_MEMORY 0x00000002

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#define NV_CLASS_DMA_TO_MEMORY 0x00000003

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#define NV_CLASS_NULL 0x00000030

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#define NV_CLASS_DMA_IN_MEMORY 0x0000003D

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Dave Airlie

2dd3c03

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#define NV03_FIFO_SIZE 0x8000UL

Ben Skeggs

c806bba

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#define NV_MAX_FIFO_NUMBER 128

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#define NV03_FIFO_REGS_SIZE 0x10000

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#define NV03_FIFO_REGS(i) (0x00800000+i*NV03_FIFO_REGS_SIZE)

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# define NV03_FIFO_REGS_DMAPUT(i) (NV03_FIFO_REGS(i)+0x40)

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# define NV03_FIFO_REGS_DMAGET(i) (NV03_FIFO_REGS(i)+0x44)

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#define NV50_FIFO_REGS_SIZE 0x2000

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#define NV50_FIFO_REGS(i) (0x00c00000+i*NV50_FIFO_REGS_SIZE)

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# define NV50_FIFO_REGS_DMAPUT(i) (NV50_FIFO_REGS(i)+0x40)

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# define NV50_FIFO_REGS_DMAGET(i) (NV50_FIFO_REGS(i)+0x44)

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Stephane Marchesin

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#define NV03_PMC_BOOT_0 0x00000000

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#define NV03_PMC_INTR_0 0x00000100

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# define NV_PMC_INTR_0_PFIFO_PENDING (1<< 8)

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# define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12)

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# define NV_PMC_INTR_0_CRTC0_PENDING (1<<24)

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# define NV_PMC_INTR_0_CRTC1_PENDING (1<<25)

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# define NV_PMC_INTR_0_CRTCn_PENDING (3<<24)

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#define NV03_PMC_INTR_EN_0 0x00000140

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# define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<< 0)

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#define NV03_PMC_ENABLE 0x00000200

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# define NV_PMC_ENABLE_PFIFO (1<< 8)

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# define NV_PMC_ENABLE_PGRAPH (1<<12)

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/* Disabling the below bit breaks newer (G7X only?) mobile chipsets,

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* the card will hang early on in the X init process.

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*/

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# define NV_PMC_ENABLE_UNK13 (1<<13)

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#define NV40_PMC_1700 0x00001700

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#define NV40_PMC_1704 0x00001704

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#define NV40_PMC_1708 0x00001708

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#define NV40_PMC_170C 0x0000170C

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Ben Skeggs

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/* probably PMC ? */

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#define NV50_PUNK_BAR0_PRAMIN 0x00001700

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#define NV50_PUNK_BAR_CFG_BASE 0x00001704

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#define NV50_PUNK_BAR_CFG_BASE_VALID (1<<30)

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#define NV50_PUNK_BAR1_CTXDMA 0x00001708

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#define NV50_PUNK_BAR1_CTXDMA_VALID (1<<31)

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#define NV50_PUNK_BAR3_CTXDMA 0x0000170C

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#define NV50_PUNK_BAR3_CTXDMA_VALID (1<<31)

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#define NV50_PUNK_UNK1710 0x00001710

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#define NV04_PTIMER_INTR_0 0x00009100

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#define NV04_PTIMER_INTR_EN_0 0x00009140

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#define NV04_PTIMER_NUMERATOR 0x00009200

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#define NV04_PTIMER_DENOMINATOR 0x00009210

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#define NV04_PTIMER_TIME_0 0x00009400

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#define NV04_PTIMER_TIME_1 0x00009410

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#define NV04_PTIMER_ALARM_0 0x00009420

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#define NV04_PFB_CFG0 0x00100200

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#define NV04_PFB_CFG1 0x00100204

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#define NV40_PFB_020C 0x0010020C

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#define NV10_PFB_TILE(i) (0x00100240 + (i*16))

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#define NV10_PFB_TILE__SIZE 8

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#define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16))

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#define NV10_PFB_TSIZE(i) (0x00100248 + (i*16))

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#define NV10_PFB_TSTATUS(i) (0x0010024C + (i*16))

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#define NV10_PFB_CLOSE_PAGE2 0x0010033C

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#define NV40_PFB_TILE(i) (0x00100600 + (i*16))

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#define NV40_PFB_TILE__SIZE_0 12

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#define NV40_PFB_TILE__SIZE_1 15

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#define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16))

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#define NV40_PFB_TSIZE(i) (0x00100608 + (i*16))

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#define NV40_PFB_TSTATUS(i) (0x0010060C + (i*16))

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#define NV04_PGRAPH_DEBUG_0 0x00400080

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#define NV04_PGRAPH_DEBUG_1 0x00400084

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#define NV04_PGRAPH_DEBUG_2 0x00400088

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#define NV04_PGRAPH_DEBUG_3 0x0040008c

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#define NV10_PGRAPH_DEBUG_4 0x00400090

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#define NV03_PGRAPH_INTR 0x00400100

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14ecf8d

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#define NV03_PGRAPH_NSTATUS 0x00400104

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# define NV03_PGRAPH_NSTATUS_STATE_IN_USE (1<<23)

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# define NV03_PGRAPH_NSTATUS_INVALID_STATE (1<<24)

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# define NV03_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25)

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# define NV03_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26)

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#define NV03_PGRAPH_NSOURCE 0x00400108

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# define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<< 0)

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# define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<< 1)

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# define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR (1<< 2)

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# define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION (1<< 3)

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# define NV03_PGRAPH_NSOURCE_LIMIT_COLOR (1<< 4)

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# define NV03_PGRAPH_NSOURCE_LIMIT_ZETA (1<< 5)

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# define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD (1<< 6)

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# define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION (1<< 7)

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# define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION (1<< 8)

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# define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1<< 9)

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# define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION (1<<10)

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# define NV03_PGRAPH_NSOURCE_STATE_INVALID (1<<11)

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# define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1<<12)

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# define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE (1<<13)

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# define NV03_PGRAPH_NSOURCE_METHOD_CNT (1<<14)

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# define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION (1<<15)

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# define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1<<16)

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# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A (1<<17)

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# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B (1<<18)

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#define NV03_PGRAPH_INTR_EN 0x00400140

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#define NV40_PGRAPH_INTR_EN 0x0040013C

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# define NV_PGRAPH_INTR_NOTIFY (1<< 0)

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# define NV_PGRAPH_INTR_MISSING_HW (1<< 4)

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dd47341

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# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12)

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# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16)

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# define NV_PGRAPH_INTR_ERROR (1<<20)

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17985f0

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#define NV10_PGRAPH_CTX_CONTROL 0x00400144

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#define NV10_PGRAPH_CTX_USER 0x00400148

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#define NV10_PGRAPH_CTX_SWITCH1 0x0040014C

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#define NV10_PGRAPH_CTX_SWITCH2 0x00400150

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#define NV10_PGRAPH_CTX_SWITCH3 0x00400154

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#define NV10_PGRAPH_CTX_SWITCH4 0x00400158

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#define NV10_PGRAPH_CTX_SWITCH5 0x0040015C

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#define NV04_PGRAPH_CTX_SWITCH1 0x00400160

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#define NV10_PGRAPH_CTX_CACHE1 0x00400160

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#define NV04_PGRAPH_CTX_SWITCH2 0x00400164

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#define NV04_PGRAPH_CTX_SWITCH3 0x00400168

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#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C

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#define NV04_PGRAPH_CTX_CONTROL 0x00400170

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#define NV04_PGRAPH_CTX_USER 0x00400174

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#define NV04_PGRAPH_CTX_CACHE1 0x00400180

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#define NV10_PGRAPH_CTX_CACHE2 0x00400180

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#define NV03_PGRAPH_CTX_CONTROL 0x00400190

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#define NV03_PGRAPH_CTX_USER 0x00400194

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#define NV04_PGRAPH_CTX_CACHE2 0x004001A0

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#define NV10_PGRAPH_CTX_CACHE3 0x004001A0

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#define NV04_PGRAPH_CTX_CACHE3 0x004001C0

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#define NV10_PGRAPH_CTX_CACHE4 0x004001C0

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#define NV04_PGRAPH_CTX_CACHE4 0x004001E0

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#define NV10_PGRAPH_CTX_CACHE5 0x004001E0

Ben Skeggs

38617b6

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#define NV40_PGRAPH_CTXCTL_0304 0x00400304

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#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001

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#define NV40_PGRAPH_CTXCTL_0310 0x00400310

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#define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020

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#define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040

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#define NV40_PGRAPH_CTXCTL_030C 0x0040030c

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#define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324

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#define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328

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#define NV40_PGRAPH_CTXCTL_CUR 0x0040032c

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#define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000

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#define NV40_PGRAPH_CTXCTL_CUR_INST_MASK 0x000FFFFF

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2007-02-03 04:57:06 +0100

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#define NV03_PGRAPH_ABS_X_RAM 0x00400400

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#define NV03_PGRAPH_ABS_Y_RAM 0x00400480

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#define NV03_PGRAPH_X_MISC 0x00400500

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#define NV03_PGRAPH_Y_MISC 0x00400504

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#define NV04_PGRAPH_VALID1 0x00400508

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#define NV04_PGRAPH_SOURCE_COLOR 0x0040050C

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#define NV04_PGRAPH_MISC24_0 0x00400510

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#define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514

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#define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518

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#define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C

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#define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520

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#define NV03_PGRAPH_CLIPX_0 0x00400524

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#define NV03_PGRAPH_CLIPX_1 0x00400528

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#define NV03_PGRAPH_CLIPY_0 0x0040052C

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#define NV03_PGRAPH_CLIPY_1 0x00400530

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#define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534

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#define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538

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#define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C

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#define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540

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#define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544

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#define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548

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#define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560

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#define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564

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#define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568

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#define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C

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#define NV04_PGRAPH_MISC24_1 0x00400570

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#define NV04_PGRAPH_MISC24_2 0x00400574

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#define NV04_PGRAPH_VALID2 0x00400578

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#define NV04_PGRAPH_PASSTHRU_0 0x0040057C

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#define NV04_PGRAPH_PASSTHRU_1 0x00400580

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#define NV04_PGRAPH_PASSTHRU_2 0x00400584

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#define NV10_PGRAPH_DIMX_TEXTURE 0x00400588

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#define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C

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#define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590

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#define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594

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#define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598

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#define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C

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#define NV04_PGRAPH_FORMAT_0 0x004005A8

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#define NV04_PGRAPH_FORMAT_1 0x004005AC

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#define NV04_PGRAPH_FILTER_0 0x004005B0

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#define NV04_PGRAPH_FILTER_1 0x004005B4

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#define NV03_PGRAPH_MONO_COLOR0 0x00400600

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#define NV04_PGRAPH_ROP3 0x00400604

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#define NV04_PGRAPH_BETA_AND 0x00400608

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#define NV04_PGRAPH_BETA_PREMULT 0x0040060C

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#define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610

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2007-01-29 04:03:59 +0100

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#define NV04_PGRAPH_FORMATS 0x00400618

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#define NV10_PGRAPH_DEBUG_2 0x00400620

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#define NV04_PGRAPH_BOFFSET0 0x00400640

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#define NV04_PGRAPH_BOFFSET1 0x00400644

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#define NV04_PGRAPH_BOFFSET2 0x00400648

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#define NV04_PGRAPH_BOFFSET3 0x0040064C

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#define NV04_PGRAPH_BOFFSET4 0x00400650

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#define NV04_PGRAPH_BOFFSET5 0x00400654

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#define NV04_PGRAPH_BBASE0 0x00400658

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#define NV04_PGRAPH_BBASE1 0x0040065C

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#define NV04_PGRAPH_BBASE2 0x00400660

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#define NV04_PGRAPH_BBASE3 0x00400664

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#define NV04_PGRAPH_BBASE4 0x00400668

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#define NV04_PGRAPH_BBASE5 0x0040066C

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#define NV04_PGRAPH_BPITCH0 0x00400670

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#define NV04_PGRAPH_BPITCH1 0x00400674

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#define NV04_PGRAPH_BPITCH2 0x00400678

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#define NV04_PGRAPH_BPITCH3 0x0040067C

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#define NV04_PGRAPH_BPITCH4 0x00400680

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#define NV04_PGRAPH_BLIMIT0 0x00400684

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#define NV04_PGRAPH_BLIMIT1 0x00400688

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#define NV04_PGRAPH_BLIMIT2 0x0040068C

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#define NV04_PGRAPH_BLIMIT3 0x00400690

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#define NV04_PGRAPH_BLIMIT4 0x00400694

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#define NV04_PGRAPH_BLIMIT5 0x00400698

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#define NV04_PGRAPH_BSWIZZLE2 0x0040069C

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#define NV04_PGRAPH_BSWIZZLE5 0x004006A0

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#define NV04_PGRAPH_SURFACE 0x0040070C

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#define NV04_PGRAPH_STATE 0x00400710

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#define NV10_PGRAPH_SURFACE 0x00400710

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#define NV04_PGRAPH_NOTIFY 0x00400714

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#define NV10_PGRAPH_STATE 0x00400714

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#define NV10_PGRAPH_NOTIFY 0x00400718

Matthieu Castet

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Stephane Marchesin

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#define NV04_PGRAPH_FIFO 0x00400720

Matthieu Castet

4ae64a1

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Stephane Marchesin

2007-02-03 04:57:06 +0100

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#define NV04_PGRAPH_BPIXEL 0x00400724

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#define NV10_PGRAPH_RDI_INDEX 0x00400750

Stephane Marchesin

7ab9e7f

2007-02-03 05:56:42 +0100

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274

#define NV04_PGRAPH_FFINTFC_ST2 0x00400754

Stephane Marchesin

2007-02-03 04:57:06 +0100

[diff] [blame]

275

#define NV10_PGRAPH_RDI_DATA 0x00400754

Stephane Marchesin

2007-01-29 04:03:59 +0100

[diff] [blame]

276

#define NV04_PGRAPH_DMA_PITCH 0x00400760

Stephane Marchesin

2007-02-03 04:57:06 +0100

[diff] [blame]

277

#define NV10_PGRAPH_FFINTFC_ST2 0x00400764

Stephane Marchesin

2007-01-29 04:03:59 +0100

[diff] [blame]

278

#define NV04_PGRAPH_DVD_COLORFMT 0x00400764

279

#define NV04_PGRAPH_SCALED_FORMAT 0x00400768

Stephane Marchesin

2007-02-03 04:57:06 +0100

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280

#define NV10_PGRAPH_DMA_PITCH 0x00400770

281

#define NV10_PGRAPH_DVD_COLORFMT 0x00400774

282

#define NV10_PGRAPH_SCALED_FORMAT 0x00400778

283

#define NV10_PGRAPH_CHANNEL_CTX_TABLE 0x00400780

284

#define NV10_PGRAPH_CHANNEL_CTX_SIZE 0x00400784

Ben Skeggs

38617b6

2007-06-25 03:52:06 +1000

[diff] [blame]

285

#define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784

Stephane Marchesin

2007-02-03 04:57:06 +0100

[diff] [blame]

286

#define NV10_PGRAPH_CHANNEL_CTX_POINTER 0x00400788

Ben Skeggs

38617b6

2007-06-25 03:52:06 +1000

[diff] [blame]

287

#define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788

288

#define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001

289

#define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002

Stephane Marchesin

2007-02-03 04:57:06 +0100

[diff] [blame]

290

#define NV04_PGRAPH_PATT_COLOR0 0x00400800

291

#define NV04_PGRAPH_PATT_COLOR1 0x00400804

292

#define NV04_PGRAPH_PATTERN 0x00400808

293

#define NV04_PGRAPH_PATTERN_SHAPE 0x00400810

294

#define NV04_PGRAPH_CHROMA 0x00400814

Stephane Marchesin

2007-01-29 04:03:59 +0100

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295

#define NV04_PGRAPH_CONTROL0 0x00400818

296

#define NV04_PGRAPH_CONTROL1 0x0040081C

297

#define NV04_PGRAPH_CONTROL2 0x00400820

298

#define NV04_PGRAPH_BLEND 0x00400824

Stephane Marchesin

2007-02-03 04:57:06 +0100

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299

#define NV04_PGRAPH_STORED_FMT 0x00400830

300

#define NV04_PGRAPH_PATT_COLORRAM 0x00400900

Ben Skeggs

2007-03-26 19:43:48 +1000

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301

#define NV40_PGRAPH_TILE0(i) 0x00400900

302

#define NV40_PGRAPH_TLIMIT0(i) 0x00400904

303

#define NV40_PGRAPH_TSIZE0(i) 0x00400908

304

#define NV40_PGRAPH_TSTATUS0(i) 0x0040090C

305

#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16))

306

#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16))

307

#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16))

308

#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16))

Stephane Marchesin

2007-01-29 04:03:59 +0100

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309

#define NV04_PGRAPH_U_RAM 0x00400D00

Ben Skeggs

2007-03-26 19:43:48 +1000

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310

#define NV47_PGRAPH_TILE0(i) 0x00400D00

311

#define NV47_PGRAPH_TLIMIT0(i) 0x00400D04

312

#define NV47_PGRAPH_TSIZE0(i) 0x00400D08

313

#define NV47_PGRAPH_TSTATUS0(i) 0x00400D0C

Stephane Marchesin

2007-01-29 04:03:59 +0100

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314

#define NV04_PGRAPH_V_RAM 0x00400D40

315

#define NV04_PGRAPH_W_RAM 0x00400D80

Stephane Marchesin

2007-02-03 04:57:06 +0100

[diff] [blame]

316

#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00

317

#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20

318

#define NV10_PGRAPH_XFMODE0 0x00400F40

319

#define NV10_PGRAPH_XFMODE1 0x00400F44

320

#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48

321

#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C

322

#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50

323

#define NV10_PGRAPH_PIPE_DATA 0x00400F54

324

#define NV04_PGRAPH_DMA_START_0 0x00401000

325

#define NV04_PGRAPH_DMA_START_1 0x00401004

326

#define NV04_PGRAPH_DMA_LENGTH 0x00401008

327

#define NV04_PGRAPH_DMA_MISC 0x0040100C

328

#define NV04_PGRAPH_DMA_DATA_0 0x00401020

329

#define NV04_PGRAPH_DMA_DATA_1 0x00401024

330

#define NV04_PGRAPH_DMA_RM 0x00401030

331

#define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040

332

#define NV04_PGRAPH_DMA_A_CONTROL 0x00401044

333

#define NV04_PGRAPH_DMA_A_LIMIT 0x00401048

334

#define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C

335

#define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050

336

#define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054

337

#define NV04_PGRAPH_DMA_A_OFFSET 0x00401058

338

#define NV04_PGRAPH_DMA_A_SIZE 0x0040105C

339

#define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060

340

#define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080

341

#define NV04_PGRAPH_DMA_B_CONTROL 0x00401084

342

#define NV04_PGRAPH_DMA_B_LIMIT 0x00401088

343

#define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C

344

#define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090

345

#define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094

346

#define NV04_PGRAPH_DMA_B_OFFSET 0x00401098

347

#define NV04_PGRAPH_DMA_B_SIZE 0x0040109C

348

#define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0

Ben Skeggs

2007-03-26 19:43:48 +1000

[diff] [blame]

349

#define NV40_PGRAPH_TILE1(i) 0x00406900

350

#define NV40_PGRAPH_TLIMIT1(i) 0x00406904

351

#define NV40_PGRAPH_TSIZE1(i) 0x00406908

352

#define NV40_PGRAPH_TSTATUS1(i) 0x0040690C

Stephane Marchesin

2007-01-29 04:03:59 +0100

[diff] [blame]

353

Jeremy Kolb

4297a83

2007-01-12 00:13:05 -0500

[diff] [blame]

354

Dave Airlie

2006-08-27 08:55:02 +1000

[diff] [blame]

355

/* It's a guess that this works on NV03. Confirmed on NV04, though */

Stephane Marchesin

2007-02-03 04:57:06 +0100

[diff] [blame]

356

#define NV04_PFIFO_DELAY_0 0x00002040

357

#define NV04_PFIFO_DMA_TIMESLICE 0x00002044

358

#define NV04_PFIFO_NEXT_CHANNEL 0x00002050

359

#define NV03_PFIFO_INTR_0 0x00002100

360

#define NV03_PFIFO_INTR_EN_0 0x00002140

Stephane Marchesin

7ef44b2

2006-10-12 17:31:49 +0200

[diff] [blame]

361

# define NV_PFIFO_INTR_CACHE_ERROR (1<< 0)

362

# define NV_PFIFO_INTR_RUNOUT (1<< 4)

363

# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8)

364

# define NV_PFIFO_INTR_DMA_PUSHER (1<<12)

365

# define NV_PFIFO_INTR_DMA_PT (1<<16)

366

# define NV_PFIFO_INTR_SEMAPHORE (1<<20)

367

# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24)

Stephane Marchesin

2007-02-03 04:57:06 +0100

[diff] [blame]

368

#define NV03_PFIFO_RAMHT 0x00002210

369

#define NV03_PFIFO_RAMFC 0x00002214

370

#define NV03_PFIFO_RAMRO 0x00002218

Ben Skeggs

7002082

2006-11-14 08:11:49 +1100

[diff] [blame]

371

#define NV40_PFIFO_RAMFC 0x00002220

Stephane Marchesin

2007-02-03 04:57:06 +0100

[diff] [blame]

372

#define NV03_PFIFO_CACHES 0x00002500

373

#define NV04_PFIFO_MODE 0x00002504

374

#define NV04_PFIFO_DMA 0x00002508

375

#define NV04_PFIFO_SIZE 0x0000250c

Ben Skeggs

c806bba

2007-07-05 00:12:33 +1000

[diff] [blame]

376

#define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4)

377

#define NV50_PFIFO_CTX_TABLE__SIZE 128

378

#define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31)

379

#define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30)

380

#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF

381

#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF

Stephane Marchesin

2007-02-03 04:57:06 +0100

[diff] [blame]

382

#define NV03_PFIFO_CACHE0_PUSH0 0x00003000

383

#define NV03_PFIFO_CACHE0_PULL0 0x00003040

384

#define NV04_PFIFO_CACHE0_PULL0 0x00003050

385

#define NV04_PFIFO_CACHE0_PULL1 0x00003054

386

#define NV03_PFIFO_CACHE1_PUSH0 0x00003200

387

#define NV03_PFIFO_CACHE1_PUSH1 0x00003204

388

#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220

389

#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224

390

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000

391

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008

392

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010

393

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018

394

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020

395

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028

396

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030

397

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038

398

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040

399

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048

400

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050

401

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058

402

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060

403

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068

404

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070

405

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078

406

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080

407

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088

408

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090

409

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098

410

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0

411

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8

412

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0

413

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8

414

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0

415

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8

416

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0

417

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8

418

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0

419

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8

420

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0

421

# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8

422

# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000

423

# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000

424

# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000

425

# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000

426

# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000

427

# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000

428

# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000

429

# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000

430

# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000

431

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000

432

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000

433

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000

434

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000

435

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000

436

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000

437

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000

438

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000

439

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000

440

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000

441

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000

442

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000

443

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000

444

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000

445

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000

446

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000

447

# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000

448

# define NV_PFIFO_CACHE1_ENDIAN 0x80000000

449

# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF

450

# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000

451

#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228

452

#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c

453

#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230

454

#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240

455

#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244

456

#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248

457

#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C

458

#define NV03_PFIFO_CACHE1_PULL0 0x00003240

459

#define NV04_PFIFO_CACHE1_PULL0 0x00003250

460

#define NV03_PFIFO_CACHE1_PULL1 0x00003250

461

#define NV04_PFIFO_CACHE1_PULL1 0x00003254

462

#define NV04_PFIFO_CACHE1_HASH 0x00003258

463

#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260

464

#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264

465

#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268

466

#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C

467

#define NV03_PFIFO_CACHE1_GET 0x00003270

468

#define NV04_PFIFO_CACHE1_ENGINE 0x00003280

Ben Skeggs

05d86d9

2007-06-24 18:57:09 +1000

[diff] [blame]

469

#define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0

Ben Skeggs

b5cf0d6

2006-10-18 02:37:19 +1100

[diff] [blame]

470

#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0

471

#define NV40_PFIFO_UNK32E4 0x000032E4

Stephane Marchesin

2007-02-03 04:57:06 +0100

[diff] [blame]

472

#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8))

473

#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8))

474

#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8))

475

#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8))

Dave Airlie