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gerrit-public.fairphone.software / platform / external / lldb / 7bc390873f7c1c798c36c8003c4b82597f67c703 / source / Plugins / Instruction / ARM / EmulateInstructionARM.cpp
  1. 7bc3908 Made the lldb_private::Opcode struct into a real boy... I mean class. by Greg Clayton · 13 years ago
  2. b344843 Fixed the LLDB build so that we can have private types, private enums and by Greg Clayton · 13 years ago
  3. baf1f64 by Caroline Tice · 13 years ago
  4. e221288 by Caroline Tice · 13 years ago
  5. 4fdf760 Split all of the core of LLDB.framework/lldb.so into a by Greg Clayton · 13 years ago
  6. 3e40797 by Caroline Tice · 13 years ago
  7. 8d681f5 by Caroline Tice · 13 years ago
  8. 8ce836d by Caroline Tice · 13 years ago
  9. 2b03ed8 by Caroline Tice · 13 years ago
  10. b27771d by Caroline Tice · 13 years ago
  11. 11555f2 by Caroline Tice · 13 years ago
  12. 8ce96d9 by Caroline Tice · 13 years ago
  13. 868198b by Caroline Tice · 13 years ago
  14. 6bf6516 by Caroline Tice · 13 years ago
  15. 40b1a6c by Caroline Tice · 13 years ago
  16. dcc11b3 by Caroline Tice · 13 years ago
  17. 5c1e2ed by Caroline Tice · 13 years ago
  18. 291a3e9 by Caroline Tice · 13 years ago
  19. d2fac09 by Caroline Tice · 13 years ago
  20. 78fb563 by Caroline Tice · 13 years ago
  21. 672f311 by Caroline Tice · 13 years ago
  22. 5f59391 by Caroline Tice · 13 years ago
  23. a5e28af by Caroline Tice · 13 years ago
  24. 0e6bc95 by Caroline Tice · 13 years ago
  25. 952b538 by Caroline Tice · 13 years ago
  26. 0491b3b by Caroline Tice · 13 years ago
  27. 01d6157 Add emulation for Encoding A1 of A8.6.97 MOV (register). by Johnny Chen · 14 years ago
  28. 696b4ef Fix typos in the opcode entries for branch instructions. by Johnny Chen · 14 years ago
  29. 59e6ab7 Add emulation for BXJ (Branch and Exchange Jazelle), assuming that the attempt to by Johnny Chen · 14 years ago
  30. b9f02cf Add emulation methods for Bitwise Bit Clear (immediate and register) operations. by Johnny Chen · 14 years ago
  31. 15a7a6b Add emulation methods for "SUB (immediate, Thumb)" and "SUB (immediate, ARM)" operations. by Johnny Chen · 14 years ago
  32. a695f95 Add emulation for "ADR" operations. Add a ThumbImm8Scaled() convenience function by Johnny Chen · 14 years ago
  33. c9e747f Modify EmulateSUBSPImm() to handle the cases with generic Rd value instead of by Johnny Chen · 14 years ago
  34. 9b38177 Add emulation methods for "SBC (immediate)" and "SBC (register)" operations. by Johnny Chen · 14 years ago
  35. 940b103 Abtracted all mach-o and ELF out of ArchSpec. This patch is a modified form by Greg Clayton · 14 years ago
  36. 2434884 Renamed macro definition of CPSR_C to be CPSR_C_POS to avoid confusions and subtle bugs. by Johnny Chen · 14 years ago
  37. 90e607b Add emulation methods for "RSC (immediate)" and "RSC (register)" operations. by Johnny Chen · 14 years ago
  38. ed32e7c Add emulation methods for "RSB (immediate)" and "RSB (register)". by Johnny Chen · 14 years ago
  39. 3dd0605 Add two convenience functions: DecodeImmShiftThumb() and DecodeImmShiftARM() to ARMUtils.h. by Johnny Chen · 14 years ago
  40. 078fbc6 Add "cmp<c>.w <Rn>, #<const>" emulation to EmulateCMPImm() method, by Johnny Chen · 14 years ago
  41. 688926f Fix the 'variants' field of "CMN (immediate)" Encoding T1 entry, it should be ARMV6T2_ABOVE, not ARMvAll. by Johnny Chen · 14 years ago
  42. 3847dad Add ARM encoding entries for "CMN (immediate)" and "CMN (register)" operations. by Johnny Chen · 14 years ago
  43. 34075cb Add ARM encoding entries for "CMP (immediate)" and "CMP (register)" operations. by Johnny Chen · 14 years ago
  44. d642a6a Add emulation methods for "MVN (immediate)" and "MVN (register)". by Johnny Chen · 14 years ago
  45. 2115b41 Add emulation methods for "EOR (Immediate)", "EOR (register)", by Johnny Chen · 14 years ago
  46. de3cce3 Add emulation methods for "TST (immediate)" and "TST (register)". by Johnny Chen · 14 years ago
  47. e39f22d Make the helper method ReadCoreReg(uint32_t reg, bool *success) more generic by Johnny Chen · 14 years ago
  48. 30fec12 by Caroline Tice · 14 years ago
  49. 7c5234d Add emulation methods for "ORR (immediate)" and "ORR (register)". by Johnny Chen · 14 years ago
  50. f55261f by Caroline Tice · 14 years ago
  51. 157b959 Add emulation methods for "ADC (immediate)" and "ADC (register)". by Johnny Chen · 14 years ago
  52. 21b604b by Caroline Tice · 14 years ago
  53. e97c0d5 Add emulation methods for "AND (immediate)" and "AND (register)". by Johnny Chen · 14 years ago
  54. fe47911 by Caroline Tice · 14 years ago
  55. e92b27c Fix typo. by Johnny Chen · 14 years ago
  56. 8fa2059 Add emulation of Encoding A1 "A8.6.6 ADD (register)" and "A8.6.5 ADD (immediate, ARM)". by Johnny Chen · 14 years ago
  57. 4d729c5 by Caroline Tice · 14 years ago
  58. 864a8e8 Finished renamings to make the emulation method names consistent case-wise. by Johnny Chen · 14 years ago
  59. 9f68772 Some renamings to make the emulation method names consistent case-wise. by Johnny Chen · 14 years ago
  60. 104c8b6 Fix a bug in EmulateTB() (TBB, TBH) where the branch length should be "twice" by Johnny Chen · 14 years ago
  61. 10530c2 Refactoring. Abstracted the set flags operation into its own helper method by Johnny Chen · 14 years ago
  62. d761dcf A8.6.6 ADD (register) by Johnny Chen · 14 years ago
  63. 60299ec Add EmulateTB() method to emulate "Table Branch Byte" and "Table Branch Halfword" by Johnny Chen · 14 years ago
  64. cc96eb5 by Caroline Tice · 14 years ago
  65. 7c677ac Move Align(val, alignment) utility function to ARMUtils.h. by Johnny Chen · 14 years ago
  66. ca67d1c Refactoring. Wrap the following pseudocode from the ARM Architecture Reference Manul: by Johnny Chen · 14 years ago
  67. eeab485 Add emulation methods for ROR (immediate), ROR (register), and RRX. by Johnny Chen · 14 years ago
  68. 73a29de by Caroline Tice · 14 years ago
  69. 2ee35bc Add encoding entries for LSL (immediate and register) and LSR (immediate and register) to by Johnny Chen · 14 years ago
  70. 41a0a15 Add emulation methods for LSL (immediate), LSL (register), LSR (immediate), and LSR (register). by Johnny Chen · 14 years ago
  71. 3fd63e9 by Caroline Tice · 14 years ago
  72. e7f8953 A8.6.14 ASR (register) by Johnny Chen · 14 years ago
  73. 7fac857 Add eContextRegisterLoad instruction emulation context. by Caroline Tice · 14 years ago
  74. 395fc33 Made lldb_private::ArchSpec contain much more than just an architecture. It by Greg Clayton · 14 years ago
  75. 668b451 Remove the "Register &reg" parameter from the BXWritePC(), LoadWritePC(), and ALUWritePC() by Johnny Chen · 14 years ago
  76. 4d896db Fix wrong mask and encoding for T2 of ASR (immediate). by Johnny Chen · 14 years ago
  77. 82f16aa A8.6.14 ASR (immediate) by Johnny Chen · 14 years ago
  78. af55656 by Caroline Tice · 14 years ago
  79. b6f8d7e by Caroline Tice · 14 years ago
  80. 2fd5034 Remove the unnecessary assignment of m_inst_cpsr inside EvaluateInstruction(), by Johnny Chen · 14 years ago
  81. 1511f50 by Caroline Tice · 14 years ago
  82. 9798cfc Add missing logic (if BadReg(d) then UNPREDICTABLE;) for Encoding T2 of EmulateMovRdImm(). by Johnny Chen · 14 years ago
  83. e524a35 Fix build warning (unused variable). by Johnny Chen · 14 years ago
  84. 9bfe7f2 - Rearrange instruction emulation contexts to use a union for the by Caroline Tice · 14 years ago
  85. 357c30f Add entries for EmulateMovRdImm() -- "MOV (immediate)" -- Encodings T1 & T2 into g_thumb_opcodes by Johnny Chen · 14 years ago
  86. 33bf6ab Add impl for EmulateMvnRdImm() -- "MVN (immediate)". Plus zero out the arg0 field of by Johnny Chen · 14 years ago
  87. 28070c3 Add entries for Encodings T1 and A1 of "MVN (immediate)" to g_arm_opcodes and g_thumb_opcodes by Johnny Chen · 14 years ago
  88. 098ae2d Add helper methods InITBlock() and LastInITBlock() to EmulateInstructionARM class by Johnny Chen · 14 years ago
  89. ab3b351 Add EmulateBXRm() ("Branch and Exchange") to both g_arm_opcodes and g_thumb_opcodes table. by Johnny Chen · 14 years ago
  90. fa17220 by Caroline Tice · 14 years ago
  91. e4a4d30 Add EmulateCmpRnRm() for Encodings T1 & T2 to the g_thumb_opcodes table to emulate by Johnny Chen · 14 years ago
  92. 383d629 Rearraned some emulate instruction entries under the appropriate category. by Johnny Chen · 14 years ago
  93. 44c10f0 Handle the case of interworking branch for EmulateLDMDA. by Johnny Chen · 14 years ago
  94. c9de910 Add Thumb2 LDR (literal) instruction into the g_thumb_opcodes table. by Johnny Chen · 14 years ago
  95. 62ff6f5 Fix build. by Johnny Chen · 14 years ago
  96. 713c266 Add new instruction context, eContextWriteRegisterRandomBits. by Caroline Tice · 14 years ago
  97. d4dc444 Add an entry for CMP (immediate) (Encoding T1) to the g_thumb_opcodes table. by Johnny Chen · 14 years ago
  98. bf6ad17 Add a helper method AddWithCarry() to the EmulateInstructionARM class. by Johnny Chen · 14 years ago
  99. bd59990 Namings are important. Renamed Bits32(const uint32_t val, uint32_t bit) to Bit32(val, bit) and by Johnny Chen · 14 years ago
  100. 1928020 Some refactorings to use the convenience function: Bits32(const uint32_t value, const uint32_t bit). by Johnny Chen · 14 years ago