commit 04863d06fb3f2972355c990b29edcab1d9a85b41
author Bill Wendling <isanbard@gmail.com> Sat Nov 13 10:40:19 2010 +0000
committer Bill Wendling <isanbard@gmail.com> Sat Nov 13 10:40:19 2010 +0000
tree 87b91000b642ef427409d1381a73bd70d352f3e6
parent 6c470b806fe8eefae1b7bf180f269a4b120173a4

Minor cleanups:

- Get the opcode once.
- Add a ParserMatchClass to reglist.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118997 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index cb8f787..f54398c 100644
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -31,8 +31,10 @@
 
 
 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
+  unsigned Opcode = MI->getOpcode();
+
   // Check for MOVs and print canonical forms, instead.
-  if (MI->getOpcode() == ARM::MOVs) {
+  if (Opcode == ARM::MOVs) {
     // FIXME: Thumb variants?
     const MCOperand &Dst = MI->getOperand(0);
     const MCOperand &MO1 = MI->getOperand(1);
@@ -61,7 +63,7 @@
   }
 
   // A8.6.123 PUSH
-  if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
+  if ((Opcode == ARM::STM_UPD || Opcode == ARM::t2STM_UPD) &&
       MI->getOperand(0).getReg() == ARM::SP) {
     const MCOperand &MO1 = MI->getOperand(2);
     if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
@@ -74,7 +76,7 @@
   }
 
   // A8.6.122 POP
-  if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
+  if ((Opcode == ARM::LDM_UPD || Opcode == ARM::t2LDM_UPD) &&
       MI->getOperand(0).getReg() == ARM::SP) {
     const MCOperand &MO1 = MI->getOperand(2);
     if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
@@ -87,7 +89,7 @@
   }
 
   // A8.6.355 VPUSH
-  if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
+  if ((Opcode == ARM::VSTMS_UPD || Opcode == ARM::VSTMD_UPD) &&
       MI->getOperand(0).getReg() == ARM::SP) {
     const MCOperand &MO1 = MI->getOperand(2);
     if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
@@ -100,7 +102,7 @@
   }
 
   // A8.6.354 VPOP
-  if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
+  if ((Opcode == ARM::VLDMS_UPD || Opcode == ARM::VLDMD_UPD) &&
       MI->getOperand(0).getReg() == ARM::SP) {
     const MCOperand &MO1 = MI->getOperand(2);
     if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
@@ -113,7 +115,7 @@
   }
 
   printInstruction(MI, O);
- }
+}
 
 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
                                   raw_ostream &O) {