commit 74f4a130d2b4542668bd8b760462ed642b25f075
author Vikram S. Adve <vadve@cs.uiuc.edu> Tue Jul 31 21:46:57 2001 +0000
committer Vikram S. Adve <vadve@cs.uiuc.edu> Tue Jul 31 21:46:57 2001 +0000
tree ca1c84293f77db6c356a8d216645300931fa8d37
parent 35fc0b172ef6a425811d6bfe8f043326d0b9cbee

Generate dummy Phi machine instruction, plus a bug fix for BrCond(boolreg).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp

diff --git a/lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp b/lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp
index 4ce6291..901ad00 100644
--- a/lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp
+++ b/lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp
@@ -138,7 +138,8 @@
     case 130:
     case 131:
     case 132:
-    case 153: return true; break;
+    case 153:
+    case 155: return true; break;
       
     default: return false; break;
     }
@@ -310,7 +311,9 @@
   case 27:	// reg:   ToUIntTy(reg)
   case 29:	// reg:   ToULongTy(reg)
     opType = subtreeRoot->leftChild()->getValue()->getType();
-    assert(opType->isIntegral() || opType == Type::BoolTy);
+    assert(opType->isIntegral() ||
+	   opType->isPointerType() ||
+	   opType == Type::BoolTy && "Ignoring cast: illegal for other types");
     numInstr = 0;
     forwardOperandNum = 0;
     break;
@@ -534,6 +537,7 @@
   }    
   
   case 43:	// boolreg: VReg
+  case 44:	// boolreg: Constant
     numInstr = 0;
     break;
 
@@ -709,6 +713,17 @@
     Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
     break;
     
+  case 64:	// reg:   Phi(reg,reg)
+  {		// This instruction has variable #operands, so resultPos is 0.
+    Instruction* phi = subtreeRoot->getInstruction();
+    mvec[0] = new MachineInstr(PHI, 1 + phi->getNumOperands());
+    mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+			          subtreeRoot->getValue());
+    for (unsigned i=0, N=phi->getNumOperands(); i < N; i++)
+      mvec[0]->SetMachineOperand(i+1, MachineOperand::MO_VirtualRegister,
+				      phi->getOperand(i));
+    break;
+  }  
   case 71:	// reg:     VReg
   case 72:	// reg:     Constant
     numInstr = 0;			// don't forward the value
@@ -730,6 +745,7 @@
   case 131:
   case 132:
   case 153:
+  case 155:
     // 
     // These are all chain rules, which have a single nonterminal on the RHS.
     // Get the rule that matches the RHS non-terminal and use that instead.
@@ -1418,7 +1434,7 @@
       const MachineInstrDescriptor& instrDesc =
 	target.getInstrInfo().getDescriptor(minstr->getOpCode());
       
-      for (unsigned op=0; op < instrDesc.numOperands; op++)
+      for (unsigned op=0; op < minstr->getNumOperands(); op++)
 	{
 	  const MachineOperand& mop = minstr->getOperand(op);