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Jia Liuc5707112012-02-17 08:55:11 +00001//===-- DelaySlotFiller.cpp - Mips Delay Slot Filler ----------------------===//
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +00007//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +00009//
Akira Hatanakaa3defb02011-09-29 23:52:13 +000010// Simple pass to fills delay slots with useful instructions.
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000011//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +000012//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000013
14#define DEBUG_TYPE "delay-slot-filler"
15
16#include "Mips.h"
17#include "MipsTargetMachine.h"
18#include "llvm/CodeGen/MachineFunctionPass.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
Akira Hatanakaa3defb02011-09-29 23:52:13 +000020#include "llvm/Support/CommandLine.h"
21#include "llvm/Target/TargetMachine.h"
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000022#include "llvm/Target/TargetInstrInfo.h"
Akira Hatanakaa3defb02011-09-29 23:52:13 +000023#include "llvm/Target/TargetRegisterInfo.h"
24#include "llvm/ADT/SmallSet.h"
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000025#include "llvm/ADT/Statistic.h"
26
27using namespace llvm;
28
29STATISTIC(FilledSlots, "Number of delay slots filled");
Akira Hatanaka98f4d4d2011-10-05 01:19:13 +000030STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
Akira Hatanaka176965f2011-10-05 02:22:49 +000031 " are not NOP.");
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000032
Akira Hatanakaa3defb02011-09-29 23:52:13 +000033static cl::opt<bool> EnableDelaySlotFiller(
34 "enable-mips-delay-filler",
35 cl::init(false),
Akira Hatanaka6585b512011-10-05 01:06:57 +000036 cl::desc("Fill the Mips delay slots useful instructions."),
Akira Hatanakaa3defb02011-09-29 23:52:13 +000037 cl::Hidden);
38
Akira Hatanakaf9c3f3b2012-05-14 23:59:17 +000039// This option can be used to silence complaints by machine verifier passes.
40static cl::opt<bool> SkipDelaySlotFiller(
41 "skip-mips-delay-filler",
42 cl::init(false),
43 cl::desc("Skip MIPS' delay slot filling pass."),
44 cl::Hidden);
45
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000046namespace {
47 struct Filler : public MachineFunctionPass {
48
49 TargetMachine &TM;
50 const TargetInstrInfo *TII;
Akira Hatanaka53120e02011-10-05 01:30:09 +000051 MachineBasicBlock::iterator LastFiller;
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000052
53 static char ID;
Bruno Cardoso Lopes90c59542010-12-09 17:31:11 +000054 Filler(TargetMachine &tm)
Owen Anderson90c579d2010-08-06 18:33:48 +000055 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000056
57 virtual const char *getPassName() const {
58 return "Mips Delay Slot Filler";
59 }
60
61 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
62 bool runOnMachineFunction(MachineFunction &F) {
Akira Hatanakaf9c3f3b2012-05-14 23:59:17 +000063 if (SkipDelaySlotFiller)
64 return false;
65
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000066 bool Changed = false;
67 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
68 FI != FE; ++FI)
69 Changed |= runOnMachineBasicBlock(*FI);
70 return Changed;
71 }
72
Akira Hatanakaa3defb02011-09-29 23:52:13 +000073 bool isDelayFiller(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator candidate);
75
76 void insertCallUses(MachineBasicBlock::iterator MI,
77 SmallSet<unsigned, 32>& RegDefs,
78 SmallSet<unsigned, 32>& RegUses);
79
80 void insertDefsUses(MachineBasicBlock::iterator MI,
81 SmallSet<unsigned, 32>& RegDefs,
82 SmallSet<unsigned, 32>& RegUses);
83
84 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
85 unsigned Reg);
86
87 bool delayHasHazard(MachineBasicBlock::iterator candidate,
88 bool &sawLoad, bool &sawStore,
89 SmallSet<unsigned, 32> &RegDefs,
90 SmallSet<unsigned, 32> &RegUses);
91
Akira Hatanaka6f818ab2011-10-05 01:23:39 +000092 bool
93 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot,
94 MachineBasicBlock::iterator &Filler);
Akira Hatanakaa3defb02011-09-29 23:52:13 +000095
96
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000097 };
98 char Filler::ID = 0;
99} // end of anonymous namespace
100
101/// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000102/// We assume there is only one delay slot per delayed instruction.
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +0000103bool Filler::
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000104runOnMachineBasicBlock(MachineBasicBlock &MBB) {
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +0000105 bool Changed = false;
Akira Hatanaka53120e02011-10-05 01:30:09 +0000106 LastFiller = MBB.end();
107
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000108 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000109 if (I->hasDelaySlot()) {
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +0000110 ++FilledSlots;
111 Changed = true;
Bruno Cardoso Lopes90c59542010-12-09 17:31:11 +0000112
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000113 MachineBasicBlock::iterator D;
114
115 if (EnableDelaySlotFiller && findDelayInstr(MBB, I, D)) {
116 MBB.splice(llvm::next(I), &MBB, D);
117 ++UsefulSlots;
Jia Liubb481f82012-02-28 07:46:26 +0000118 } else
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000119 BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
120
Akira Hatanaka53120e02011-10-05 01:30:09 +0000121 // Record the filler instruction that filled the delay slot.
122 // The instruction after it will be visited in the next iteration.
123 LastFiller = ++I;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000124 }
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +0000125 return Changed;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000126
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +0000127}
128
129/// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
130/// slots in Mips MachineFunctions
131FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
132 return new Filler(tm);
133}
134
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000135bool Filler::findDelayInstr(MachineBasicBlock &MBB,
136 MachineBasicBlock::iterator slot,
137 MachineBasicBlock::iterator &Filler) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000138 SmallSet<unsigned, 32> RegDefs;
139 SmallSet<unsigned, 32> RegUses;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000140
Akira Hatanaka0f0c59a02011-10-05 02:04:17 +0000141 insertDefsUses(slot, RegDefs, RegUses);
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000142
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000143 bool sawLoad = false;
144 bool sawStore = false;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000145
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000146 for (MachineBasicBlock::reverse_iterator I(slot); I != MBB.rend(); ++I) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000147 // skip debug value
148 if (I->isDebugValue())
149 continue;
150
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000151 // Convert to forward iterator.
NAKAMURA Takumi4cbc5a12011-10-05 10:11:02 +0000152 MachineBasicBlock::iterator FI(llvm::next(I).base());
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000153
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000154 if (I->hasUnmodeledSideEffects()
155 || I->isInlineAsm()
156 || I->isLabel()
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000157 || FI == LastFiller
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000158 || I->isPseudo()
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000159 //
160 // Should not allow:
161 // ERET, DERET or WAIT, PAUSE. Need to add these to instruction
162 // list. TBD.
163 )
164 break;
165
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000166 if (delayHasHazard(FI, sawLoad, sawStore, RegDefs, RegUses)) {
167 insertDefsUses(FI, RegDefs, RegUses);
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000168 continue;
169 }
170
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000171 Filler = FI;
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000172 return true;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000173 }
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000174
175 return false;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000176}
177
178bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
Akira Hatanaka82099682011-12-19 19:52:25 +0000179 bool &sawLoad, bool &sawStore,
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000180 SmallSet<unsigned, 32> &RegDefs,
181 SmallSet<unsigned, 32> &RegUses) {
182 if (candidate->isImplicitDef() || candidate->isKill())
183 return true;
184
Akira Hatanakacfc3fb52011-10-05 01:09:37 +0000185 // Loads or stores cannot be moved past a store to the delay slot
Jia Liubb481f82012-02-28 07:46:26 +0000186 // and stores cannot be moved past a load.
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000187 if (candidate->mayLoad()) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000188 if (sawStore)
189 return true;
Akira Hatanakacfc3fb52011-10-05 01:09:37 +0000190 sawLoad = true;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000191 }
192
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000193 if (candidate->mayStore()) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000194 if (sawStore)
195 return true;
196 sawStore = true;
197 if (sawLoad)
198 return true;
199 }
200
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000201 assert((!candidate->isCall() && !candidate->isReturn()) &&
Akira Hatanaka42be2802011-10-05 18:17:49 +0000202 "Cannot put calls or returns in delay slot.");
Akira Hatanaka0c419a72011-10-05 02:18:58 +0000203
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000204 for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
205 const MachineOperand &MO = candidate->getOperand(i);
Akira Hatanaka0c419a72011-10-05 02:18:58 +0000206 unsigned Reg;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000207
Akira Hatanaka0c419a72011-10-05 02:18:58 +0000208 if (!MO.isReg() || !(Reg = MO.getReg()))
209 continue; // skip
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000210
211 if (MO.isDef()) {
212 // check whether Reg is defined or used before delay slot.
213 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
214 return true;
215 }
216 if (MO.isUse()) {
217 // check whether Reg is defined before delay slot.
218 if (IsRegInSet(RegDefs, Reg))
219 return true;
220 }
221 }
222 return false;
223}
224
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000225// Insert Defs and Uses of MI into the sets RegDefs and RegUses.
226void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
227 SmallSet<unsigned, 32>& RegDefs,
228 SmallSet<unsigned, 32>& RegUses) {
Akira Hatanaka0c419a72011-10-05 02:18:58 +0000229 // If MI is a call or return, just examine the explicit non-variadic operands.
Akira Hatanaka6e4e6482011-10-05 02:21:58 +0000230 MCInstrDesc MCID = MI->getDesc();
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000231 unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() :
232 MI->getNumOperands();
Jia Liubb481f82012-02-28 07:46:26 +0000233
234 // Add RA to RegDefs to prevent users of RA from going into delay slot.
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000235 if (MI->isCall())
Akira Hatanaka2f523382011-10-05 18:11:44 +0000236 RegDefs.insert(Mips::RA);
Akira Hatanaka0f0c59a02011-10-05 02:04:17 +0000237
238 for (unsigned i = 0; i != e; ++i) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000239 const MachineOperand &MO = MI->getOperand(i);
Akira Hatanaka0f0c59a02011-10-05 02:04:17 +0000240 unsigned Reg;
241
242 if (!MO.isReg() || !(Reg = MO.getReg()))
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000243 continue;
244
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000245 if (MO.isDef())
246 RegDefs.insert(Reg);
Akira Hatanaka0f0c59a02011-10-05 02:04:17 +0000247 else if (MO.isUse())
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000248 RegUses.insert(Reg);
249 }
250}
251
252//returns true if the Reg or its alias is in the RegSet.
253bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) {
Jakob Stoklund Olesenf152fe82012-06-01 20:36:54 +0000254 // Check Reg and all aliased Registers.
255 for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
256 AI.isValid(); ++AI)
257 if (RegSet.count(*AI))
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000258 return true;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000259 return false;
260}