Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 1 | //===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===// |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 Register file, defining the registers themselves, |
| 11 | // aliases between the registers, and the register classes built out of the |
| 12 | // registers. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
| 16 | //===----------------------------------------------------------------------===// |
| 17 | // Register definitions... |
| 18 | // |
Chris Lattner | c8f4587 | 2003-08-04 04:59:56 +0000 | [diff] [blame] | 19 | let Namespace = "X86" in { |
Chris Lattner | b228657 | 2004-09-14 04:17:02 +0000 | [diff] [blame] | 20 | |
| 21 | // In the register alias definitions below, we define which registers alias |
| 22 | // which others. We only specify which registers the small registers alias, |
| 23 | // because the register file generator is smart enough to figure out that |
| 24 | // AL aliases AX if we tell it that AX aliased AL (for example). |
| 25 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 26 | // FIXME: X86-64 have different Dwarf numbers. |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 27 | // 8-bit registers |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 28 | // Low registers |
Evan Cheng | 6120433 | 2007-04-20 21:15:21 +0000 | [diff] [blame] | 29 | def AL : Register<"AL">, DwarfRegNum<0>; |
| 30 | def CL : Register<"CL">, DwarfRegNum<1>; |
| 31 | def DL : Register<"DL">, DwarfRegNum<2>; |
| 32 | def BL : Register<"BL">, DwarfRegNum<3>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 33 | |
| 34 | // X86-64 only |
Evan Cheng | 6120433 | 2007-04-20 21:15:21 +0000 | [diff] [blame] | 35 | def SIL : Register<"SIL">, DwarfRegNum<4>; |
| 36 | def DIL : Register<"DIL">, DwarfRegNum<5>; |
| 37 | def BPL : Register<"BPL">, DwarfRegNum<6>; |
| 38 | def SPL : Register<"SPL">, DwarfRegNum<7>; |
| 39 | def R8B : Register<"R8B">, DwarfRegNum<8>; |
| 40 | def R9B : Register<"R9B">, DwarfRegNum<9>; |
| 41 | def R10B : Register<"R10B">, DwarfRegNum<10>; |
| 42 | def R11B : Register<"R11B">, DwarfRegNum<11>; |
| 43 | def R12B : Register<"R12B">, DwarfRegNum<12>; |
| 44 | def R13B : Register<"R13B">, DwarfRegNum<13>; |
| 45 | def R14B : Register<"R14B">, DwarfRegNum<14>; |
| 46 | def R15B : Register<"R15B">, DwarfRegNum<15>; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 47 | |
| 48 | // High registers X86-32 only |
Evan Cheng | 6120433 | 2007-04-20 21:15:21 +0000 | [diff] [blame] | 49 | def AH : Register<"AH">, DwarfRegNum<0>; |
| 50 | def CH : Register<"CH">, DwarfRegNum<1>; |
| 51 | def DH : Register<"DH">, DwarfRegNum<2>; |
| 52 | def BH : Register<"BH">, DwarfRegNum<3>; |
| 53 | |
| 54 | // 16-bit registers |
| 55 | def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<0>; |
| 56 | def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<1>; |
| 57 | def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<2>; |
| 58 | def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<3>; |
| 59 | def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<4>; |
| 60 | def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<5>; |
| 61 | def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<6>; |
| 62 | def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<7>; |
Anton Korobeynikov | 038082d | 2007-05-02 08:46:03 +0000 | [diff] [blame] | 63 | def IP : Register<"IP">, DwarfRegNum<8>; |
Evan Cheng | 6120433 | 2007-04-20 21:15:21 +0000 | [diff] [blame] | 64 | |
| 65 | // X86-64 only |
| 66 | def R8W : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<8>; |
| 67 | def R9W : RegisterWithSubRegs<"R9W", [R9B]>, DwarfRegNum<9>; |
| 68 | def R10W : RegisterWithSubRegs<"R10W", [R10B]>, DwarfRegNum<10>; |
| 69 | def R11W : RegisterWithSubRegs<"R11W", [R11B]>, DwarfRegNum<11>; |
| 70 | def R12W : RegisterWithSubRegs<"R12W", [R12B]>, DwarfRegNum<12>; |
| 71 | def R13W : RegisterWithSubRegs<"R13W", [R13B]>, DwarfRegNum<13>; |
| 72 | def R14W : RegisterWithSubRegs<"R14W", [R14B]>, DwarfRegNum<14>; |
| 73 | def R15W : RegisterWithSubRegs<"R15W", [R15B]>, DwarfRegNum<15>; |
| 74 | |
| 75 | // 32-bit registers |
| 76 | def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<0>; |
| 77 | def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<1>; |
| 78 | def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<2>; |
| 79 | def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<3>; |
| 80 | def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<4>; |
| 81 | def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<5>; |
| 82 | def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<6>; |
| 83 | def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<7>; |
Anton Korobeynikov | 038082d | 2007-05-02 08:46:03 +0000 | [diff] [blame] | 84 | def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<8>; |
Evan Cheng | 6120433 | 2007-04-20 21:15:21 +0000 | [diff] [blame] | 85 | |
| 86 | // X86-64 only |
| 87 | def R8D : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<8>; |
| 88 | def R9D : RegisterWithSubRegs<"R9D", [R9W]>, DwarfRegNum<9>; |
| 89 | def R10D : RegisterWithSubRegs<"R10D", [R10W]>, DwarfRegNum<10>; |
| 90 | def R11D : RegisterWithSubRegs<"R11D", [R11W]>, DwarfRegNum<11>; |
| 91 | def R12D : RegisterWithSubRegs<"R12D", [R12W]>, DwarfRegNum<12>; |
| 92 | def R13D : RegisterWithSubRegs<"R13D", [R13W]>, DwarfRegNum<13>; |
| 93 | def R14D : RegisterWithSubRegs<"R14D", [R14W]>, DwarfRegNum<14>; |
| 94 | def R15D : RegisterWithSubRegs<"R15D", [R15W]>, DwarfRegNum<15>; |
| 95 | |
| 96 | // 64-bit registers, X86-64 only |
| 97 | def RAX : RegisterWithSubRegs<"RAX", [EAX]>, DwarfRegNum<0>; |
| 98 | def RDX : RegisterWithSubRegs<"RDX", [EDX]>, DwarfRegNum<1>; |
| 99 | def RCX : RegisterWithSubRegs<"RCX", [ECX]>, DwarfRegNum<2>; |
| 100 | def RBX : RegisterWithSubRegs<"RBX", [EBX]>, DwarfRegNum<3>; |
| 101 | def RSI : RegisterWithSubRegs<"RSI", [ESI]>, DwarfRegNum<4>; |
| 102 | def RDI : RegisterWithSubRegs<"RDI", [EDI]>, DwarfRegNum<5>; |
| 103 | def RBP : RegisterWithSubRegs<"RBP", [EBP]>, DwarfRegNum<6>; |
| 104 | def RSP : RegisterWithSubRegs<"RSP", [ESP]>, DwarfRegNum<7>; |
| 105 | |
| 106 | def R8 : RegisterWithSubRegs<"R8", [R8D]>, DwarfRegNum<8>; |
| 107 | def R9 : RegisterWithSubRegs<"R9", [R9D]>, DwarfRegNum<9>; |
| 108 | def R10 : RegisterWithSubRegs<"R10", [R10D]>, DwarfRegNum<10>; |
| 109 | def R11 : RegisterWithSubRegs<"R11", [R11D]>, DwarfRegNum<11>; |
| 110 | def R12 : RegisterWithSubRegs<"R12", [R12D]>, DwarfRegNum<12>; |
| 111 | def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<13>; |
| 112 | def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<14>; |
| 113 | def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<15>; |
Anton Korobeynikov | 038082d | 2007-05-02 08:46:03 +0000 | [diff] [blame] | 114 | def RIP : RegisterWithSubRegs<"RIP", [EIP]>, DwarfRegNum<16>; |
Evan Cheng | aea20f5 | 2006-02-20 22:34:53 +0000 | [diff] [blame] | 115 | |
| 116 | // MMX Registers. These are actually aliased to ST0 .. ST7 |
Evan Cheng | e46e1a5 | 2006-08-07 21:02:39 +0000 | [diff] [blame] | 117 | def MM0 : Register<"MM0">, DwarfRegNum<29>; |
| 118 | def MM1 : Register<"MM1">, DwarfRegNum<30>; |
| 119 | def MM2 : Register<"MM2">, DwarfRegNum<31>; |
| 120 | def MM3 : Register<"MM3">, DwarfRegNum<32>; |
| 121 | def MM4 : Register<"MM4">, DwarfRegNum<33>; |
| 122 | def MM5 : Register<"MM5">, DwarfRegNum<34>; |
| 123 | def MM6 : Register<"MM6">, DwarfRegNum<35>; |
| 124 | def MM7 : Register<"MM7">, DwarfRegNum<36>; |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 125 | |
| 126 | // Pseudo Floating Point registers |
Jim Laskey | 47622e3 | 2006-03-24 21:15:58 +0000 | [diff] [blame] | 127 | def FP0 : Register<"FP0">, DwarfRegNum<-1>; |
| 128 | def FP1 : Register<"FP1">, DwarfRegNum<-1>; |
| 129 | def FP2 : Register<"FP2">, DwarfRegNum<-1>; |
| 130 | def FP3 : Register<"FP3">, DwarfRegNum<-1>; |
| 131 | def FP4 : Register<"FP4">, DwarfRegNum<-1>; |
| 132 | def FP5 : Register<"FP5">, DwarfRegNum<-1>; |
| 133 | def FP6 : Register<"FP6">, DwarfRegNum<-1>; |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 134 | |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 135 | // XMM Registers, used by the various SSE instruction set extensions |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 136 | def XMM0: Register<"XMM0">, DwarfRegNum<17>; |
| 137 | def XMM1: Register<"XMM1">, DwarfRegNum<18>; |
| 138 | def XMM2: Register<"XMM2">, DwarfRegNum<19>; |
| 139 | def XMM3: Register<"XMM3">, DwarfRegNum<20>; |
| 140 | def XMM4: Register<"XMM4">, DwarfRegNum<21>; |
| 141 | def XMM5: Register<"XMM5">, DwarfRegNum<22>; |
| 142 | def XMM6: Register<"XMM6">, DwarfRegNum<23>; |
| 143 | def XMM7: Register<"XMM7">, DwarfRegNum<24>; |
| 144 | |
| 145 | // X86-64 only |
| 146 | def XMM8: Register<"XMM8">, DwarfRegNum<25>; |
| 147 | def XMM9: Register<"XMM9">, DwarfRegNum<26>; |
| 148 | def XMM10: Register<"XMM10">, DwarfRegNum<27>; |
| 149 | def XMM11: Register<"XMM11">, DwarfRegNum<28>; |
| 150 | def XMM12: Register<"XMM12">, DwarfRegNum<29>; |
| 151 | def XMM13: Register<"XMM13">, DwarfRegNum<30>; |
| 152 | def XMM14: Register<"XMM14">, DwarfRegNum<31>; |
| 153 | def XMM15: Register<"XMM15">, DwarfRegNum<32>; |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 154 | |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 155 | // Floating point stack registers |
Evan Cheng | e46e1a5 | 2006-08-07 21:02:39 +0000 | [diff] [blame] | 156 | def ST0 : Register<"ST(0)">, DwarfRegNum<11>; |
| 157 | def ST1 : Register<"ST(1)">, DwarfRegNum<12>; |
| 158 | def ST2 : Register<"ST(2)">, DwarfRegNum<13>; |
| 159 | def ST3 : Register<"ST(3)">, DwarfRegNum<14>; |
| 160 | def ST4 : Register<"ST(4)">, DwarfRegNum<15>; |
| 161 | def ST5 : Register<"ST(5)">, DwarfRegNum<16>; |
| 162 | def ST6 : Register<"ST(6)">, DwarfRegNum<17>; |
| 163 | def ST7 : Register<"ST(7)">, DwarfRegNum<18>; |
Evan Cheng | 3054dde | 2007-09-11 19:53:28 +0000 | [diff] [blame^] | 164 | |
| 165 | // Status flags register |
| 166 | def EFLAGS : Register<"EFLAGS">; |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 167 | } |
| 168 | |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 169 | |
| 170 | //===----------------------------------------------------------------------===// |
| 171 | // Subregister Set Definitions... now that we have all of the pieces, define the |
| 172 | // sub registers for each register. |
| 173 | // |
| 174 | |
| 175 | def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI, |
| 176 | R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], |
| 177 | [AL, CL, DL, BL, SPL, BPL, SIL, DIL, |
| 178 | R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; |
| 179 | |
| 180 | // It's unclear if this subreg set is safe, given that not all registers |
| 181 | // in the class have an 'H' subreg. |
| 182 | // def : SubRegSet<2, [AX, CX, DX, BX], |
| 183 | // [AH, CH, DH, BH]>; |
| 184 | |
| 185 | def : SubRegSet<1, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI, |
| 186 | R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D], |
| 187 | [AL, CL, DL, BL, SPL, BPL, SIL, DIL, |
| 188 | R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; |
| 189 | |
| 190 | def : SubRegSet<2, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI, |
| 191 | R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D], |
| 192 | [AX, CX, DX, BX, SP, BP, SI, DI, |
| 193 | R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>; |
| 194 | |
| 195 | |
| 196 | def : SubRegSet<1, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, |
| 197 | R8, R9, R10, R11, R12, R13, R14, R15], |
| 198 | [AL, CL, DL, BL, SPL, BPL, SIL, DIL, |
| 199 | R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; |
| 200 | |
| 201 | def : SubRegSet<2, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, |
| 202 | R8, R9, R10, R11, R12, R13, R14, R15], |
| 203 | [AX, CX, DX, BX, SP, BP, SI, DI, |
| 204 | R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>; |
| 205 | |
| 206 | def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI, |
| 207 | R8, R9, R10, R11, R12, R13, R14, R15], |
| 208 | [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI, |
| 209 | R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>; |
| 210 | |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 211 | //===----------------------------------------------------------------------===// |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 212 | // Register Class Definitions... now that we have all of the pieces, define the |
| 213 | // top-level register classes. The order specified in the register list is |
| 214 | // implicitly defined to be the register allocation order. |
| 215 | // |
Chris Lattner | 0539313 | 2005-01-05 16:09:16 +0000 | [diff] [blame] | 216 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 217 | // List call-clobbered registers before callee-save registers. RBX, RBP, (and |
| 218 | // R12, R13, R14, and R15 for X86-64) are callee-save registers. |
| 219 | // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and |
| 220 | // R8B, ... R15B. |
| 221 | // FIXME: Allow AH, CH, DH, BH in 64-mode for non-REX instructions, |
| 222 | def GR8 : RegisterClass<"X86", [i8], 8, |
| 223 | [AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL, |
| 224 | R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]> { |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 225 | let MethodProtos = [{ |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 226 | iterator allocation_order_begin(const MachineFunction &MF) const; |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 227 | iterator allocation_order_end(const MachineFunction &MF) const; |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 228 | }]; |
| 229 | let MethodBodies = [{ |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 230 | // Does the function dedicate RBP / EBP to being a frame ptr? |
| 231 | // If so, don't allocate SPL or BPL. |
| 232 | static const unsigned X86_GR8_AO_64_fp[] = |
| 233 | {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, |
| 234 | X86::R8B, X86::R9B, X86::R10B, X86::R11B, |
| 235 | X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B}; |
| 236 | // If not, just don't allocate SPL. |
| 237 | static const unsigned X86_GR8_AO_64[] = |
| 238 | {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL, |
| 239 | X86::R8B, X86::R9B, X86::R10B, X86::R11B, |
| 240 | X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL}; |
| 241 | // In 32-mode, none of the 8-bit registers aliases EBP or ESP. |
| 242 | static const unsigned X86_GR8_AO_32[] = |
| 243 | {X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH}; |
| 244 | |
| 245 | GR8Class::iterator |
| 246 | GR8Class::allocation_order_begin(const MachineFunction &MF) const { |
| 247 | const TargetMachine &TM = MF.getTarget(); |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 248 | const MRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 249 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 250 | if (!Subtarget.is64Bit()) |
| 251 | return X86_GR8_AO_32; |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 252 | else if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 253 | return X86_GR8_AO_64_fp; |
| 254 | else |
| 255 | return X86_GR8_AO_64; |
| 256 | } |
| 257 | |
| 258 | GR8Class::iterator |
| 259 | GR8Class::allocation_order_end(const MachineFunction &MF) const { |
| 260 | const TargetMachine &TM = MF.getTarget(); |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 261 | const MRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 262 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 263 | if (!Subtarget.is64Bit()) |
| 264 | return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned)); |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 265 | else if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 266 | return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned)); |
| 267 | else |
| 268 | return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned)); |
| 269 | } |
| 270 | }]; |
| 271 | } |
| 272 | |
| 273 | |
| 274 | def GR16 : RegisterClass<"X86", [i16], 16, |
| 275 | [AX, CX, DX, SI, DI, BX, BP, SP, |
| 276 | R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]> { |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 277 | let SubRegClassList = [GR8]; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 278 | let MethodProtos = [{ |
| 279 | iterator allocation_order_begin(const MachineFunction &MF) const; |
| 280 | iterator allocation_order_end(const MachineFunction &MF) const; |
| 281 | }]; |
| 282 | let MethodBodies = [{ |
| 283 | // Does the function dedicate RBP / EBP to being a frame ptr? |
| 284 | // If so, don't allocate SP or BP. |
| 285 | static const unsigned X86_GR16_AO_64_fp[] = |
| 286 | {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, |
| 287 | X86::R8W, X86::R9W, X86::R10W, X86::R11W, |
| 288 | X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W}; |
| 289 | static const unsigned X86_GR16_AO_32_fp[] = |
| 290 | {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX}; |
| 291 | // If not, just don't allocate SPL. |
| 292 | static const unsigned X86_GR16_AO_64[] = |
| 293 | {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, |
| 294 | X86::R8W, X86::R9W, X86::R10W, X86::R11W, |
| 295 | X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP}; |
| 296 | static const unsigned X86_GR16_AO_32[] = |
| 297 | {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP}; |
| 298 | |
| 299 | GR16Class::iterator |
| 300 | GR16Class::allocation_order_begin(const MachineFunction &MF) const { |
| 301 | const TargetMachine &TM = MF.getTarget(); |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 302 | const MRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 303 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 304 | if (Subtarget.is64Bit()) { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 305 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 306 | return X86_GR16_AO_64_fp; |
| 307 | else |
| 308 | return X86_GR16_AO_64; |
| 309 | } else { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 310 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 311 | return X86_GR16_AO_32_fp; |
| 312 | else |
| 313 | return X86_GR16_AO_32; |
| 314 | } |
| 315 | } |
| 316 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 317 | GR16Class::iterator |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 318 | GR16Class::allocation_order_end(const MachineFunction &MF) const { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 319 | const TargetMachine &TM = MF.getTarget(); |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 320 | const MRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 321 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 322 | if (Subtarget.is64Bit()) { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 323 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 324 | return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned)); |
| 325 | else |
| 326 | return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned)); |
| 327 | } else { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 328 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 329 | return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned)); |
| 330 | else |
| 331 | return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned)); |
| 332 | } |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 333 | } |
| 334 | }]; |
| 335 | } |
| 336 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 337 | |
Evan Cheng | 069287d | 2006-05-16 07:21:53 +0000 | [diff] [blame] | 338 | def GR32 : RegisterClass<"X86", [i32], 32, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 339 | [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, |
| 340 | R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]> { |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 341 | let SubRegClassList = [GR8, GR16]; |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 342 | let MethodProtos = [{ |
| 343 | iterator allocation_order_begin(const MachineFunction &MF) const; |
| 344 | iterator allocation_order_end(const MachineFunction &MF) const; |
| 345 | }]; |
| 346 | let MethodBodies = [{ |
| 347 | // Does the function dedicate RBP / EBP to being a frame ptr? |
| 348 | // If so, don't allocate ESP or EBP. |
| 349 | static const unsigned X86_GR32_AO_64_fp[] = |
| 350 | {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, |
| 351 | X86::R8D, X86::R9D, X86::R10D, X86::R11D, |
| 352 | X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D}; |
| 353 | static const unsigned X86_GR32_AO_32_fp[] = |
| 354 | {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX}; |
| 355 | // If not, just don't allocate SPL. |
| 356 | static const unsigned X86_GR32_AO_64[] = |
| 357 | {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, |
| 358 | X86::R8D, X86::R9D, X86::R10D, X86::R11D, |
| 359 | X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP}; |
| 360 | static const unsigned X86_GR32_AO_32[] = |
| 361 | {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP}; |
| 362 | |
| 363 | GR32Class::iterator |
| 364 | GR32Class::allocation_order_begin(const MachineFunction &MF) const { |
| 365 | const TargetMachine &TM = MF.getTarget(); |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 366 | const MRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 367 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 368 | if (Subtarget.is64Bit()) { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 369 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 370 | return X86_GR32_AO_64_fp; |
| 371 | else |
| 372 | return X86_GR32_AO_64; |
| 373 | } else { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 374 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 375 | return X86_GR32_AO_32_fp; |
| 376 | else |
| 377 | return X86_GR32_AO_32; |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | GR32Class::iterator |
| 382 | GR32Class::allocation_order_end(const MachineFunction &MF) const { |
| 383 | const TargetMachine &TM = MF.getTarget(); |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 384 | const MRegisterInfo *RI = TM.getRegisterInfo(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 385 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 386 | if (Subtarget.is64Bit()) { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 387 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 388 | return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned)); |
| 389 | else |
| 390 | return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned)); |
| 391 | } else { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 392 | if (RI->hasFP(MF)) |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 393 | return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned)); |
| 394 | else |
| 395 | return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned)); |
| 396 | } |
| 397 | } |
| 398 | }]; |
| 399 | } |
| 400 | |
| 401 | |
| 402 | def GR64 : RegisterClass<"X86", [i64], 64, |
| 403 | [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, |
| 404 | RBX, R14, R15, R12, R13, RBP, RSP]> { |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 405 | let SubRegClassList = [GR8, GR16, GR32]; |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 406 | let MethodProtos = [{ |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 407 | iterator allocation_order_end(const MachineFunction &MF) const; |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 408 | }]; |
| 409 | let MethodBodies = [{ |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 410 | GR64Class::iterator |
| 411 | GR64Class::allocation_order_end(const MachineFunction &MF) const { |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 412 | const TargetMachine &TM = MF.getTarget(); |
| 413 | const MRegisterInfo *RI = TM.getRegisterInfo(); |
| 414 | if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr? |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 415 | return end()-2; // If so, don't allocate RSP or RBP |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 416 | else |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 417 | return end()-1; // If not, just don't allocate RSP |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 418 | } |
| 419 | }]; |
| 420 | } |
| 421 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 422 | |
Evan Cheng | a333b41 | 2007-08-09 18:05:17 +0000 | [diff] [blame] | 423 | // GR16, GR32 subclasses which contain registers that have GR8 sub-registers. |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 424 | // These should only be used for 32-bit mode. |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 425 | def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> { |
Evan Cheng | a3231ba | 2007-08-09 22:25:35 +0000 | [diff] [blame] | 426 | let SubRegClassList = [GR8]; |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 427 | } |
| 428 | def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> { |
Evan Cheng | a3231ba | 2007-08-09 22:25:35 +0000 | [diff] [blame] | 429 | let SubRegClassList = [GR8, GR16]; |
Christopher Lamb | f9b90ea | 2007-07-28 19:03:30 +0000 | [diff] [blame] | 430 | } |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 431 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 432 | // Scalar SSE2 floating point registers. |
| 433 | def FR32 : RegisterClass<"X86", [f32], 32, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 434 | [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
| 435 | XMM8, XMM9, XMM10, XMM11, |
| 436 | XMM12, XMM13, XMM14, XMM15]> { |
| 437 | let MethodProtos = [{ |
| 438 | iterator allocation_order_end(const MachineFunction &MF) const; |
| 439 | }]; |
| 440 | let MethodBodies = [{ |
| 441 | FR32Class::iterator |
| 442 | FR32Class::allocation_order_end(const MachineFunction &MF) const { |
| 443 | const TargetMachine &TM = MF.getTarget(); |
| 444 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 445 | if (!Subtarget.is64Bit()) |
| 446 | return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode. |
| 447 | else |
| 448 | return end(); |
| 449 | } |
| 450 | }]; |
| 451 | } |
| 452 | |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 453 | def FR64 : RegisterClass<"X86", [f64], 64, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 454 | [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
| 455 | XMM8, XMM9, XMM10, XMM11, |
| 456 | XMM12, XMM13, XMM14, XMM15]> { |
| 457 | let MethodProtos = [{ |
| 458 | iterator allocation_order_end(const MachineFunction &MF) const; |
| 459 | }]; |
| 460 | let MethodBodies = [{ |
| 461 | FR64Class::iterator |
| 462 | FR64Class::allocation_order_end(const MachineFunction &MF) const { |
| 463 | const TargetMachine &TM = MF.getTarget(); |
| 464 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 465 | if (!Subtarget.is64Bit()) |
| 466 | return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode. |
| 467 | else |
| 468 | return end(); |
| 469 | } |
| 470 | }]; |
| 471 | } |
| 472 | |
Nate Begeman | f1702ac | 2005-06-27 21:20:31 +0000 | [diff] [blame] | 473 | |
Chris Lattner | 45de191 | 2004-12-02 18:17:31 +0000 | [diff] [blame] | 474 | // FIXME: This sets up the floating point register files as though they are f64 |
| 475 | // values, though they really are f80 values. This will cause us to spill |
| 476 | // values as 64-bit quantities instead of 80-bit quantities, which is much much |
| 477 | // faster on common hardware. In reality, this should be controlled by a |
| 478 | // command line option or something. |
| 479 | |
Dale Johannesen | 849f214 | 2007-07-03 00:53:03 +0000 | [diff] [blame] | 480 | def RFP32 : RegisterClass<"X86", [f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>; |
| 481 | def RFP64 : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>; |
Dale Johannesen | 59a5873 | 2007-08-05 18:49:15 +0000 | [diff] [blame] | 482 | def RFP80 : RegisterClass<"X86", [f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>; |
Chris Lattner | b76d6fc | 2003-08-03 15:47:25 +0000 | [diff] [blame] | 483 | |
Alkis Evlogimenos | 65cbfa0 | 2004-09-21 21:22:11 +0000 | [diff] [blame] | 484 | // Floating point stack registers (these are not allocatable by the |
| 485 | // register allocator - the floating point stackifier is responsible |
| 486 | // for transforming FPn allocations to STn registers) |
Nate Begeman | 6510b22 | 2005-12-01 04:51:06 +0000 | [diff] [blame] | 487 | def RST : RegisterClass<"X86", [f64], 32, |
Chris Lattner | 03ba7b9 | 2005-08-19 18:51:57 +0000 | [diff] [blame] | 488 | [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> { |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 489 | let MethodProtos = [{ |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 490 | iterator allocation_order_end(const MachineFunction &MF) const; |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 491 | }]; |
| 492 | let MethodBodies = [{ |
| 493 | RSTClass::iterator |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 494 | RSTClass::allocation_order_end(const MachineFunction &MF) const { |
Alkis Evlogimenos | 65cbfa0 | 2004-09-21 21:22:11 +0000 | [diff] [blame] | 495 | return begin(); |
| 496 | } |
| 497 | }]; |
| 498 | } |
Evan Cheng | aea20f5 | 2006-02-20 22:34:53 +0000 | [diff] [blame] | 499 | |
Evan Cheng | 933be33 | 2006-02-21 01:38:21 +0000 | [diff] [blame] | 500 | // Generic vector registers: VR64 and VR128. |
Bill Wendling | eebc8a1 | 2007-03-26 07:53:08 +0000 | [diff] [blame] | 501 | def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64], 64, |
Evan Cheng | 933be33 | 2006-02-21 01:38:21 +0000 | [diff] [blame] | 502 | [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>; |
| 503 | def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 504 | [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
| 505 | XMM8, XMM9, XMM10, XMM11, |
| 506 | XMM12, XMM13, XMM14, XMM15]> { |
| 507 | let MethodProtos = [{ |
| 508 | iterator allocation_order_end(const MachineFunction &MF) const; |
| 509 | }]; |
| 510 | let MethodBodies = [{ |
| 511 | VR128Class::iterator |
| 512 | VR128Class::allocation_order_end(const MachineFunction &MF) const { |
| 513 | const TargetMachine &TM = MF.getTarget(); |
| 514 | const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); |
| 515 | if (!Subtarget.is64Bit()) |
| 516 | return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode. |
| 517 | else |
| 518 | return end(); |
| 519 | } |
| 520 | }]; |
| 521 | } |
Evan Cheng | 3054dde | 2007-09-11 19:53:28 +0000 | [diff] [blame^] | 522 | |
| 523 | // Status flags registers. |
| 524 | def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]>; |