| Owen Anderson | 3132520 | 2010-10-22 23:21:04 +0000 | [diff] [blame^] | 1 | ; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s |
| 2 | |
| 3 | ; CHECK: vsub_8xi8 |
| 4 | define <8 x i8> @vsub_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { |
| 5 | %tmp1 = load <8 x i8>* %A |
| 6 | %tmp2 = load <8 x i8>* %B |
| 7 | ; CHECK: vsub.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf3] |
| 8 | %tmp3 = sub <8 x i8> %tmp1, %tmp2 |
| 9 | ret <8 x i8> %tmp3 |
| 10 | } |
| 11 | |
| 12 | ; CHECK: vsub_4xi16 |
| 13 | define <4 x i16> @vsub_4xi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { |
| 14 | %tmp1 = load <4 x i16>* %A |
| 15 | %tmp2 = load <4 x i16>* %B |
| 16 | ; CHECK: vsub.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf3] |
| 17 | %tmp3 = sub <4 x i16> %tmp1, %tmp2 |
| 18 | ret <4 x i16> %tmp3 |
| 19 | } |
| 20 | |
| 21 | ; CHECK: vsub_2xi32 |
| 22 | define <2 x i32> @vsub_2xi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { |
| 23 | %tmp1 = load <2 x i32>* %A |
| 24 | ; CHECK: vsub.i32 d16, d17, d16 @ encoding: [0xa0,0x08,0x61,0xf3] |
| 25 | %tmp2 = load <2 x i32>* %B |
| 26 | %tmp3 = sub <2 x i32> %tmp1, %tmp2 |
| 27 | ret <2 x i32> %tmp3 |
| 28 | } |
| 29 | |
| 30 | ; CHECK: vsub_1xi64 |
| 31 | define <1 x i64> @vsub_1xi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { |
| 32 | %tmp1 = load <1 x i64>* %A |
| 33 | %tmp2 = load <1 x i64>* %B |
| 34 | ; CHECK: vsub.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf3] |
| 35 | %tmp3 = sub <1 x i64> %tmp1, %tmp2 |
| 36 | ret <1 x i64> %tmp3 |
| 37 | } |
| 38 | |
| 39 | ; CHECK: vsub_2xifloat |
| 40 | define <2 x float> @vsub_2xifloat(<2 x float>* %A, <2 x float>* %B) nounwind { |
| 41 | %tmp1 = load <2 x float>* %A |
| 42 | %tmp2 = load <2 x float>* %B |
| 43 | ; CHECK: vsub.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xf2] |
| 44 | %tmp3 = fsub <2 x float> %tmp1, %tmp2 |
| 45 | ret <2 x float> %tmp3 |
| 46 | } |
| 47 | |
| 48 | ; CHECK: vsub_16xi8 |
| 49 | define <16 x i8> @vsub_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { |
| 50 | %tmp1 = load <16 x i8>* %A |
| 51 | %tmp2 = load <16 x i8>* %B |
| 52 | ; CHECK: vsub.i8 q8, q8, q9 @ encoding: [0xe2,0x08,0x40,0xf3] |
| 53 | %tmp3 = sub <16 x i8> %tmp1, %tmp2 |
| 54 | ret <16 x i8> %tmp3 |
| 55 | } |
| 56 | |
| 57 | ; CHECK: vsub_8xi16 |
| 58 | define <8 x i16> @vsub_8xi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { |
| 59 | %tmp1 = load <8 x i16>* %A |
| 60 | %tmp2 = load <8 x i16>* %B |
| 61 | ; CHECK: vsub.i16 q8, q8, q9 @ encoding: [0xe2,0x08,0x50,0xf3] |
| 62 | %tmp3 = sub <8 x i16> %tmp1, %tmp2 |
| 63 | ret <8 x i16> %tmp3 |
| 64 | } |
| 65 | |
| 66 | ; CHECK: vsub_4xi32 |
| 67 | define <4 x i32> @vsub_4xi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { |
| 68 | %tmp1 = load <4 x i32>* %A |
| 69 | %tmp2 = load <4 x i32>* %B |
| 70 | ; CHECK: vsub.i32 q8, q8, q9 @ encoding: [0xe2,0x08,0x60,0xf3] |
| 71 | %tmp3 = sub <4 x i32> %tmp1, %tmp2 |
| 72 | ret <4 x i32> %tmp3 |
| 73 | } |
| 74 | |
| 75 | ; CHECK: vsub_2xi64 |
| 76 | define <2 x i64> @vsub_2xi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { |
| 77 | %tmp1 = load <2 x i64>* %A |
| 78 | %tmp2 = load <2 x i64>* %B |
| 79 | ; CHECK: vsub.i64 q8, q8, q9 @ encoding: [0xe2,0x08,0x70,0xf3] |
| 80 | %tmp3 = sub <2 x i64> %tmp1, %tmp2 |
| 81 | ret <2 x i64> %tmp3 |
| 82 | } |
| 83 | |
| 84 | ; CHECK: vsub_4xfloat |
| 85 | define <4 x float> @vsub_4xfloat(<4 x float>* %A, <4 x float>* %B) nounwind { |
| 86 | %tmp1 = load <4 x float>* %A |
| 87 | %tmp2 = load <4 x float>* %B |
| 88 | ; CHECK: vsub.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xf2] |
| 89 | %tmp3 = fsub <4 x float> %tmp1, %tmp2 |
| 90 | ret <4 x float> %tmp3 |
| 91 | } |