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Evan Cheng78a9f132011-07-06 22:02:34 +00001//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides ARM specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMMCTARGETDESC_H
15#define ARMMCTARGETDESC_H
16
NAKAMURA Takumi883d99f2011-07-23 01:16:22 +000017#include "llvm/Support/DataTypes.h"
Evan Cheng94ca42f2011-07-07 00:08:19 +000018#include <string>
19
Evan Cheng78a9f132011-07-06 22:02:34 +000020namespace llvm {
Evan Cheng78c10ee2011-07-25 23:24:55 +000021class MCAsmBackend;
Evan Chengbe740292011-07-23 00:00:19 +000022class MCCodeEmitter;
23class MCContext;
24class MCInstrInfo;
25class MCObjectWriter;
Evan Chengebdeeab2011-07-08 01:53:10 +000026class MCSubtargetInfo;
Evan Cheng94ca42f2011-07-07 00:08:19 +000027class StringRef;
Evan Chengbe740292011-07-23 00:00:19 +000028class Target;
Evan Chengbe740292011-07-23 00:00:19 +000029class raw_ostream;
Evan Cheng78a9f132011-07-06 22:02:34 +000030
31extern Target TheARMTarget, TheThumbTarget;
Evan Cheng94ca42f2011-07-07 00:08:19 +000032
33namespace ARM_MC {
Evan Chengdb068732011-07-07 08:26:46 +000034 std::string ParseARMTriple(StringRef TT);
Evan Chengebdeeab2011-07-08 01:53:10 +000035
36 /// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
37 /// This is exposed so Asm parser, etc. do not need to go through
38 /// TargetRegistry.
39 MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
40 StringRef FS);
Evan Cheng94ca42f2011-07-07 00:08:19 +000041}
42
Evan Chengbe740292011-07-23 00:00:19 +000043MCCodeEmitter *createARMMCCodeEmitter(const MCInstrInfo &MCII,
44 const MCSubtargetInfo &STI,
45 MCContext &Ctx);
46
Evan Cheng78c10ee2011-07-25 23:24:55 +000047MCAsmBackend *createARMAsmBackend(const Target &T, StringRef TT);
Evan Chengbe740292011-07-23 00:00:19 +000048
49/// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
50MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
51 bool Is64Bit,
52 uint32_t CPUType,
53 uint32_t CPUSubtype);
54
Evan Cheng78a9f132011-07-06 22:02:34 +000055} // End llvm namespace
56
57// Defines symbolic names for ARM registers. This defines a mapping from
58// register name to register number.
59//
60#define GET_REGINFO_ENUM
61#include "ARMGenRegisterInfo.inc"
62
63// Defines symbolic names for the ARM instructions.
64//
65#define GET_INSTRINFO_ENUM
66#include "ARMGenInstrInfo.inc"
67
Evan Chengc60f9b72011-07-14 20:59:42 +000068#define GET_SUBTARGETINFO_ENUM
69#include "ARMGenSubtargetInfo.inc"
70
Evan Cheng78a9f132011-07-06 22:02:34 +000071#endif