Sanjiv Gupta | 0e68771 | 2008-05-13 09:02:57 +0000 | [diff] [blame] | 1 | //===- PIC16InstrInfo.h - PIC16 Instruction Information----------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the niversity of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the PIC16 implementation of the TargetInstrInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef PIC16INSTRUCTIONINFO_H |
| 15 | #define PIC16INSTRUCTIONINFO_H |
| 16 | |
| 17 | #include "PIC16.h" |
| 18 | #include "PIC16RegisterInfo.h" |
| 19 | #include "llvm/Target/TargetInstrInfo.h" |
| 20 | |
| 21 | namespace llvm { |
| 22 | |
| 23 | |
| 24 | class PIC16InstrInfo : public TargetInstrInfoImpl |
| 25 | { |
| 26 | PIC16TargetMachine &TM; |
| 27 | const PIC16RegisterInfo RI; |
| 28 | public: |
| 29 | explicit PIC16InstrInfo(PIC16TargetMachine &TM); |
| 30 | |
| 31 | /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As |
| 32 | /// such, whenever a client has an instance of instruction info, it should |
| 33 | /// always be able to get register info as well (through this method). |
| 34 | /// |
Dan Gohman | c9f5f3f | 2008-05-14 01:58:56 +0000 | [diff] [blame] | 35 | virtual const PIC16RegisterInfo &getRegisterInfo() const { return RI; } |
Sanjiv Gupta | 0e68771 | 2008-05-13 09:02:57 +0000 | [diff] [blame] | 36 | |
| 37 | |
| 38 | /// isLoadFromStackSlot - If the specified machine instruction is a direct |
| 39 | /// load from a stack slot, return the virtual or physical register number of |
| 40 | /// the destination along with the FrameIndex of the loaded stack slot. If |
| 41 | /// not, return 0. This predicate must return 0 if the instruction has |
| 42 | /// any side effects other than loading from the stack slot. |
| 43 | virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; |
| 44 | |
| 45 | /// isStoreToStackSlot - If the specified machine instruction is a direct |
| 46 | /// store to a stack slot, return the virtual or physical register number of |
| 47 | /// the source reg along with the FrameIndex of the loaded stack slot. If |
| 48 | /// not, return 0. This predicate must return 0 if the instruction has |
| 49 | /// any side effects other than storing to the stack slot. |
| 50 | virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; |
| 51 | |
| 52 | /// Used for spilling a register |
| 53 | void storeRegToStackSlot(MachineBasicBlock &MBB, |
| 54 | MachineBasicBlock::iterator MI, |
| 55 | unsigned SrcReg, bool isKill, int FrameIndex, |
| 56 | const TargetRegisterClass *RC) const; |
| 57 | |
| 58 | |
| 59 | void loadRegFromStackSlot(MachineBasicBlock &MBB, |
| 60 | MachineBasicBlock::iterator MI, |
| 61 | unsigned DestReg, int FrameIndex, |
| 62 | const TargetRegisterClass *RC) const; |
| 63 | |
| 64 | /// InsertBranch - Insert a branch into the end of the specified |
| 65 | /// MachineBasicBlock. This operands to this method are the same as those |
| 66 | /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch |
| 67 | /// returns success and when an unconditional branch (TBB is non-null, FBB is |
| 68 | /// null, Cond is empty) needs to be inserted. It returns the number of |
| 69 | /// instructions inserted. |
| 70 | virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
| 71 | MachineBasicBlock *FBB, |
Owen Anderson | 44eb65c | 2008-08-14 22:49:33 +0000 | [diff] [blame^] | 72 | const SmallVectorImpl<MachineOperand> &Cond) const ; |
Sanjiv Gupta | 0e68771 | 2008-05-13 09:02:57 +0000 | [diff] [blame] | 73 | |
| 74 | }; |
| 75 | |
| 76 | } // namespace llvm |
| 77 | |
| 78 | #endif |