blob: f84774d9b615900497bc379b3581cbd67b17f94c [file] [log] [blame]
Bob Wilson13e80bd2009-10-27 05:50:28 +00001; RUN: llc < %s -march=arm | FileCheck %s
Evan Cheng1e249e32009-06-25 20:59:23 +00002
3define i64 @f1(i64 %a, i64 %b) {
Bob Wilson13e80bd2009-10-27 05:50:28 +00004; CHECK: f1:
5; CHECK: subs r
6; CHECK: sbc r
Evan Cheng1e249e32009-06-25 20:59:23 +00007entry:
8 %tmp = sub i64 %a, %b
9 ret i64 %tmp
10}
11
12define i64 @f2(i64 %a, i64 %b) {
Bob Wilson13e80bd2009-10-27 05:50:28 +000013; CHECK: f2:
14; CHECK: adc r
15; CHECK: subs r
16; CHECK: sbc r
Evan Cheng1e249e32009-06-25 20:59:23 +000017entry:
18 %tmp1 = shl i64 %a, 1
19 %tmp2 = sub i64 %tmp1, %b
20 ret i64 %tmp2
21}
Andrew Trick1c3af772011-04-23 03:55:32 +000022
23; add with live carry
24define i64 @f3(i32 %al, i32 %bl) {
25; CHECK: f3:
26; CHECK: adds r
Andrew Trick1c3af772011-04-23 03:55:32 +000027; CHECK: adc r
28entry:
29 ; unsigned wide add
30 %aw = zext i32 %al to i64
31 %bw = zext i32 %bl to i64
32 %cw = add i64 %aw, %bw
33 ; ch == carry bit
34 %ch = lshr i64 %cw, 32
35 %dw = add i64 %ch, %bw
36 ret i64 %dw
37}
Evan Cheng4a517082011-09-06 18:52:20 +000038
39; rdar://10073745
40define i64 @f4(i64 %x) nounwind readnone {
41entry:
42; CHECK: f4:
43; CHECK: rsbs r
44; CHECK: rsc r
45 %0 = sub nsw i64 0, %x
46 ret i64 %0
47}