| Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 1 | //===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | // Target-independent interfaces which we are implementing |
| 15 | //===----------------------------------------------------------------------===// |
| 16 | |
| 17 | include "../Target.td" |
| 18 | |
| 19 | //===----------------------------------------------------------------------===// |
| Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 20 | // ARM Subtarget features. |
| 21 | // |
| 22 | |
| 23 | def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T", |
| 24 | "ARM v4T">; |
| 25 | def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T", |
| 26 | "ARM v5T">; |
| 27 | def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE", |
| 28 | "ARM v5TE, v5TEj, v5TExp">; |
| 29 | def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6", |
| 30 | "ARM v6">; |
| 31 | def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFP2", "true", |
| 32 | "Enable VFP2 instructions ">; |
| 33 | |
| 34 | //===----------------------------------------------------------------------===// |
| 35 | // ARM Processors supported. |
| 36 | // |
| 37 | |
| 38 | class Proc<string Name, list<SubtargetFeature> Features> |
| 39 | : Processor<Name, NoItineraries, Features>; |
| 40 | |
| 41 | // V4 Processors. |
| 42 | def : Proc<"generic", []>; |
| 43 | def : Proc<"arm8", []>; |
| 44 | def : Proc<"arm810", []>; |
| 45 | def : Proc<"strongarm", []>; |
| 46 | def : Proc<"strongarm110", []>; |
| 47 | def : Proc<"strongarm1100", []>; |
| 48 | def : Proc<"strongarm1110", []>; |
| 49 | |
| 50 | // V4T Processors. |
| 51 | def : Proc<"arm7tdmi", [ArchV4T]>; |
| 52 | def : Proc<"arm7tdmi-s", [ArchV4T]>; |
| 53 | def : Proc<"arm710t", [ArchV4T]>; |
| 54 | def : Proc<"arm720t", [ArchV4T]>; |
| 55 | def : Proc<"arm9", [ArchV4T]>; |
| 56 | def : Proc<"arm9tdmi", [ArchV4T]>; |
| 57 | def : Proc<"arm920", [ArchV4T]>; |
| 58 | def : Proc<"arm920t", [ArchV4T]>; |
| 59 | def : Proc<"arm922t", [ArchV4T]>; |
| 60 | def : Proc<"arm940t", [ArchV4T]>; |
| 61 | def : Proc<"ep9312", [ArchV4T]>; |
| 62 | |
| 63 | // V5T Processors. |
| 64 | def : Proc<"arm10tdmi", [ArchV5T]>; |
| 65 | def : Proc<"arm1020t", [ArchV5T]>; |
| 66 | |
| 67 | // V5TE Processors. |
| 68 | def : Proc<"arm9e", [ArchV5TE]>; |
| Lauro Ramos Venancio | a8e9562 | 2007-05-04 22:16:30 +0000 | [diff] [blame] | 69 | def : Proc<"arm926ej-s", [ArchV5TE]>; |
| Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 70 | def : Proc<"arm946e-s", [ArchV5TE]>; |
| 71 | def : Proc<"arm966e-s", [ArchV5TE]>; |
| 72 | def : Proc<"arm968e-s", [ArchV5TE]>; |
| 73 | def : Proc<"arm10e", [ArchV5TE]>; |
| 74 | def : Proc<"arm1020e", [ArchV5TE]>; |
| 75 | def : Proc<"arm1022e", [ArchV5TE]>; |
| 76 | def : Proc<"xscale", [ArchV5TE]>; |
| 77 | def : Proc<"iwmmxt", [ArchV5TE]>; |
| 78 | |
| 79 | // V6 Processors. |
| 80 | def : Proc<"arm1136j-s", [ArchV6]>; |
| 81 | def : Proc<"arm1136jf-s", [ArchV6, FeatureVFP2]>; |
| 82 | def : Proc<"arm1176jz-s", [ArchV6]>; |
| 83 | def : Proc<"arm1176jzf-s", [ArchV6, FeatureVFP2]>; |
| 84 | def : Proc<"mpcorenovfp", [ArchV6]>; |
| 85 | def : Proc<"mpcore", [ArchV6, FeatureVFP2]>; |
| 86 | |
| 87 | //===----------------------------------------------------------------------===// |
| Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 88 | // Register File Description |
| 89 | //===----------------------------------------------------------------------===// |
| 90 | |
| 91 | include "ARMRegisterInfo.td" |
| 92 | |
| 93 | //===----------------------------------------------------------------------===// |
| 94 | // Instruction Descriptions |
| 95 | //===----------------------------------------------------------------------===// |
| 96 | |
| 97 | include "ARMInstrInfo.td" |
| 98 | |
| 99 | def ARMInstrInfo : InstrInfo { |
| 100 | // Define how we want to layout our target-specific information field. |
| Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 101 | let TSFlagsFields = ["AddrModeBits", |
| 102 | "SizeFlag", |
| 103 | "IndexModeBits", |
| Evan Cheng | 0ff94f7 | 2007-08-07 01:37:15 +0000 | [diff] [blame] | 104 | "Opcode", |
| 105 | "Form"]; |
| Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 106 | let TSFlagsShifts = [0, |
| 107 | 4, |
| 108 | 7, |
| Evan Cheng | 0ff94f7 | 2007-08-07 01:37:15 +0000 | [diff] [blame] | 109 | 9, |
| 110 | 13]; |
| Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | //===----------------------------------------------------------------------===// |
| 114 | // Declare the target which we are implementing |
| 115 | //===----------------------------------------------------------------------===// |
| 116 | |
| 117 | def ARM : Target { |
| Rafael Espindola | 7bc59bc | 2006-05-14 22:18:28 +0000 | [diff] [blame] | 118 | // Pull in Instruction Info: |
| 119 | let InstructionSet = ARMInstrInfo; |
| 120 | } |