Misha Brukman | 2a8350a | 2005-02-05 02:24:26 +0000 | [diff] [blame] | 1 | //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===// |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 2 | // |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 7 | // |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Andrew Lenharth | 2d6f022 | 2005-01-24 19:44:07 +0000 | [diff] [blame] | 10 | // This file contains the Alpha implementation of the MRegisterInfo class. |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #define DEBUG_TYPE "reginfo" |
| 15 | #include "Alpha.h" |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 16 | #include "AlphaRegisterInfo.h" |
| 17 | #include "llvm/Constants.h" |
| 18 | #include "llvm/Type.h" |
Andrew Lenharth | c24b537 | 2005-04-13 17:17:28 +0000 | [diff] [blame] | 19 | #include "llvm/Function.h" |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/ValueTypes.h" |
| 21 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 22 | #include "llvm/CodeGen/MachineFunction.h" |
| 23 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 24 | #include "llvm/CodeGen/MachineLocation.h" |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 25 | #include "llvm/Target/TargetFrameInfo.h" |
| 26 | #include "llvm/Target/TargetMachine.h" |
| 27 | #include "llvm/Target/TargetOptions.h" |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 28 | #include "llvm/Target/TargetInstrInfo.h" |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 29 | #include "llvm/Support/CommandLine.h" |
| 30 | #include "llvm/Support/Debug.h" |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 31 | #include "llvm/ADT/BitVector.h" |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 32 | #include "llvm/ADT/STLExtras.h" |
| 33 | #include <cstdlib> |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 34 | using namespace llvm; |
| 35 | |
Andrew Lenharth | f69a98c | 2005-03-04 21:40:02 +0000 | [diff] [blame] | 36 | //These describe LDAx |
Andrew Lenharth | c051383 | 2005-03-29 19:24:04 +0000 | [diff] [blame] | 37 | static const int IMM_LOW = -32768; |
| 38 | static const int IMM_HIGH = 32767; |
Andrew Lenharth | 3ee6041 | 2005-03-05 15:30:33 +0000 | [diff] [blame] | 39 | static const int IMM_MULT = 65536; |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 40 | |
| 41 | static long getUpper16(long l) |
| 42 | { |
Andrew Lenharth | f69a98c | 2005-03-04 21:40:02 +0000 | [diff] [blame] | 43 | long y = l / IMM_MULT; |
| 44 | if (l % IMM_MULT > IMM_HIGH) |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 45 | ++y; |
| 46 | return y; |
| 47 | } |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 48 | |
Andrew Lenharth | f69a98c | 2005-03-04 21:40:02 +0000 | [diff] [blame] | 49 | static long getLower16(long l) |
| 50 | { |
| 51 | long h = getUpper16(l); |
| 52 | return l - h * IMM_MULT; |
| 53 | } |
| 54 | |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 55 | AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) |
| 56 | : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP), |
| 57 | TII(tii) |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 58 | { |
| 59 | } |
| 60 | |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 61 | void |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 62 | AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, |
| 63 | MachineBasicBlock::iterator MI, |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 64 | unsigned SrcReg, bool isKill, int FrameIdx, |
| 65 | const TargetRegisterClass *RC) const { |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 66 | //cerr << "Trying to store " << getPrettyName(SrcReg) << " to " |
| 67 | // << FrameIdx << "\n"; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 68 | //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 69 | if (RC == Alpha::F4RCRegisterClass) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 70 | BuildMI(MBB, MI, TII.get(Alpha::STS)) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 71 | .addReg(SrcReg, false, false, isKill) |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 72 | .addFrameIndex(FrameIdx).addReg(Alpha::F31); |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 73 | else if (RC == Alpha::F8RCRegisterClass) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 74 | BuildMI(MBB, MI, TII.get(Alpha::STT)) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 75 | .addReg(SrcReg, false, false, isKill) |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 76 | .addFrameIndex(FrameIdx).addReg(Alpha::F31); |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 77 | else if (RC == Alpha::GPRCRegisterClass) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 78 | BuildMI(MBB, MI, TII.get(Alpha::STQ)) |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 79 | .addReg(SrcReg, false, false, isKill) |
Evan Cheng | 0fa1b6d | 2007-02-23 01:10:04 +0000 | [diff] [blame] | 80 | .addFrameIndex(FrameIdx).addReg(Alpha::F31); |
Andrew Lenharth | 2a8fc23 | 2005-02-01 20:35:57 +0000 | [diff] [blame] | 81 | else |
| 82 | abort(); |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 83 | } |
| 84 | |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 85 | void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 86 | bool isKill, |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 87 | SmallVectorImpl<MachineOperand> &Addr, |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 88 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 89 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 90 | unsigned Opc = 0; |
| 91 | if (RC == Alpha::F4RCRegisterClass) |
| 92 | Opc = Alpha::STS; |
| 93 | else if (RC == Alpha::F8RCRegisterClass) |
| 94 | Opc = Alpha::STT; |
| 95 | else if (RC == Alpha::GPRCRegisterClass) |
| 96 | Opc = Alpha::STQ; |
| 97 | else |
| 98 | abort(); |
| 99 | MachineInstrBuilder MIB = |
Evan Cheng | d64b5c8 | 2007-12-05 03:14:33 +0000 | [diff] [blame] | 100 | BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill); |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 101 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) { |
| 102 | MachineOperand &MO = Addr[i]; |
| 103 | if (MO.isRegister()) |
| 104 | MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); |
| 105 | else |
| 106 | MIB.addImm(MO.getImm()); |
| 107 | } |
| 108 | NewMIs.push_back(MIB); |
| 109 | } |
| 110 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 111 | void |
| 112 | AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, |
| 113 | MachineBasicBlock::iterator MI, |
Chris Lattner | 97d5e64 | 2005-09-30 01:29:42 +0000 | [diff] [blame] | 114 | unsigned DestReg, int FrameIdx, |
| 115 | const TargetRegisterClass *RC) const { |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 116 | //cerr << "Trying to load " << getPrettyName(DestReg) << " to " |
| 117 | // << FrameIdx << "\n"; |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 118 | if (RC == Alpha::F4RCRegisterClass) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 119 | BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg) |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 120 | .addFrameIndex(FrameIdx).addReg(Alpha::F31); |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 121 | else if (RC == Alpha::F8RCRegisterClass) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 122 | BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg) |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 123 | .addFrameIndex(FrameIdx).addReg(Alpha::F31); |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 124 | else if (RC == Alpha::GPRCRegisterClass) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 125 | BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg) |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 126 | .addFrameIndex(FrameIdx).addReg(Alpha::F31); |
Andrew Lenharth | 2a8fc23 | 2005-02-01 20:35:57 +0000 | [diff] [blame] | 127 | else |
| 128 | abort(); |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 129 | } |
| 130 | |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 131 | void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, |
Evan Cheng | f0a0cdd | 2007-10-18 22:40:57 +0000 | [diff] [blame] | 132 | SmallVectorImpl<MachineOperand> &Addr, |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 133 | const TargetRegisterClass *RC, |
Evan Cheng | 58184e6 | 2007-10-18 21:29:24 +0000 | [diff] [blame] | 134 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
Evan Cheng | 66f0f64 | 2007-10-05 01:32:41 +0000 | [diff] [blame] | 135 | unsigned Opc = 0; |
| 136 | if (RC == Alpha::F4RCRegisterClass) |
| 137 | Opc = Alpha::LDS; |
| 138 | else if (RC == Alpha::F8RCRegisterClass) |
| 139 | Opc = Alpha::LDT; |
| 140 | else if (RC == Alpha::GPRCRegisterClass) |
| 141 | Opc = Alpha::LDQ; |
| 142 | else |
| 143 | abort(); |
| 144 | MachineInstrBuilder MIB = |
| 145 | BuildMI(TII.get(Opc), DestReg); |
| 146 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) { |
| 147 | MachineOperand &MO = Addr[i]; |
| 148 | if (MO.isRegister()) |
| 149 | MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); |
| 150 | else |
| 151 | MIB.addImm(MO.getImm()); |
| 152 | } |
| 153 | NewMIs.push_back(MIB); |
| 154 | } |
| 155 | |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 156 | MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 157 | SmallVectorImpl<unsigned> &Ops, |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 158 | int FrameIndex) const { |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 159 | if (Ops.size() != 1) return NULL; |
| 160 | |
Andrew Lenharth | 7a832da | 2006-01-01 22:13:54 +0000 | [diff] [blame] | 161 | // Make sure this is a reg-reg copy. |
| 162 | unsigned Opc = MI->getOpcode(); |
| 163 | |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 164 | MachineInstr *NewMI = NULL; |
Andrew Lenharth | 7a832da | 2006-01-01 22:13:54 +0000 | [diff] [blame] | 165 | switch(Opc) { |
| 166 | default: |
| 167 | break; |
Andrew Lenharth | 6bbf6b0 | 2006-10-31 23:46:56 +0000 | [diff] [blame] | 168 | case Alpha::BISr: |
Andrew Lenharth | 7a832da | 2006-01-01 22:13:54 +0000 | [diff] [blame] | 169 | case Alpha::CPYSS: |
| 170 | case Alpha::CPYST: |
| 171 | if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 172 | if (Ops[0] == 0) { // move -> store |
Anton Korobeynikov | bed2946 | 2007-04-16 18:10:23 +0000 | [diff] [blame] | 173 | unsigned InReg = MI->getOperand(1).getReg(); |
| 174 | Opc = (Opc == Alpha::BISr) ? Alpha::STQ : |
| 175 | ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); |
| 176 | NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex) |
| 177 | .addReg(Alpha::F31); |
Andrew Lenharth | 7a832da | 2006-01-01 22:13:54 +0000 | [diff] [blame] | 178 | } else { // load -> move |
Anton Korobeynikov | bed2946 | 2007-04-16 18:10:23 +0000 | [diff] [blame] | 179 | unsigned OutReg = MI->getOperand(0).getReg(); |
| 180 | Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : |
| 181 | ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); |
| 182 | NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex) |
| 183 | .addReg(Alpha::F31); |
Andrew Lenharth | 7a832da | 2006-01-01 22:13:54 +0000 | [diff] [blame] | 184 | } |
| 185 | } |
| 186 | break; |
| 187 | } |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 188 | if (NewMI) |
| 189 | NewMI->copyKillDeadInfo(MI); |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 190 | return 0; |
| 191 | } |
| 192 | |
| 193 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 194 | void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 195 | MachineBasicBlock::iterator MI, |
| 196 | unsigned DestReg, unsigned SrcReg, |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 197 | const TargetRegisterClass *DestRC, |
| 198 | const TargetRegisterClass *SrcRC) const { |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 199 | //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 200 | if (DestRC != SrcRC) { |
| 201 | cerr << "Not yet supported!"; |
| 202 | abort(); |
| 203 | } |
| 204 | |
| 205 | if (DestRC == Alpha::GPRCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 206 | BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg); |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 207 | } else if (DestRC == Alpha::F4RCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 208 | BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg); |
Evan Cheng | 9efce63 | 2007-09-26 06:25:56 +0000 | [diff] [blame] | 209 | } else if (DestRC == Alpha::F8RCRegisterClass) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 210 | BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 211 | } else { |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 212 | cerr << "Attempt to copy register that is not GPR or FPR"; |
| 213 | abort(); |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 214 | } |
| 215 | } |
| 216 | |
Evan Cheng | bf2c8b3 | 2007-03-20 08:09:38 +0000 | [diff] [blame] | 217 | void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB, |
| 218 | MachineBasicBlock::iterator I, |
| 219 | unsigned DestReg, |
| 220 | const MachineInstr *Orig) const { |
| 221 | MachineInstr *MI = Orig->clone(); |
| 222 | MI->getOperand(0).setReg(DestReg); |
| 223 | MBB.insert(I, MI); |
| 224 | } |
| 225 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 226 | const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) |
| 227 | const { |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 228 | static const unsigned CalleeSavedRegs[] = { |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 229 | Alpha::R9, Alpha::R10, |
| 230 | Alpha::R11, Alpha::R12, |
| 231 | Alpha::R13, Alpha::R14, |
| 232 | Alpha::F2, Alpha::F3, |
| 233 | Alpha::F4, Alpha::F5, |
| 234 | Alpha::F6, Alpha::F7, |
| 235 | Alpha::F8, Alpha::F9, 0 |
| 236 | }; |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 237 | return CalleeSavedRegs; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 238 | } |
| 239 | |
| 240 | const TargetRegisterClass* const* |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 241 | AlphaRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 242 | static const TargetRegisterClass * const CalleeSavedRegClasses[] = { |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 243 | &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, |
| 244 | &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, |
| 245 | &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, |
| 246 | &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, |
| 247 | &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, |
| 248 | &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, |
| 249 | &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0 |
| 250 | }; |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 251 | return CalleeSavedRegClasses; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 252 | } |
| 253 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 254 | BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
| 255 | BitVector Reserved(getNumRegs()); |
| 256 | Reserved.set(Alpha::R15); |
| 257 | Reserved.set(Alpha::R30); |
| 258 | Reserved.set(Alpha::R31); |
| 259 | return Reserved; |
| 260 | } |
| 261 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 262 | //===----------------------------------------------------------------------===// |
| 263 | // Stack Frame Processing methods |
| 264 | //===----------------------------------------------------------------------===// |
| 265 | |
| 266 | // hasFP - Return true if the specified function should have a dedicated frame |
| 267 | // pointer register. This is true if the function has variable sized allocas or |
| 268 | // if frame pointer elimination is disabled. |
| 269 | // |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 270 | bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const { |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 271 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 272 | return MFI->hasVarSizedObjects(); |
| 273 | } |
| 274 | |
| 275 | void AlphaRegisterInfo:: |
| 276 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 277 | MachineBasicBlock::iterator I) const { |
| 278 | if (hasFP(MF)) { |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 279 | // If we have a frame pointer, turn the adjcallstackup instruction into a |
| 280 | // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP, |
| 281 | // <amt>' |
| 282 | MachineInstr *Old = I; |
Andrew Lenharth | 65b889f | 2006-05-17 19:24:49 +0000 | [diff] [blame] | 283 | uint64_t Amount = Old->getOperand(0).getImmedValue(); |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 284 | if (Amount != 0) { |
| 285 | // We need to keep the stack aligned properly. To do this, we round the |
| 286 | // amount of space needed for the outgoing arguments up to the next |
| 287 | // alignment boundary. |
| 288 | unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 289 | Amount = (Amount+Align-1)/Align*Align; |
| 290 | |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 291 | MachineInstr *New; |
| 292 | if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 293 | New=BuildMI(TII.get(Alpha::LDA), Alpha::R30) |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 294 | .addImm(-Amount).addReg(Alpha::R30); |
| 295 | } else { |
Misha Brukman | 7847fca | 2005-04-22 17:54:37 +0000 | [diff] [blame] | 296 | assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 297 | New=BuildMI(TII.get(Alpha::LDA), Alpha::R30) |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 298 | .addImm(Amount).addReg(Alpha::R30); |
| 299 | } |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 300 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 301 | // Replace the pseudo instruction with a new instruction... |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 302 | MBB.insert(I, New); |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 303 | } |
| 304 | } |
| 305 | |
| 306 | MBB.erase(I); |
| 307 | } |
| 308 | |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 309 | //Alpha has a slightly funny stack: |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 310 | //Args |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 311 | //<- incoming SP |
| 312 | //fixed locals (and spills, callee saved, etc) |
| 313 | //<- FP |
| 314 | //variable locals |
| 315 | //<- SP |
| 316 | |
Evan Cheng | 5e6df46 | 2007-02-28 00:21:17 +0000 | [diff] [blame] | 317 | void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
Evan Cheng | 97de913 | 2007-05-01 09:13:03 +0000 | [diff] [blame] | 318 | int SPAdj, RegScavenger *RS) const { |
| 319 | assert(SPAdj == 0 && "Unexpected"); |
| 320 | |
Andrew Lenharth | 684f229 | 2005-01-30 00:35:27 +0000 | [diff] [blame] | 321 | unsigned i = 0; |
| 322 | MachineInstr &MI = *II; |
| 323 | MachineBasicBlock &MBB = *MI.getParent(); |
| 324 | MachineFunction &MF = *MBB.getParent(); |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 325 | bool FP = hasFP(MF); |
| 326 | |
Andrew Lenharth | 684f229 | 2005-01-30 00:35:27 +0000 | [diff] [blame] | 327 | while (!MI.getOperand(i).isFrameIndex()) { |
| 328 | ++i; |
| 329 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 330 | } |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 331 | |
Andrew Lenharth | 684f229 | 2005-01-30 00:35:27 +0000 | [diff] [blame] | 332 | int FrameIndex = MI.getOperand(i).getFrameIndex(); |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 333 | |
Andrew Lenharth | 684f229 | 2005-01-30 00:35:27 +0000 | [diff] [blame] | 334 | // Add the base register of R30 (SP) or R15 (FP). |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 335 | MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 336 | |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 337 | // Now add the frame object offset to the offset from the virtual frame index. |
Andrew Lenharth | 684f229 | 2005-01-30 00:35:27 +0000 | [diff] [blame] | 338 | int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); |
| 339 | |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 340 | DOUT << "FI: " << FrameIndex << " Offset: " << Offset << "\n"; |
Andrew Lenharth | 684f229 | 2005-01-30 00:35:27 +0000 | [diff] [blame] | 341 | |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 342 | Offset += MF.getFrameInfo()->getStackSize(); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 343 | |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 344 | DOUT << "Corrected Offset " << Offset |
| 345 | << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n"; |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 346 | |
Andrew Lenharth | f69a98c | 2005-03-04 21:40:02 +0000 | [diff] [blame] | 347 | if (Offset > IMM_HIGH || Offset < IMM_LOW) { |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 348 | DOUT << "Unconditionally using R28 for evil purposes Offset: " |
| 349 | << Offset << "\n"; |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 350 | //so in this case, we need to use a temporary register, and move the |
| 351 | //original inst off the SP/FP |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 352 | //fix up the old: |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 353 | MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 354 | MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 355 | //insert the new |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 356 | MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28) |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 357 | .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); |
Andrew Lenharth | 84e2dc2 | 2005-03-13 00:43:20 +0000 | [diff] [blame] | 358 | MBB.insert(II, nMI); |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 359 | } else { |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 360 | MI.getOperand(i).ChangeToImmediate(Offset); |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 361 | } |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 362 | } |
| 363 | |
| 364 | |
| 365 | void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const { |
| 366 | MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB |
| 367 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
| 368 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 369 | bool FP = hasFP(MF); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 370 | |
Andrew Lenharth | 0934ae0 | 2005-07-22 20:52:16 +0000 | [diff] [blame] | 371 | static int curgpdist = 0; |
| 372 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 373 | //handle GOP offset |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 374 | BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29) |
Andrew Lenharth | 0934ae0 | 2005-07-22 20:52:16 +0000 | [diff] [blame] | 375 | .addGlobalAddress(const_cast<Function*>(MF.getFunction())) |
| 376 | .addReg(Alpha::R27).addImm(++curgpdist); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 377 | BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29) |
Andrew Lenharth | 0934ae0 | 2005-07-22 20:52:16 +0000 | [diff] [blame] | 378 | .addGlobalAddress(const_cast<Function*>(MF.getFunction())) |
| 379 | .addReg(Alpha::R29).addImm(curgpdist); |
| 380 | |
Andrew Lenharth | c24b537 | 2005-04-13 17:17:28 +0000 | [diff] [blame] | 381 | //evil const_cast until MO stuff setup to handle const |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 382 | BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT)) |
Chris Lattner | ea50fab | 2006-05-04 01:15:02 +0000 | [diff] [blame] | 383 | .addGlobalAddress(const_cast<Function*>(MF.getFunction())); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 384 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 385 | // Get the number of bytes to allocate from the FrameInfo |
Andrew Lenharth | f69a98c | 2005-03-04 21:40:02 +0000 | [diff] [blame] | 386 | long NumBytes = MFI->getStackSize(); |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 387 | |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 388 | if (FP) |
| 389 | NumBytes += 8; //reserve space for the old FP |
| 390 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 391 | // Do we need to allocate space on the stack? |
| 392 | if (NumBytes == 0) return; |
| 393 | |
Andrew Lenharth | 2391897 | 2006-01-25 01:51:08 +0000 | [diff] [blame] | 394 | unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 395 | NumBytes = (NumBytes+Align-1)/Align*Align; |
| 396 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 397 | // Update frame info to pretend that this is part of the stack... |
| 398 | MFI->setStackSize(NumBytes); |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 399 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 400 | // adjust stack pointer: r30 -= numbytes |
Andrew Lenharth | f69a98c | 2005-03-04 21:40:02 +0000 | [diff] [blame] | 401 | NumBytes = -NumBytes; |
| 402 | if (NumBytes >= IMM_LOW) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 403 | BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) |
Andrew Lenharth | a48f3ce | 2005-07-07 19:52:58 +0000 | [diff] [blame] | 404 | .addReg(Alpha::R30); |
Andrew Lenharth | f69a98c | 2005-03-04 21:40:02 +0000 | [diff] [blame] | 405 | } else if (getUpper16(NumBytes) >= IMM_LOW) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 406 | BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes)) |
Andrew Lenharth | a48f3ce | 2005-07-07 19:52:58 +0000 | [diff] [blame] | 407 | .addReg(Alpha::R30); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 408 | BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes)) |
Andrew Lenharth | a48f3ce | 2005-07-07 19:52:58 +0000 | [diff] [blame] | 409 | .addReg(Alpha::R30); |
Andrew Lenharth | 3e98fde | 2005-01-26 21:54:09 +0000 | [diff] [blame] | 410 | } else { |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 411 | cerr << "Too big a stack frame at " << NumBytes << "\n"; |
Andrew Lenharth | 3e98fde | 2005-01-26 21:54:09 +0000 | [diff] [blame] | 412 | abort(); |
| 413 | } |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 414 | |
| 415 | //now if we need to, save the old FP and set the new |
| 416 | if (FP) |
| 417 | { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 418 | BuildMI(MBB, MBBI, TII.get(Alpha::STQ)) |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 419 | .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 420 | //this must be the last instr in the prolog |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 421 | BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15) |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 422 | .addReg(Alpha::R30).addReg(Alpha::R30); |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 423 | } |
| 424 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 425 | } |
| 426 | |
| 427 | void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, |
| 428 | MachineBasicBlock &MBB) const { |
| 429 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 430 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 431 | assert(MBBI->getOpcode() == Alpha::RETDAG || |
| 432 | MBBI->getOpcode() == Alpha::RETDAGp |
Misha Brukman | 7847fca | 2005-04-22 17:54:37 +0000 | [diff] [blame] | 433 | && "Can only insert epilog into returning blocks"); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 434 | |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 435 | bool FP = hasFP(MF); |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 436 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 437 | // Get the number of bytes allocated from the FrameInfo... |
Andrew Lenharth | 3ee6041 | 2005-03-05 15:30:33 +0000 | [diff] [blame] | 438 | long NumBytes = MFI->getStackSize(); |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 439 | |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 440 | //now if we need to, restore the old FP |
| 441 | if (FP) |
| 442 | { |
Andrew Lenharth | 0169475 | 2005-02-24 18:36:32 +0000 | [diff] [blame] | 443 | //copy the FP into the SP (discards allocas) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 444 | BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) |
Andrew Lenharth | a48f3ce | 2005-07-07 19:52:58 +0000 | [diff] [blame] | 445 | .addReg(Alpha::R15); |
Andrew Lenharth | 0169475 | 2005-02-24 18:36:32 +0000 | [diff] [blame] | 446 | //restore the FP |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 447 | BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15); |
Andrew Lenharth | 032f235 | 2005-02-22 21:59:48 +0000 | [diff] [blame] | 448 | } |
| 449 | |
Misha Brukman | 4633f1c | 2005-04-21 23:13:11 +0000 | [diff] [blame] | 450 | if (NumBytes != 0) |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 451 | { |
Andrew Lenharth | f69a98c | 2005-03-04 21:40:02 +0000 | [diff] [blame] | 452 | if (NumBytes <= IMM_HIGH) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 453 | BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) |
Andrew Lenharth | a48f3ce | 2005-07-07 19:52:58 +0000 | [diff] [blame] | 454 | .addReg(Alpha::R30); |
Andrew Lenharth | f69a98c | 2005-03-04 21:40:02 +0000 | [diff] [blame] | 455 | } else if (getUpper16(NumBytes) <= IMM_HIGH) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 456 | BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30) |
Andrew Lenharth | a48f3ce | 2005-07-07 19:52:58 +0000 | [diff] [blame] | 457 | .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 458 | BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30) |
Andrew Lenharth | a48f3ce | 2005-07-07 19:52:58 +0000 | [diff] [blame] | 459 | .addImm(getLower16(NumBytes)).addReg(Alpha::R30); |
Andrew Lenharth | 04c868e | 2005-01-27 08:31:19 +0000 | [diff] [blame] | 460 | } else { |
Bill Wendling | f5da133 | 2006-12-07 22:21:48 +0000 | [diff] [blame] | 461 | cerr << "Too big a stack frame at " << NumBytes << "\n"; |
Andrew Lenharth | 04c868e | 2005-01-27 08:31:19 +0000 | [diff] [blame] | 462 | abort(); |
| 463 | } |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 464 | } |
| 465 | } |
| 466 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 467 | unsigned AlphaRegisterInfo::getRARegister() const { |
| 468 | assert(0 && "What is the return address register"); |
| 469 | return 0; |
| 470 | } |
| 471 | |
Jim Laskey | a997918 | 2006-03-28 13:48:33 +0000 | [diff] [blame] | 472 | unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const { |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 473 | return hasFP(MF) ? Alpha::R15 : Alpha::R30; |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 474 | } |
| 475 | |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 476 | unsigned AlphaRegisterInfo::getEHExceptionRegister() const { |
| 477 | assert(0 && "What is the exception register"); |
| 478 | return 0; |
| 479 | } |
| 480 | |
| 481 | unsigned AlphaRegisterInfo::getEHHandlerRegister() const { |
| 482 | assert(0 && "What is the exception handler register"); |
| 483 | return 0; |
| 484 | } |
| 485 | |
Dale Johannesen | b97aec6 | 2007-11-13 19:13:01 +0000 | [diff] [blame] | 486 | int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 487 | assert(0 && "What is the dwarf register number"); |
| 488 | return -1; |
| 489 | } |
| 490 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 491 | #include "AlphaGenRegisterInfo.inc" |
| 492 | |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 493 | std::string AlphaRegisterInfo::getPrettyName(unsigned reg) |
| 494 | { |
| 495 | std::string s(RegisterDescriptors[reg].Name); |
| 496 | return s; |
| 497 | } |