Misha Brukman | bc9ccf6 | 2005-02-04 20:25:52 +0000 | [diff] [blame] | 1 | //===- AlphaRegisterInfo.td - The Alpha Register File ------*- tablegen -*-===// |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Misha Brukman | f5024ff | 2005-02-10 01:52:22 +0000 | [diff] [blame] | 10 | // This file describes the Alpha register set. |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | class AlphaReg<string n> : Register<n> { |
| 15 | field bits<5> Num; |
| 16 | let Namespace = "Alpha"; |
| 17 | } |
| 18 | |
| 19 | // We identify all our registers with a 5-bit ID, for consistency's sake. |
| 20 | |
| 21 | // GPR - One of the 32 32-bit general-purpose registers |
| 22 | class GPR<bits<5> num, string n> : AlphaReg<n> { |
| 23 | let Num = num; |
| 24 | } |
| 25 | |
| 26 | // FPR - One of the 32 64-bit floating-point registers |
| 27 | class FPR<bits<5> num, string n> : AlphaReg<n> { |
| 28 | let Num = num; |
| 29 | } |
| 30 | |
| 31 | //#define FP $15 |
| 32 | //#define RA $26 |
| 33 | //#define PV $27 |
| 34 | //#define GP $29 |
| 35 | //#define SP $30 |
| 36 | |
| 37 | // General-purpose registers |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 38 | def R0 : GPR< 0, "$0">, DwarfRegNum<[0]>; |
| 39 | def R1 : GPR< 1, "$1">, DwarfRegNum<[1]>; |
| 40 | def R2 : GPR< 2, "$2">, DwarfRegNum<[2]>; |
| 41 | def R3 : GPR< 3, "$3">, DwarfRegNum<[3]>; |
| 42 | def R4 : GPR< 4, "$4">, DwarfRegNum<[4]>; |
| 43 | def R5 : GPR< 5, "$5">, DwarfRegNum<[5]>; |
| 44 | def R6 : GPR< 6, "$6">, DwarfRegNum<[6]>; |
| 45 | def R7 : GPR< 7, "$7">, DwarfRegNum<[7]>; |
| 46 | def R8 : GPR< 8, "$8">, DwarfRegNum<[8]>; |
| 47 | def R9 : GPR< 9, "$9">, DwarfRegNum<[9]>; |
| 48 | def R10 : GPR<10, "$10">, DwarfRegNum<[10]>; |
| 49 | def R11 : GPR<11, "$11">, DwarfRegNum<[11]>; |
| 50 | def R12 : GPR<12, "$12">, DwarfRegNum<[12]>; |
| 51 | def R13 : GPR<13, "$13">, DwarfRegNum<[13]>; |
| 52 | def R14 : GPR<14, "$14">, DwarfRegNum<[14]>; |
| 53 | def R15 : GPR<15, "$15">, DwarfRegNum<[15]>; |
| 54 | def R16 : GPR<16, "$16">, DwarfRegNum<[16]>; |
| 55 | def R17 : GPR<17, "$17">, DwarfRegNum<[17]>; |
| 56 | def R18 : GPR<18, "$18">, DwarfRegNum<[18]>; |
| 57 | def R19 : GPR<19, "$19">, DwarfRegNum<[19]>; |
| 58 | def R20 : GPR<20, "$20">, DwarfRegNum<[20]>; |
| 59 | def R21 : GPR<21, "$21">, DwarfRegNum<[21]>; |
| 60 | def R22 : GPR<22, "$22">, DwarfRegNum<[22]>; |
| 61 | def R23 : GPR<23, "$23">, DwarfRegNum<[23]>; |
| 62 | def R24 : GPR<24, "$24">, DwarfRegNum<[24]>; |
| 63 | def R25 : GPR<25, "$25">, DwarfRegNum<[25]>; |
| 64 | def R26 : GPR<26, "$26">, DwarfRegNum<[26]>; |
| 65 | def R27 : GPR<27, "$27">, DwarfRegNum<[27]>; |
| 66 | def R28 : GPR<28, "$28">, DwarfRegNum<[28]>; |
| 67 | def R29 : GPR<29, "$29">, DwarfRegNum<[29]>; |
| 68 | def R30 : GPR<30, "$30">, DwarfRegNum<[30]>; |
| 69 | def R31 : GPR<31, "$31">, DwarfRegNum<[31]>; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 70 | |
| 71 | // Floating-point registers |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 72 | def F0 : FPR< 0, "$f0">, DwarfRegNum<[33]>; |
| 73 | def F1 : FPR< 1, "$f1">, DwarfRegNum<[34]>; |
| 74 | def F2 : FPR< 2, "$f2">, DwarfRegNum<[35]>; |
| 75 | def F3 : FPR< 3, "$f3">, DwarfRegNum<[36]>; |
| 76 | def F4 : FPR< 4, "$f4">, DwarfRegNum<[37]>; |
| 77 | def F5 : FPR< 5, "$f5">, DwarfRegNum<[38]>; |
| 78 | def F6 : FPR< 6, "$f6">, DwarfRegNum<[39]>; |
| 79 | def F7 : FPR< 7, "$f7">, DwarfRegNum<[40]>; |
| 80 | def F8 : FPR< 8, "$f8">, DwarfRegNum<[41]>; |
| 81 | def F9 : FPR< 9, "$f9">, DwarfRegNum<[42]>; |
| 82 | def F10 : FPR<10, "$f10">, DwarfRegNum<[43]>; |
| 83 | def F11 : FPR<11, "$f11">, DwarfRegNum<[44]>; |
| 84 | def F12 : FPR<12, "$f12">, DwarfRegNum<[45]>; |
| 85 | def F13 : FPR<13, "$f13">, DwarfRegNum<[46]>; |
| 86 | def F14 : FPR<14, "$f14">, DwarfRegNum<[47]>; |
| 87 | def F15 : FPR<15, "$f15">, DwarfRegNum<[48]>; |
| 88 | def F16 : FPR<16, "$f16">, DwarfRegNum<[49]>; |
| 89 | def F17 : FPR<17, "$f17">, DwarfRegNum<[50]>; |
| 90 | def F18 : FPR<18, "$f18">, DwarfRegNum<[51]>; |
| 91 | def F19 : FPR<19, "$f19">, DwarfRegNum<[52]>; |
| 92 | def F20 : FPR<20, "$f20">, DwarfRegNum<[53]>; |
| 93 | def F21 : FPR<21, "$f21">, DwarfRegNum<[54]>; |
| 94 | def F22 : FPR<22, "$f22">, DwarfRegNum<[55]>; |
| 95 | def F23 : FPR<23, "$f23">, DwarfRegNum<[56]>; |
| 96 | def F24 : FPR<24, "$f24">, DwarfRegNum<[57]>; |
| 97 | def F25 : FPR<25, "$f25">, DwarfRegNum<[58]>; |
| 98 | def F26 : FPR<26, "$f26">, DwarfRegNum<[59]>; |
| 99 | def F27 : FPR<27, "$f27">, DwarfRegNum<[60]>; |
| 100 | def F28 : FPR<28, "$f28">, DwarfRegNum<[61]>; |
| 101 | def F29 : FPR<29, "$f29">, DwarfRegNum<[62]>; |
| 102 | def F30 : FPR<30, "$f30">, DwarfRegNum<[63]>; |
| 103 | def F31 : FPR<31, "$f31">, DwarfRegNum<[64]>; |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 104 | |
| 105 | // //#define FP $15 |
| 106 | // //#define RA $26 |
| 107 | // //#define PV $27 |
| 108 | // //#define GP $29 |
| 109 | // //#define SP $30 |
| 110 | // $28 is undefined after any and all calls |
| 111 | |
| 112 | /// Register classes |
Nate Begeman | 6510b22 | 2005-12-01 04:51:06 +0000 | [diff] [blame] | 113 | def GPRC : RegisterClass<"Alpha", [i64], 64, |
Misha Brukman | f5024ff | 2005-02-10 01:52:22 +0000 | [diff] [blame] | 114 | // Volatile |
| 115 | [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22, |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 116 | R23, R24, R25, R28, |
Andrew Lenharth | c7989ce | 2005-06-29 00:31:08 +0000 | [diff] [blame] | 117 | //Special meaning, but volatile |
| 118 | R27, //procedure address |
| 119 | R26, //return address |
| 120 | R29, //global offset table address |
Misha Brukman | f5024ff | 2005-02-10 01:52:22 +0000 | [diff] [blame] | 121 | // Non-volatile |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 122 | R9, R10, R11, R12, R13, R14, |
Andrew Lenharth | 7f0db91 | 2005-11-30 07:19:56 +0000 | [diff] [blame] | 123 | // Don't allocate 15, 30, 31 |
| 124 | R15, R30, R31 ]> //zero |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 125 | { |
| 126 | let MethodProtos = [{ |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 127 | iterator allocation_order_end(const MachineFunction &MF) const; |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 128 | }]; |
| 129 | let MethodBodies = [{ |
| 130 | GPRCClass::iterator |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 131 | GPRCClass::allocation_order_end(const MachineFunction &MF) const { |
Andrew Lenharth | 7f0db91 | 2005-11-30 07:19:56 +0000 | [diff] [blame] | 132 | return end()-3; |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 133 | } |
| 134 | }]; |
| 135 | } |
Andrew Lenharth | 304d0f3 | 2005-01-22 23:41:55 +0000 | [diff] [blame] | 136 | |
Nate Begeman | 6510b22 | 2005-12-01 04:51:06 +0000 | [diff] [blame] | 137 | def F4RC : RegisterClass<"Alpha", [f32], 64, [F0, F1, |
Andrew Lenharth | 2c9e38c | 2005-02-06 21:07:31 +0000 | [diff] [blame] | 138 | F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, |
| 139 | F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, |
Misha Brukman | f5024ff | 2005-02-10 01:52:22 +0000 | [diff] [blame] | 140 | // Saved: |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 141 | F2, F3, F4, F5, F6, F7, F8, F9, |
| 142 | F31 ]> //zero |
| 143 | { |
| 144 | let MethodProtos = [{ |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 145 | iterator allocation_order_end(const MachineFunction &MF) const; |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 146 | }]; |
| 147 | let MethodBodies = [{ |
| 148 | F4RCClass::iterator |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 149 | F4RCClass::allocation_order_end(const MachineFunction &MF) const { |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 150 | return end()-1; |
| 151 | } |
| 152 | }]; |
| 153 | } |
| 154 | |
Nate Begeman | 6510b22 | 2005-12-01 04:51:06 +0000 | [diff] [blame] | 155 | def F8RC : RegisterClass<"Alpha", [f64], 64, [F0, F1, |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 156 | F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, |
| 157 | F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, |
| 158 | // Saved: |
| 159 | F2, F3, F4, F5, F6, F7, F8, F9, |
| 160 | F31 ]> //zero |
| 161 | { |
| 162 | let MethodProtos = [{ |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 163 | iterator allocation_order_end(const MachineFunction &MF) const; |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 164 | }]; |
| 165 | let MethodBodies = [{ |
| 166 | F8RCClass::iterator |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 167 | F8RCClass::allocation_order_end(const MachineFunction &MF) const { |
Andrew Lenharth | 5cefc5e | 2005-11-09 19:17:08 +0000 | [diff] [blame] | 168 | return end()-1; |
| 169 | } |
| 170 | }]; |
| 171 | } |