Scott Michel | 67d5755 | 2007-12-05 01:31:18 +0000 | [diff] [blame] | 1 | //===-- CellSDKIntrinsics.td - Cell SDK Intrinsics ---------*- tablegen -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
Scott Michel | 67d5755 | 2007-12-05 01:31:18 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | ///--==-- Arithmetic ops intrinsics --==-- |
| 11 | def CellSDKah: |
| 12 | RR_Int_v8i16<0b00010011000, "ah", IntegerOp, int_spu_si_ah>; |
| 13 | def CellSDKahi: |
| 14 | RI10_Int_v8i16<0b00010011000, "ahi", IntegerOp, int_spu_si_ahi>; |
| 15 | def CellSDKa: |
| 16 | RR_Int_v4i32<0b00000011000, "a", IntegerOp, int_spu_si_a>; |
| 17 | def CellSDKai: |
| 18 | RI10_Int_v4i32<0b00111000, "ai", IntegerOp, int_spu_si_ai>; |
| 19 | def CellSDKsfh: |
| 20 | RR_Int_v8i16<0b00010010000, "sfh", IntegerOp, int_spu_si_sfh>; |
| 21 | def CellSDKsfhi: |
| 22 | RI10_Int_v8i16<0b10110000, "sfhi", IntegerOp, int_spu_si_sfhi>; |
| 23 | def CellSDKsf: |
| 24 | RR_Int_v4i32<0b00000010000, "sf", IntegerOp, int_spu_si_sf>; |
| 25 | def CellSDKsfi: |
| 26 | RI10_Int_v4i32<0b00110000, "sfi", IntegerOp, int_spu_si_sfi>; |
| 27 | def CellSDKaddx: |
| 28 | RR_Int_v4i32<0b00000010110, "addx", IntegerOp, int_spu_si_addx>; |
| 29 | def CellSDKcg: |
| 30 | RR_Int_v4i32<0b0100001100, "cg", IntegerOp, int_spu_si_cg>; |
| 31 | def CellSDKcgx: |
| 32 | RR_Int_v4i32<0b01000010110, "cgx", IntegerOp, int_spu_si_cgx>; |
| 33 | def CellSDKsfx: |
| 34 | RR_Int_v4i32<0b10000010110, "sfx", IntegerOp, int_spu_si_sfx>; |
| 35 | def CellSDKbg: |
| 36 | RR_Int_v4i32<0b01000010000, "bg", IntegerOp, int_spu_si_bg>; |
| 37 | def CellSDKbgx: |
| 38 | RR_Int_v4i32<0b11000010110, "bgx", IntegerOp, int_spu_si_bgx>; |
| 39 | |
| 40 | def CellSDKmpy: |
| 41 | RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 42 | "mpy $rT, $rA, $rB", IntegerMulDiv, |
| 43 | [(set (v4i32 VECREG:$rT), (int_spu_si_mpy (v8i16 VECREG:$rA), |
| 44 | (v8i16 VECREG:$rB)))]>; |
| 45 | |
| 46 | def CellSDKmpyu: |
| 47 | RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 48 | "mpyu $rT, $rA, $rB", IntegerMulDiv, |
| 49 | [(set (v4i32 VECREG:$rT), (int_spu_si_mpyu (v8i16 VECREG:$rA), |
| 50 | (v8i16 VECREG:$rB)))] >; |
| 51 | |
| 52 | def CellSDKmpyi: |
| 53 | RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 54 | "mpyi $rT, $rA, $val", IntegerMulDiv, |
| 55 | [(set (v4i32 VECREG:$rT), (int_spu_si_mpyi (v8i16 VECREG:$rA), |
| 56 | i16ImmSExt10:$val))]>; |
| 57 | |
| 58 | def CellSDKmpyui: |
| 59 | RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 60 | "mpyui $rT, $rA, $val", IntegerMulDiv, |
| 61 | [(set (v4i32 VECREG:$rT), (int_spu_si_mpyui (v8i16 VECREG:$rA), |
| 62 | i16ImmSExt10:$val))]>; |
| 63 | |
| 64 | def CellSDKmpya: |
| 65 | RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), |
| 66 | "mpya $rT, $rA, $rB, $rC", IntegerMulDiv, |
| 67 | [(set (v4i32 VECREG:$rT), (int_spu_si_mpya (v8i16 VECREG:$rA), |
| 68 | (v8i16 VECREG:$rB), |
| 69 | (v8i16 VECREG:$rC)))]>; |
| 70 | |
| 71 | def CellSDKmpyh: |
| 72 | RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 73 | "mpyh $rT, $rA, $rB", IntegerMulDiv, |
| 74 | [(set (v4i32 VECREG:$rT), (int_spu_si_mpyh (v4i32 VECREG:$rA), |
| 75 | (v8i16 VECREG:$rB)))]>; |
| 76 | |
| 77 | def CellSDKmpys: |
| 78 | RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 79 | "mpys $rT, $rA, $rB", IntegerMulDiv, |
| 80 | [(set (v4i32 VECREG:$rT), (int_spu_si_mpys (v8i16 VECREG:$rA), |
| 81 | (v8i16 VECREG:$rB)))]>; |
| 82 | |
| 83 | def CellSDKmpyhh: |
| 84 | RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 85 | "mpyhh $rT, $rA, $rB", IntegerMulDiv, |
| 86 | [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhh (v8i16 VECREG:$rA), |
| 87 | (v8i16 VECREG:$rB)))]>; |
| 88 | |
| 89 | def CellSDKmpyhha: |
| 90 | RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 91 | "mpyhha $rT, $rA, $rB", IntegerMulDiv, |
| 92 | [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhha (v8i16 VECREG:$rA), |
| 93 | (v8i16 VECREG:$rB)))]>; |
| 94 | |
| 95 | // Not sure how to match a (set $rT, (add $rT (mpyhh $rA, $rB)))... so leave |
| 96 | // as an intrinsic for the time being |
| 97 | def CellSDKmpyhhu: |
| 98 | RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 99 | "mpyhhu $rT, $rA, $rB", IntegerMulDiv, |
| 100 | [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhhu (v8i16 VECREG:$rA), |
| 101 | (v8i16 VECREG:$rB)))]>; |
| 102 | |
| 103 | def CellSDKmpyhhau: |
| 104 | RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 105 | "mpyhhau $rT, $rA, $rB", IntegerMulDiv, |
| 106 | [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhhau (v8i16 VECREG:$rA), |
| 107 | (v8i16 VECREG:$rB)))]>; |
| 108 | |
| 109 | def CellSDKand: |
| 110 | RRForm<0b1000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 111 | "add\t $rT, $rA, $rB", IntegerOp, |
| 112 | [(set (v4i32 VECREG:$rT), |
| 113 | (int_spu_si_and (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; |
| 114 | |
| 115 | def CellSDKandc: |
| 116 | RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 117 | "addc\t $rT, $rA, $rB", IntegerOp, |
| 118 | [(set (v4i32 VECREG:$rT), |
| 119 | (int_spu_si_andc (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; |
| 120 | |
| 121 | def CellSDKandbi: |
| 122 | RI10Form<0b01101000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), |
| 123 | "andbi\t $rT, $rA, $val", BranchResolv, |
| 124 | [(set (v16i8 VECREG:$rT), |
| 125 | (int_spu_si_andbi (v16i8 VECREG:$rA), immU8:$val))]>; |
| 126 | |
| 127 | def CellSDKandhi: |
| 128 | RI10Form<0b10101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 129 | "andhi\t $rT, $rA, $val", BranchResolv, |
| 130 | [(set (v8i16 VECREG:$rT), |
| 131 | (int_spu_si_andhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>; |
| 132 | |
| 133 | def CellSDKandi: |
| 134 | RI10Form<0b00101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 135 | "andi\t $rT, $rA, $val", BranchResolv, |
| 136 | [(set (v4i32 VECREG:$rT), |
| 137 | (int_spu_si_andi (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>; |
| 138 | |
| 139 | def CellSDKor: |
| 140 | RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 141 | "or\t $rT, $rA, $rB", IntegerOp, |
| 142 | [(set (v4i32 VECREG:$rT), |
| 143 | (int_spu_si_or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; |
| 144 | |
| 145 | def CellSDKorc: |
| 146 | RRForm<0b10010011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 147 | "addc\t $rT, $rA, $rB", IntegerOp, |
| 148 | [(set (v4i32 VECREG:$rT), |
| 149 | (int_spu_si_orc (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; |
| 150 | |
| 151 | def CellSDKorbi: |
| 152 | RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), |
| 153 | "orbi\t $rT, $rA, $val", BranchResolv, |
| 154 | [(set (v16i8 VECREG:$rT), |
| 155 | (int_spu_si_orbi (v16i8 VECREG:$rA), immU8:$val))]>; |
| 156 | |
| 157 | def CellSDKorhi: |
| 158 | RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 159 | "orhi\t $rT, $rA, $val", BranchResolv, |
| 160 | [(set (v8i16 VECREG:$rT), |
| 161 | (int_spu_si_orhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>; |
| 162 | |
| 163 | def CellSDKori: |
| 164 | RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 165 | "ori\t $rT, $rA, $val", BranchResolv, |
| 166 | [(set (v4i32 VECREG:$rT), |
| 167 | (int_spu_si_ori (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>; |
| 168 | |
| 169 | def CellSDKxor: |
| 170 | RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 171 | "xor\t $rT, $rA, $rB", IntegerOp, |
| 172 | [(set (v4i32 VECREG:$rT), |
| 173 | (int_spu_si_xor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; |
| 174 | |
| 175 | def CellSDKxorbi: |
| 176 | RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), |
| 177 | "xorbi\t $rT, $rA, $val", BranchResolv, |
| 178 | [(set (v16i8 VECREG:$rT), (int_spu_si_xorbi (v16i8 VECREG:$rA), immU8:$val))]>; |
| 179 | |
| 180 | def CellSDKxorhi: |
| 181 | RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 182 | "xorhi\t $rT, $rA, $val", BranchResolv, |
| 183 | [(set (v8i16 VECREG:$rT), |
| 184 | (int_spu_si_xorhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>; |
| 185 | |
| 186 | def CellSDKxori: |
| 187 | RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 188 | "xori\t $rT, $rA, $val", BranchResolv, |
| 189 | [(set (v4i32 VECREG:$rT), |
| 190 | (int_spu_si_xori (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>; |
| 191 | |
| 192 | def CellSDKnor: |
| 193 | RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 194 | "nor\t $rT, $rA, $rB", IntegerOp, |
| 195 | [(set (v4i32 VECREG:$rT), |
| 196 | (int_spu_si_nor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; |
| 197 | |
| 198 | def CellSDKnand: |
| 199 | RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 200 | "nand\t $rT, $rA, $rB", IntegerOp, |
| 201 | [(set (v4i32 VECREG:$rT), |
| 202 | (int_spu_si_nand (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; |
| 203 | |
| 204 | //===----------------------------------------------------------------------===// |
| 205 | // Shift/rotate intrinsics: |
| 206 | //===----------------------------------------------------------------------===// |
| 207 | |
| 208 | def CellSDKshli: |
| 209 | Pat<(int_spu_si_shli (v4i32 VECREG:$rA), uimm7:$val), |
| 210 | (SHLIv4i32 VECREG:$rA, uimm7:$val)>; |
| 211 | |
| 212 | def CellSDKshlqbi: |
| 213 | Pat<(int_spu_si_shlqbi VECREG:$rA, VECREG:$rB), |
| 214 | (SHLQBIvec VECREG:$rA, VECREG:$rB)>; |
| 215 | |
| 216 | def CellSDKshlqii: |
| 217 | Pat<(int_spu_si_shlqbii VECREG:$rA, uimm7:$val), |
| 218 | (SHLQBIIvec VECREG:$rA, uimm7:$val)>; |
| 219 | |
| 220 | def CellSDKshlqby: |
| 221 | Pat<(int_spu_si_shlqby VECREG:$rA, VECREG:$rB), |
| 222 | (SHLQBYvec VECREG:$rA, VECREG:$rB)>; |
| 223 | |
| 224 | def CellSDKshlqbyi: |
| 225 | Pat<(int_spu_si_shlqbyi VECREG:$rA, uimm7:$val), |
| 226 | (SHLQBYIvec VECREG:$rA, uimm7:$val)>; |
| 227 | |
| 228 | //===----------------------------------------------------------------------===// |
| 229 | // Branch/compare intrinsics: |
| 230 | //===----------------------------------------------------------------------===// |
| 231 | |
| 232 | def CellSDKceq: |
| 233 | RRForm<0b00000011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 234 | "ceq\t $rT, $rA, $rB", BranchResolv, |
| 235 | [(set (v4i32 VECREG:$rT), |
| 236 | (int_spu_si_ceq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; |
| 237 | |
| 238 | def CellSDKceqi: |
| 239 | RI10Form<0b00111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 240 | "ceqi\t $rT, $rA, $val", BranchResolv, |
| 241 | [(set (v4i32 VECREG:$rT), |
| 242 | (int_spu_si_ceqi (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>; |
| 243 | |
| 244 | def CellSDKceqb: |
| 245 | RRForm<0b00001011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 246 | "ceqb\t $rT, $rA, $rB", BranchResolv, |
| 247 | [(set (v16i8 VECREG:$rT), |
| 248 | (int_spu_si_ceqb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>; |
| 249 | |
| 250 | def CellSDKceqbi: |
| 251 | RI10Form<0b01111110, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), |
| 252 | "ceqbi\t $rT, $rA, $val", BranchResolv, |
| 253 | [(set (v16i8 VECREG:$rT), (int_spu_si_ceqbi (v16i8 VECREG:$rA), immU8:$val))]>; |
| 254 | |
| 255 | def CellSDKceqh: |
| 256 | RRForm<0b00010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 257 | "ceqh\t $rT, $rA, $rB", BranchResolv, |
| 258 | [(set (v8i16 VECREG:$rT), |
| 259 | (int_spu_si_ceqh (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>; |
| 260 | |
| 261 | def CellSDKceqhi: |
| 262 | RI10Form<0b10111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 263 | "ceqhi\t $rT, $rA, $val", BranchResolv, |
| 264 | [(set (v8i16 VECREG:$rT), |
| 265 | (int_spu_si_ceqhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>; |
| 266 | def CellSDKcgth: |
| 267 | RRForm<0b00010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 268 | "cgth\t $rT, $rA, $rB", BranchResolv, |
| 269 | [(set (v8i16 VECREG:$rT), |
| 270 | (int_spu_si_cgth (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>; |
| 271 | |
| 272 | def CellSDKcgthi: |
| 273 | RI10Form<0b10111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 274 | "cgthi\t $rT, $rA, $val", BranchResolv, |
| 275 | [(set (v8i16 VECREG:$rT), |
| 276 | (int_spu_si_cgthi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>; |
| 277 | |
| 278 | def CellSDKcgt: |
| 279 | RRForm<0b00000010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 280 | "cgt\t $rT, $rA, $rB", BranchResolv, |
| 281 | [(set (v4i32 VECREG:$rT), |
| 282 | (int_spu_si_cgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; |
| 283 | |
| 284 | def CellSDKcgti: |
| 285 | RI10Form<0b00110010, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 286 | "cgti\t $rT, $rA, $val", BranchResolv, |
| 287 | [(set (v4i32 VECREG:$rT), |
| 288 | (int_spu_si_cgti (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>; |
| 289 | |
| 290 | def CellSDKcgtb: |
| 291 | RRForm<0b00001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 292 | "cgtb\t $rT, $rA, $rB", BranchResolv, |
| 293 | [(set (v16i8 VECREG:$rT), |
| 294 | (int_spu_si_cgtb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>; |
| 295 | |
| 296 | def CellSDKcgtbi: |
| 297 | RI10Form<0b01110010, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), |
| 298 | "cgtbi\t $rT, $rA, $val", BranchResolv, |
| 299 | [(set (v16i8 VECREG:$rT), (int_spu_si_cgtbi (v16i8 VECREG:$rA), immU8:$val))]>; |
| 300 | |
| 301 | def CellSDKclgth: |
| 302 | RRForm<0b00010011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 303 | "clgth\t $rT, $rA, $rB", BranchResolv, |
| 304 | [(set (v8i16 VECREG:$rT), |
| 305 | (int_spu_si_clgth (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>; |
| 306 | |
| 307 | def CellSDKclgthi: |
| 308 | RI10Form<0b10111010, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 309 | "clgthi\t $rT, $rA, $val", BranchResolv, |
| 310 | [(set (v8i16 VECREG:$rT), |
| 311 | (int_spu_si_clgthi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>; |
| 312 | |
| 313 | def CellSDKclgt: |
| 314 | RRForm<0b00000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 315 | "clgt\t $rT, $rA, $rB", BranchResolv, |
| 316 | [(set (v4i32 VECREG:$rT), |
| 317 | (int_spu_si_clgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; |
| 318 | |
| 319 | def CellSDKclgti: |
| 320 | RI10Form<0b00111010, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), |
| 321 | "clgti\t $rT, $rA, $val", BranchResolv, |
| 322 | [(set (v4i32 VECREG:$rT), |
| 323 | (int_spu_si_clgti (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>; |
| 324 | |
| 325 | def CellSDKclgtb: |
| 326 | RRForm<0b00001011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 327 | "clgtb\t $rT, $rA, $rB", BranchResolv, |
| 328 | [(set (v16i8 VECREG:$rT), |
| 329 | (int_spu_si_clgtb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>; |
| 330 | |
| 331 | def CellSDKclgtbi: |
| 332 | RI10Form<0b01111010, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val), |
| 333 | "clgtbi\t $rT, $rA, $val", BranchResolv, |
| 334 | [(set (v16i8 VECREG:$rT), |
| 335 | (int_spu_si_clgtbi (v16i8 VECREG:$rA), immU8:$val))]>; |
| 336 | |
| 337 | //===----------------------------------------------------------------------===// |
| 338 | // Floating-point intrinsics: |
| 339 | //===----------------------------------------------------------------------===// |
| 340 | |
| 341 | def CellSDKfa: |
| 342 | RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 343 | "fa\t $rT, $rA, $rB", SPrecFP, |
| 344 | [(set (v4f32 VECREG:$rT), (int_spu_si_fa (v4f32 VECREG:$rA), |
| 345 | (v4f32 VECREG:$rB)))]>; |
| 346 | |
| 347 | def CellSDKfs: |
| 348 | RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 349 | "fs\t $rT, $rA, $rB", SPrecFP, |
| 350 | [(set (v4f32 VECREG:$rT), (int_spu_si_fs (v4f32 VECREG:$rA), |
| 351 | (v4f32 VECREG:$rB)))]>; |
| 352 | |
| 353 | def CellSDKfm: |
| 354 | RRForm<0b01100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 355 | "fm\t $rT, $rA, $rB", SPrecFP, |
| 356 | [(set (v4f32 VECREG:$rT), (int_spu_si_fm (v4f32 VECREG:$rA), |
| 357 | (v4f32 VECREG:$rB)))]>; |
| 358 | |
| 359 | def CellSDKfceq: |
| 360 | RRForm<0b01000011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 361 | "fceq\t $rT, $rA, $rB", SPrecFP, |
| 362 | [(set (v4f32 VECREG:$rT), (int_spu_si_fceq (v4f32 VECREG:$rA), |
| 363 | (v4f32 VECREG:$rB)))]>; |
| 364 | |
| 365 | def CellSDKfcgt: |
| 366 | RRForm<0b01000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 367 | "fcgt\t $rT, $rA, $rB", SPrecFP, |
| 368 | [(set (v4f32 VECREG:$rT), (int_spu_si_fcgt (v4f32 VECREG:$rA), |
| 369 | (v4f32 VECREG:$rB)))]>; |
| 370 | |
| 371 | def CellSDKfcmeq: |
| 372 | RRForm<0b01010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 373 | "fcmeq\t $rT, $rA, $rB", SPrecFP, |
| 374 | [(set (v4f32 VECREG:$rT), (int_spu_si_fcmeq (v4f32 VECREG:$rA), |
| 375 | (v4f32 VECREG:$rB)))]>; |
| 376 | |
| 377 | def CellSDKfcmgt: |
| 378 | RRForm<0b01010011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 379 | "fcmgt\t $rT, $rA, $rB", SPrecFP, |
| 380 | [(set (v4f32 VECREG:$rT), (int_spu_si_fcmgt (v4f32 VECREG:$rA), |
| 381 | (v4f32 VECREG:$rB)))]>; |
| 382 | |
| 383 | def CellSDKfma: |
| 384 | RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), |
| 385 | "fma\t $rT, $rA, $rB, $rC", SPrecFP, |
| 386 | [(set (v4f32 VECREG:$rT), (int_spu_si_fma (v4f32 VECREG:$rA), |
| 387 | (v4f32 VECREG:$rB), |
| 388 | (v4f32 VECREG:$rC)))]>; |
| 389 | |
| 390 | def CellSDKfnms: |
| 391 | RRRForm<0b1011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), |
| 392 | "fnms\t $rT, $rA, $rB, $rC", SPrecFP, |
| 393 | [(set (v4f32 VECREG:$rT), (int_spu_si_fnms (v4f32 VECREG:$rA), |
| 394 | (v4f32 VECREG:$rB), |
| 395 | (v4f32 VECREG:$rC)))]>; |
| 396 | |
| 397 | def CellSDKfms: |
| 398 | RRRForm<0b1111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC), |
| 399 | "fms\t $rT, $rA, $rB, $rC", SPrecFP, |
| 400 | [(set (v4f32 VECREG:$rT), (int_spu_si_fms (v4f32 VECREG:$rA), |
| 401 | (v4f32 VECREG:$rB), |
| 402 | (v4f32 VECREG:$rC)))]>; |
| 403 | |
| 404 | //===----------------------------------------------------------------------===// |
| 405 | // Double precision floating-point intrinsics: |
| 406 | //===----------------------------------------------------------------------===// |
| 407 | |
| 408 | def CellSDKdfa: |
| 409 | RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 410 | "dfa\t $rT, $rA, $rB", DPrecFP, |
| 411 | [(set (v2f64 VECREG:$rT), (int_spu_si_dfa (v2f64 VECREG:$rA), |
| 412 | (v2f64 VECREG:$rB)))]>; |
| 413 | |
| 414 | def CellSDKdfs: |
| 415 | RRForm<0b10110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 416 | "dfs\t $rT, $rA, $rB", DPrecFP, |
| 417 | [(set (v2f64 VECREG:$rT), (int_spu_si_dfs (v2f64 VECREG:$rA), |
| 418 | (v2f64 VECREG:$rB)))]>; |
| 419 | |
| 420 | def CellSDKdfm: |
| 421 | RRForm<0b01110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 422 | "dfm\t $rT, $rA, $rB", DPrecFP, |
| 423 | [(set (v2f64 VECREG:$rT), (int_spu_si_dfm (v2f64 VECREG:$rA), |
| 424 | (v2f64 VECREG:$rB)))]>; |
| 425 | |
| 426 | def CellSDKdfma: |
| 427 | RRForm<0b00111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 428 | "dfma\t $rT, $rA, $rB", DPrecFP, |
| 429 | [(set (v2f64 VECREG:$rT), (int_spu_si_dfma (v2f64 VECREG:$rA), |
| 430 | (v2f64 VECREG:$rB)))]>; |
| 431 | |
| 432 | def CellSDKdfnma: |
| 433 | RRForm<0b11111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 434 | "dfnma\t $rT, $rA, $rB", DPrecFP, |
| 435 | [(set (v2f64 VECREG:$rT), (int_spu_si_dfnma (v2f64 VECREG:$rA), |
| 436 | (v2f64 VECREG:$rB)))]>; |
| 437 | |
| 438 | def CellSDKdfnms: |
| 439 | RRForm<0b01111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 440 | "dfnms\t $rT, $rA, $rB", DPrecFP, |
| 441 | [(set (v2f64 VECREG:$rT), (int_spu_si_dfnms (v2f64 VECREG:$rA), |
| 442 | (v2f64 VECREG:$rB)))]>; |
| 443 | |
| 444 | def CellSDKdfms: |
| 445 | RRForm<0b10111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 446 | "dfms\t $rT, $rA, $rB", DPrecFP, |
| 447 | [(set (v2f64 VECREG:$rT), (int_spu_si_dfms (v2f64 VECREG:$rA), |
| 448 | (v2f64 VECREG:$rB)))]>; |