| Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 1 | //===-- SPUHazardRecognizers.cpp - Cell Hazard Recognizer Impls -----------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file implements hazard recognizers for scheduling on Cell SPU |
| 11 | // processors. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #define DEBUG_TYPE "sched" |
| 16 | |
| 17 | #include "SPUHazardRecognizers.h" |
| 18 | #include "SPU.h" |
| 19 | #include "SPUInstrInfo.h" |
| 20 | #include "llvm/Support/Debug.h" |
| 21 | |
| 22 | using namespace llvm; |
| 23 | |
| 24 | //===----------------------------------------------------------------------===// |
| 25 | // Cell SPU hazard recognizer |
| 26 | // |
| 27 | // This is the pipeline hazard recognizer for the Cell SPU processor. It does |
| 28 | // very little right now. |
| 29 | //===----------------------------------------------------------------------===// |
| 30 | |
| 31 | SPUHazardRecognizer::SPUHazardRecognizer(const TargetInstrInfo &tii) : |
| 32 | TII(tii), |
| 33 | EvenOdd(0) |
| 34 | { |
| 35 | } |
| 36 | |
| 37 | /// Return the pipeline hazard type encountered or generated by this |
| 38 | /// instruction. Currently returns NoHazard. |
| 39 | /// |
| 40 | /// \return NoHazard |
| 41 | HazardRecognizer::HazardType |
| 42 | SPUHazardRecognizer::getHazardType(SDNode *Node) |
| 43 | { |
| 44 | // Initial thoughts on how to do this, but this code cannot work unless the |
| 45 | // function's prolog and epilog code are also being scheduled so that we can |
| 46 | // accurately determine which pipeline is being scheduled. |
| 47 | #if 0 |
| 48 | HazardRecognizer::HazardType retval = NoHazard; |
| 49 | bool mustBeOdd = false; |
| 50 | |
| 51 | switch (Node->getOpcode()) { |
| 52 | case SPU::LQDv16i8: |
| 53 | case SPU::LQDv8i16: |
| 54 | case SPU::LQDv4i32: |
| 55 | case SPU::LQDv4f32: |
| 56 | case SPU::LQDv2f64: |
| 57 | case SPU::LQDr128: |
| 58 | case SPU::LQDr64: |
| 59 | case SPU::LQDr32: |
| 60 | case SPU::LQDr16: |
| 61 | case SPU::LQAv16i8: |
| 62 | case SPU::LQAv8i16: |
| 63 | case SPU::LQAv4i32: |
| 64 | case SPU::LQAv4f32: |
| 65 | case SPU::LQAv2f64: |
| 66 | case SPU::LQAr128: |
| 67 | case SPU::LQAr64: |
| 68 | case SPU::LQAr32: |
| 69 | case SPU::LQXv4i32: |
| 70 | case SPU::LQXr128: |
| 71 | case SPU::LQXr64: |
| 72 | case SPU::LQXr32: |
| 73 | case SPU::LQXr16: |
| 74 | case SPU::STQDv16i8: |
| 75 | case SPU::STQDv8i16: |
| 76 | case SPU::STQDv4i32: |
| 77 | case SPU::STQDv4f32: |
| 78 | case SPU::STQDv2f64: |
| 79 | case SPU::STQDr128: |
| 80 | case SPU::STQDr64: |
| 81 | case SPU::STQDr32: |
| 82 | case SPU::STQDr16: |
| 83 | case SPU::STQDr8: |
| 84 | case SPU::STQAv16i8: |
| 85 | case SPU::STQAv8i16: |
| 86 | case SPU::STQAv4i32: |
| 87 | case SPU::STQAv4f32: |
| 88 | case SPU::STQAv2f64: |
| 89 | case SPU::STQAr128: |
| 90 | case SPU::STQAr64: |
| 91 | case SPU::STQAr32: |
| 92 | case SPU::STQAr16: |
| 93 | case SPU::STQAr8: |
| 94 | case SPU::STQXv16i8: |
| 95 | case SPU::STQXv8i16: |
| 96 | case SPU::STQXv4i32: |
| 97 | case SPU::STQXv4f32: |
| 98 | case SPU::STQXv2f64: |
| 99 | case SPU::STQXr128: |
| 100 | case SPU::STQXr64: |
| 101 | case SPU::STQXr32: |
| 102 | case SPU::STQXr16: |
| 103 | case SPU::STQXr8: |
| 104 | case SPU::RET: |
| 105 | mustBeOdd = true; |
| 106 | break; |
| 107 | default: |
| 108 | // Assume that this instruction can be on the even pipe |
| 109 | break; |
| 110 | } |
| 111 | |
| 112 | if (mustBeOdd && !EvenOdd) |
| 113 | retval = Hazard; |
| 114 | |
| 115 | DOUT << "SPUHazardRecognizer EvenOdd " << EvenOdd << " Hazard " << retval << "\n"; |
| 116 | EvenOdd ^= 1; |
| 117 | return retval; |
| 118 | #else |
| 119 | return NoHazard; |
| 120 | #endif |
| 121 | } |
| 122 | |
| 123 | void SPUHazardRecognizer::EmitInstruction(SDNode *Node) |
| 124 | { |
| 125 | } |
| 126 | |
| 127 | void SPUHazardRecognizer::AdvanceCycle() |
| 128 | { |
| 129 | DOUT << "SPUHazardRecognizer::AdvanceCycle\n"; |
| 130 | } |
| 131 | |
| 132 | void SPUHazardRecognizer::EmitNoop() |
| 133 | { |
| 134 | AdvanceCycle(); |
| 135 | } |