Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 1 | //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===// |
Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines a pattern matching instruction selector for the Cell SPU, |
| 11 | // converting from a legalized dag to a SPU-target dag. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #include "SPU.h" |
| 16 | #include "SPUTargetMachine.h" |
| 17 | #include "SPUISelLowering.h" |
| 18 | #include "SPUHazardRecognizers.h" |
| 19 | #include "SPUFrameInfo.h" |
| 20 | #include "llvm/CodeGen/MachineConstantPool.h" |
| 21 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 22 | #include "llvm/CodeGen/MachineFunction.h" |
| 23 | #include "llvm/CodeGen/SSARegMap.h" |
| 24 | #include "llvm/CodeGen/SelectionDAG.h" |
| 25 | #include "llvm/CodeGen/SelectionDAGISel.h" |
| 26 | #include "llvm/Target/TargetOptions.h" |
| 27 | #include "llvm/ADT/Statistic.h" |
| 28 | #include "llvm/Constants.h" |
| 29 | #include "llvm/GlobalValue.h" |
| 30 | #include "llvm/Intrinsics.h" |
| 31 | #include "llvm/Support/Debug.h" |
| 32 | #include "llvm/Support/MathExtras.h" |
| 33 | #include "llvm/Support/Compiler.h" |
| 34 | #include <iostream> |
| 35 | #include <queue> |
| 36 | #include <set> |
| 37 | |
| 38 | using namespace llvm; |
| 39 | |
| 40 | namespace { |
| 41 | //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates |
| 42 | bool |
| 43 | isI64IntS10Immediate(ConstantSDNode *CN) |
| 44 | { |
| 45 | return isS10Constant(CN->getValue()); |
| 46 | } |
| 47 | |
| 48 | //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates |
| 49 | bool |
| 50 | isI32IntS10Immediate(ConstantSDNode *CN) |
| 51 | { |
| 52 | return isS10Constant((int) CN->getValue()); |
| 53 | } |
| 54 | |
| 55 | #if 0 |
| 56 | //! SDNode predicate for sign-extended, 10-bit immediate values |
| 57 | bool |
| 58 | isI32IntS10Immediate(SDNode *N) |
| 59 | { |
| 60 | return (N->getOpcode() == ISD::Constant |
| 61 | && isI32IntS10Immediate(cast<ConstantSDNode>(N))); |
| 62 | } |
| 63 | #endif |
| 64 | |
Scott Michel | 504c369 | 2007-12-17 22:32:34 +0000 | [diff] [blame] | 65 | //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values |
| 66 | bool |
| 67 | isI32IntU10Immediate(ConstantSDNode *CN) |
| 68 | { |
| 69 | return isU10Constant((int) CN->getValue()); |
| 70 | } |
| 71 | |
Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 72 | //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values |
| 73 | bool |
| 74 | isI16IntS10Immediate(ConstantSDNode *CN) |
| 75 | { |
| 76 | return isS10Constant((short) CN->getValue()); |
| 77 | } |
| 78 | |
| 79 | //! SDNode predicate for i16 sign-extended, 10-bit immediate values |
| 80 | bool |
| 81 | isI16IntS10Immediate(SDNode *N) |
| 82 | { |
| 83 | return (N->getOpcode() == ISD::Constant |
| 84 | && isI16IntS10Immediate(cast<ConstantSDNode>(N))); |
| 85 | } |
| 86 | |
Scott Michel | ec2a08f | 2007-12-15 00:38:50 +0000 | [diff] [blame] | 87 | //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values |
| 88 | bool |
| 89 | isI16IntU10Immediate(ConstantSDNode *CN) |
| 90 | { |
| 91 | return isU10Constant((short) CN->getValue()); |
| 92 | } |
| 93 | |
| 94 | //! SDNode predicate for i16 sign-extended, 10-bit immediate values |
| 95 | bool |
| 96 | isI16IntU10Immediate(SDNode *N) |
| 97 | { |
| 98 | return (N->getOpcode() == ISD::Constant |
| 99 | && isI16IntU10Immediate(cast<ConstantSDNode>(N))); |
| 100 | } |
| 101 | |
Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 102 | //! ConstantSDNode predicate for signed 16-bit values |
| 103 | /*! |
| 104 | \arg CN The constant SelectionDAG node holding the value |
| 105 | \arg Imm The returned 16-bit value, if returning true |
| 106 | |
| 107 | This predicate tests the value in \a CN to see whether it can be |
| 108 | represented as a 16-bit, sign-extended quantity. Returns true if |
| 109 | this is the case. |
| 110 | */ |
| 111 | bool |
| 112 | isIntS16Immediate(ConstantSDNode *CN, short &Imm) |
| 113 | { |
| 114 | MVT::ValueType vt = CN->getValueType(0); |
| 115 | Imm = (short) CN->getValue(); |
| 116 | if (vt >= MVT::i1 && vt <= MVT::i16) { |
| 117 | return true; |
| 118 | } else if (vt == MVT::i32) { |
| 119 | int32_t i_val = (int32_t) CN->getValue(); |
| 120 | short s_val = (short) i_val; |
| 121 | return i_val == s_val; |
| 122 | } else { |
| 123 | int64_t i_val = (int64_t) CN->getValue(); |
| 124 | short s_val = (short) i_val; |
| 125 | return i_val == s_val; |
| 126 | } |
| 127 | |
| 128 | return false; |
| 129 | } |
| 130 | |
| 131 | //! SDNode predicate for signed 16-bit values. |
| 132 | bool |
| 133 | isIntS16Immediate(SDNode *N, short &Imm) |
| 134 | { |
| 135 | return (N->getOpcode() == ISD::Constant |
| 136 | && isIntS16Immediate(cast<ConstantSDNode>(N), Imm)); |
| 137 | } |
| 138 | |
| 139 | //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext. |
| 140 | static bool |
| 141 | isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm) |
| 142 | { |
| 143 | MVT::ValueType vt = FPN->getValueType(0); |
| 144 | if (vt == MVT::f32) { |
Chris Lattner | d3ada75 | 2007-12-22 22:45:38 +0000 | [diff] [blame] | 145 | int val = FloatToBits(FPN->getValueAPF().convertToFloat()); |
Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 146 | int sval = (int) ((val << 16) >> 16); |
| 147 | Imm = (short) val; |
| 148 | return val == sval; |
| 149 | } |
| 150 | |
| 151 | return false; |
| 152 | } |
| 153 | |
| 154 | //===------------------------------------------------------------------===// |
Scott Michel | 86c041f | 2007-12-20 00:44:13 +0000 | [diff] [blame] | 155 | //! MVT::ValueType to "useful stuff" mapping structure: |
Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 156 | |
| 157 | struct valtype_map_s { |
| 158 | MVT::ValueType VT; |
| 159 | unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined) |
| 160 | int prefslot_byte; /// Byte offset of the "preferred" slot |
| 161 | unsigned brcc_eq_ins; /// br_cc equal instruction |
| 162 | unsigned brcc_neq_ins; /// br_cc not equal instruction |
| 163 | }; |
| 164 | |
| 165 | const valtype_map_s valtype_map[] = { |
Scott Michel | 86c041f | 2007-12-20 00:44:13 +0000 | [diff] [blame] | 166 | { MVT::i1, 0, 3, 0, 0 }, |
| 167 | { MVT::i8, 0, 3, 0, 0 }, |
| 168 | { MVT::i16, SPU::ORHIr16, 2, SPU::BRHZ, SPU::BRHNZ }, |
| 169 | { MVT::i32, SPU::ORIr32, 0, SPU::BRZ, SPU::BRNZ }, |
| 170 | { MVT::i64, SPU::ORIr64, 0, 0, 0 }, |
| 171 | { MVT::f32, 0, 0, 0, 0 }, |
| 172 | { MVT::f64, 0, 0, 0, 0 } |
Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 173 | }; |
| 174 | |
| 175 | const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]); |
| 176 | |
| 177 | const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT) |
| 178 | { |
| 179 | const valtype_map_s *retval = 0; |
| 180 | for (size_t i = 0; i < n_valtype_map; ++i) { |
| 181 | if (valtype_map[i].VT == VT) { |
| 182 | retval = valtype_map + i; |
| 183 | break; |
| 184 | } |
| 185 | } |
| 186 | |
| 187 | |
| 188 | #ifndef NDEBUG |
| 189 | if (retval == 0) { |
| 190 | cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for " |
| 191 | << MVT::getValueTypeString(VT) |
| 192 | << "\n"; |
| 193 | abort(); |
| 194 | } |
| 195 | #endif |
| 196 | |
| 197 | return retval; |
| 198 | } |
| 199 | } |
| 200 | |
| 201 | //===--------------------------------------------------------------------===// |
| 202 | /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine |
| 203 | /// instructions for SelectionDAG operations. |
| 204 | /// |
| 205 | class SPUDAGToDAGISel : |
| 206 | public SelectionDAGISel |
| 207 | { |
| 208 | SPUTargetMachine &TM; |
| 209 | SPUTargetLowering &SPUtli; |
| 210 | unsigned GlobalBaseReg; |
| 211 | |
| 212 | public: |
| 213 | SPUDAGToDAGISel(SPUTargetMachine &tm) : |
| 214 | SelectionDAGISel(*tm.getTargetLowering()), |
| 215 | TM(tm), |
| 216 | SPUtli(*tm.getTargetLowering()) |
| 217 | {} |
| 218 | |
| 219 | virtual bool runOnFunction(Function &Fn) { |
| 220 | // Make sure we re-emit a set of the global base reg if necessary |
| 221 | GlobalBaseReg = 0; |
| 222 | SelectionDAGISel::runOnFunction(Fn); |
| 223 | return true; |
| 224 | } |
| 225 | |
| 226 | /// getI32Imm - Return a target constant with the specified value, of type |
| 227 | /// i32. |
| 228 | inline SDOperand getI32Imm(uint32_t Imm) { |
| 229 | return CurDAG->getTargetConstant(Imm, MVT::i32); |
| 230 | } |
| 231 | |
| 232 | /// getI64Imm - Return a target constant with the specified value, of type |
| 233 | /// i64. |
| 234 | inline SDOperand getI64Imm(uint64_t Imm) { |
| 235 | return CurDAG->getTargetConstant(Imm, MVT::i64); |
| 236 | } |
| 237 | |
| 238 | /// getSmallIPtrImm - Return a target constant of pointer type. |
| 239 | inline SDOperand getSmallIPtrImm(unsigned Imm) { |
| 240 | return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy()); |
| 241 | } |
| 242 | |
| 243 | /// Select - Convert the specified operand from a target-independent to a |
| 244 | /// target-specific node if it hasn't already been changed. |
| 245 | SDNode *Select(SDOperand Op); |
| 246 | |
| 247 | /// Return true if the address N is a RI7 format address [r+imm] |
| 248 | bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp, |
| 249 | SDOperand &Base); |
| 250 | |
| 251 | //! Returns true if the address N is an A-form (local store) address |
| 252 | bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, |
| 253 | SDOperand &Index); |
| 254 | |
| 255 | //! D-form address predicate |
| 256 | bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, |
| 257 | SDOperand &Index); |
| 258 | |
| 259 | //! Address predicate if N can be expressed as an indexed [r+r] operation. |
| 260 | bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, |
| 261 | SDOperand &Index); |
| 262 | |
| 263 | /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for |
| 264 | /// inline asm expressions. |
| 265 | virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op, |
| 266 | char ConstraintCode, |
| 267 | std::vector<SDOperand> &OutOps, |
| 268 | SelectionDAG &DAG) { |
| 269 | SDOperand Op0, Op1; |
| 270 | switch (ConstraintCode) { |
| 271 | default: return true; |
| 272 | case 'm': // memory |
| 273 | if (!SelectDFormAddr(Op, Op, Op0, Op1) |
| 274 | && !SelectAFormAddr(Op, Op, Op0, Op1)) |
| 275 | SelectXFormAddr(Op, Op, Op0, Op1); |
| 276 | break; |
| 277 | case 'o': // offsetable |
| 278 | if (!SelectDFormAddr(Op, Op, Op0, Op1) |
| 279 | && !SelectAFormAddr(Op, Op, Op0, Op1)) { |
| 280 | Op0 = Op; |
| 281 | AddToISelQueue(Op0); // r+0. |
| 282 | Op1 = getSmallIPtrImm(0); |
| 283 | } |
| 284 | break; |
| 285 | case 'v': // not offsetable |
| 286 | #if 1 |
| 287 | assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled."); |
| 288 | #else |
| 289 | SelectAddrIdxOnly(Op, Op, Op0, Op1); |
| 290 | #endif |
| 291 | break; |
| 292 | } |
| 293 | |
| 294 | OutOps.push_back(Op0); |
| 295 | OutOps.push_back(Op1); |
| 296 | return false; |
| 297 | } |
| 298 | |
| 299 | /// InstructionSelectBasicBlock - This callback is invoked by |
| 300 | /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. |
| 301 | virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); |
| 302 | |
| 303 | virtual const char *getPassName() const { |
| 304 | return "Cell SPU DAG->DAG Pattern Instruction Selection"; |
| 305 | } |
| 306 | |
| 307 | /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for |
| 308 | /// this target when scheduling the DAG. |
| 309 | virtual HazardRecognizer *CreateTargetHazardRecognizer() { |
| 310 | const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo(); |
| 311 | assert(II && "No InstrInfo?"); |
| 312 | return new SPUHazardRecognizer(*II); |
| 313 | } |
| 314 | |
| 315 | // Include the pieces autogenerated from the target description. |
| 316 | #include "SPUGenDAGISel.inc" |
| 317 | }; |
| 318 | |
| 319 | /// InstructionSelectBasicBlock - This callback is invoked by |
| 320 | /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. |
| 321 | void |
| 322 | SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) |
| 323 | { |
| 324 | DEBUG(BB->dump()); |
| 325 | |
| 326 | // Select target instructions for the DAG. |
| 327 | DAG.setRoot(SelectRoot(DAG.getRoot())); |
| 328 | DAG.RemoveDeadNodes(); |
| 329 | |
| 330 | // Emit machine code to BB. |
| 331 | ScheduleAndEmitDAG(DAG); |
| 332 | } |
| 333 | |
| 334 | bool |
| 335 | SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp, |
| 336 | SDOperand &Base) { |
| 337 | unsigned Opc = N.getOpcode(); |
| 338 | unsigned VT = N.getValueType(); |
| 339 | MVT::ValueType PtrVT = SPUtli.getPointerTy(); |
| 340 | ConstantSDNode *CN = 0; |
| 341 | int Imm; |
| 342 | |
| 343 | if (Opc == ISD::ADD) { |
| 344 | SDOperand Op0 = N.getOperand(0); |
| 345 | SDOperand Op1 = N.getOperand(1); |
| 346 | if (Op1.getOpcode() == ISD::Constant || |
| 347 | Op1.getOpcode() == ISD::TargetConstant) { |
| 348 | CN = cast<ConstantSDNode>(Op1); |
| 349 | Imm = int(CN->getValue()); |
| 350 | if (Imm <= 0xff) { |
| 351 | Disp = CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy()); |
| 352 | Base = Op0; |
| 353 | return true; |
| 354 | } |
| 355 | } |
| 356 | } else if (Opc == ISD::GlobalAddress |
| 357 | || Opc == ISD::TargetGlobalAddress |
| 358 | || Opc == ISD::Register) { |
| 359 | // Plain old local store address: |
| 360 | Disp = CurDAG->getTargetConstant(0, VT); |
| 361 | Base = N; |
| 362 | return true; |
| 363 | } else if (Opc == SPUISD::DFormAddr) { |
| 364 | // D-Form address: This is pretty straightforward, naturally... |
| 365 | CN = cast<ConstantSDNode>(N.getOperand(1)); |
| 366 | assert(CN != 0 && "SelectDFormAddr/SPUISD::DForm2Addr expecting constant"); |
| 367 | Imm = unsigned(CN->getValue()); |
| 368 | if (Imm < 0xff) { |
| 369 | Disp = CurDAG->getTargetConstant(CN->getValue(), PtrVT); |
| 370 | Base = N.getOperand(0); |
| 371 | return true; |
| 372 | } |
| 373 | } |
| 374 | |
| 375 | return false; |
| 376 | } |
| 377 | |
| 378 | /*! |
| 379 | \arg Op The ISD instructio operand |
| 380 | \arg N The address to be tested |
| 381 | \arg Base The base address |
| 382 | \arg Index The base address index |
| 383 | */ |
| 384 | bool |
| 385 | SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, |
| 386 | SDOperand &Index) { |
| 387 | // These match the addr256k operand type: |
| 388 | MVT::ValueType PtrVT = SPUtli.getPointerTy(); |
| 389 | MVT::ValueType OffsVT = MVT::i16; |
| 390 | |
| 391 | switch (N.getOpcode()) { |
| 392 | case ISD::Constant: |
| 393 | case ISD::TargetConstant: { |
| 394 | // Loading from a constant address. |
| 395 | ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N); |
| 396 | int Imm = (int)CN->getValue(); |
| 397 | if (Imm < 0x3ffff && (Imm & 0x3) == 0) { |
| 398 | Base = CurDAG->getTargetConstant(Imm, PtrVT); |
| 399 | // Note that this operand will be ignored by the assembly printer... |
| 400 | Index = CurDAG->getTargetConstant(0, OffsVT); |
| 401 | return true; |
| 402 | } |
| 403 | } |
| 404 | case ISD::ConstantPool: |
| 405 | case ISD::TargetConstantPool: { |
| 406 | // The constant pool address is N. Base is a dummy that will be ignored by |
| 407 | // the assembly printer. |
| 408 | Base = N; |
| 409 | Index = CurDAG->getTargetConstant(0, OffsVT); |
| 410 | return true; |
| 411 | } |
| 412 | |
| 413 | case ISD::GlobalAddress: |
| 414 | case ISD::TargetGlobalAddress: { |
| 415 | // The global address is N. Base is a dummy that is ignored by the |
| 416 | // assembly printer. |
| 417 | Base = N; |
| 418 | Index = CurDAG->getTargetConstant(0, OffsVT); |
| 419 | return true; |
| 420 | } |
| 421 | } |
| 422 | |
| 423 | return false; |
| 424 | } |
| 425 | |
| 426 | /*! |
| 427 | \arg Op The ISD instruction (ignored) |
| 428 | \arg N The address to be tested |
| 429 | \arg Base Base address register/pointer |
| 430 | \arg Index Base address index |
| 431 | |
| 432 | Examine the input address by a base register plus a signed 10-bit |
| 433 | displacement, [r+I10] (D-form address). |
| 434 | |
| 435 | \return true if \a N is a D-form address with \a Base and \a Index set |
| 436 | to non-empty SDOperand instances. |
| 437 | */ |
| 438 | bool |
| 439 | SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, |
| 440 | SDOperand &Index) { |
| 441 | unsigned Opc = N.getOpcode(); |
| 442 | unsigned PtrTy = SPUtli.getPointerTy(); |
| 443 | |
| 444 | if (Opc == ISD::Register) { |
| 445 | Base = N; |
| 446 | Index = CurDAG->getTargetConstant(0, PtrTy); |
| 447 | return true; |
| 448 | } else if (Opc == ISD::FrameIndex) { |
| 449 | // Stack frame index must be less than 512 (divided by 16): |
| 450 | FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N); |
| 451 | DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = " |
| 452 | << FI->getIndex() << "\n"); |
| 453 | if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) { |
| 454 | Base = CurDAG->getTargetConstant(0, PtrTy); |
| 455 | Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy); |
| 456 | return true; |
| 457 | } |
| 458 | } else if (Opc == ISD::ADD) { |
| 459 | // Generated by getelementptr |
| 460 | const SDOperand Op0 = N.getOperand(0); // Frame index/base |
| 461 | const SDOperand Op1 = N.getOperand(1); // Offset within base |
| 462 | ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1); |
| 463 | |
| 464 | // Not a constant? |
| 465 | if (CN == 0) |
| 466 | return false; |
| 467 | |
| 468 | int32_t offset = (int32_t) CN->getSignExtended(); |
| 469 | unsigned Opc0 = Op0.getOpcode(); |
| 470 | |
| 471 | if ((offset & 0xf) != 0) { |
| 472 | cerr << "SelectDFormAddr: unaligned offset = " << offset << "\n"; |
| 473 | abort(); |
| 474 | /*NOTREACHED*/ |
| 475 | } |
| 476 | |
| 477 | if (Opc0 == ISD::FrameIndex) { |
| 478 | FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op0); |
| 479 | DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset |
| 480 | << " frame index = " << FI->getIndex() << "\n"); |
| 481 | |
| 482 | if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) { |
| 483 | Base = CurDAG->getTargetConstant(offset, PtrTy); |
| 484 | Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy); |
| 485 | return true; |
| 486 | } |
| 487 | } else if (offset > SPUFrameInfo::minFrameOffset() |
| 488 | && offset < SPUFrameInfo::maxFrameOffset()) { |
| 489 | Base = CurDAG->getTargetConstant(offset, PtrTy); |
| 490 | if (Opc0 == ISD::GlobalAddress) { |
| 491 | // Convert global address to target global address |
| 492 | GlobalAddressSDNode *GV = dyn_cast<GlobalAddressSDNode>(Op0); |
| 493 | Index = CurDAG->getTargetGlobalAddress(GV->getGlobal(), PtrTy); |
| 494 | return true; |
| 495 | } else { |
| 496 | // Otherwise, just take operand 0 |
| 497 | Index = Op0; |
| 498 | return true; |
| 499 | } |
| 500 | } |
| 501 | } else if (Opc == SPUISD::DFormAddr) { |
| 502 | // D-Form address: This is pretty straightforward, naturally... |
| 503 | ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1)); |
| 504 | assert(CN != 0 && "SelectDFormAddr/SPUISD::DFormAddr expecting constant"); |
| 505 | Base = CurDAG->getTargetConstant(CN->getValue(), PtrTy); |
| 506 | Index = N.getOperand(0); |
| 507 | return true; |
| 508 | } |
| 509 | |
| 510 | return false; |
| 511 | } |
| 512 | |
| 513 | /*! |
| 514 | \arg Op The ISD instruction operand |
| 515 | \arg N The address operand |
| 516 | \arg Base The base pointer operand |
| 517 | \arg Index The offset/index operand |
| 518 | |
| 519 | If the address \a N can be expressed as a [r + s10imm] address, returns false. |
| 520 | Otherwise, creates two operands, Base and Index that will become the [r+r] |
| 521 | address. |
| 522 | */ |
| 523 | bool |
| 524 | SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base, |
| 525 | SDOperand &Index) { |
| 526 | if (SelectAFormAddr(Op, N, Base, Index) |
| 527 | || SelectDFormAddr(Op, N, Base, Index)) |
| 528 | return false; |
| 529 | |
| 530 | unsigned Opc = N.getOpcode(); |
| 531 | |
| 532 | if (Opc == ISD::ADD) { |
| 533 | SDOperand N1 = N.getOperand(0); |
| 534 | SDOperand N2 = N.getOperand(1); |
| 535 | unsigned N1Opc = N1.getOpcode(); |
| 536 | unsigned N2Opc = N2.getOpcode(); |
| 537 | |
| 538 | if ((N1Opc == SPUISD::Hi && N2Opc == SPUISD::Lo) |
| 539 | || (N1Opc == SPUISD::Lo && N2Opc == SPUISD::Hi)) { |
| 540 | Base = N.getOperand(0); |
| 541 | Index = N.getOperand(1); |
| 542 | return true; |
| 543 | } else { |
| 544 | cerr << "SelectXFormAddr: Unhandled ADD operands:\n"; |
| 545 | N1.Val->dump(); |
| 546 | cerr << "\n"; |
| 547 | N2.Val->dump(); |
| 548 | cerr << "\n"; |
| 549 | abort(); |
| 550 | /*UNREACHED*/ |
| 551 | } |
| 552 | } else if (N.getNumOperands() == 2) { |
| 553 | SDOperand N1 = N.getOperand(0); |
| 554 | SDOperand N2 = N.getOperand(1); |
| 555 | unsigned N1Opc = N1.getOpcode(); |
| 556 | unsigned N2Opc = N2.getOpcode(); |
| 557 | |
| 558 | if ((N1Opc == ISD::CopyToReg || N1Opc == ISD::Register) |
| 559 | && (N2Opc == ISD::CopyToReg || N2Opc == ISD::Register)) { |
| 560 | Base = N.getOperand(0); |
| 561 | Index = N.getOperand(1); |
| 562 | return true; |
| 563 | /*UNREACHED*/ |
| 564 | } else { |
| 565 | cerr << "SelectXFormAddr: 2-operand unhandled operand:\n"; |
| 566 | N.Val->dump(); |
| 567 | cerr << "\n"; |
| 568 | abort(); |
| 569 | /*UNREACHED*/ |
| 570 | } |
| 571 | } else { |
| 572 | cerr << "SelectXFormAddr: Unhandled operand type:\n"; |
| 573 | N.Val->dump(); |
| 574 | cerr << "\n"; |
| 575 | abort(); |
| 576 | /*UNREACHED*/ |
| 577 | } |
| 578 | |
| 579 | return false; |
| 580 | } |
| 581 | |
| 582 | //! Convert the operand from a target-independent to a target-specific node |
| 583 | /*! |
| 584 | */ |
| 585 | SDNode * |
| 586 | SPUDAGToDAGISel::Select(SDOperand Op) { |
| 587 | SDNode *N = Op.Val; |
| 588 | unsigned Opc = N->getOpcode(); |
| 589 | |
| 590 | if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) { |
| 591 | return NULL; // Already selected. |
| 592 | } else if (Opc == ISD::FrameIndex) { |
| 593 | // Selects to AIr32 FI, 0 which in turn will become AIr32 SP, imm. |
| 594 | int FI = cast<FrameIndexSDNode>(N)->getIndex(); |
| 595 | SDOperand TFI = CurDAG->getTargetFrameIndex(FI, SPUtli.getPointerTy()); |
| 596 | |
Scott Michel | 9999e68 | 2007-12-19 07:35:06 +0000 | [diff] [blame] | 597 | DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 <FI>, 0\n"); |
Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 598 | return CurDAG->SelectNodeTo(N, SPU::AIr32, Op.getValueType(), TFI, |
| 599 | CurDAG->getTargetConstant(0, MVT::i32)); |
| 600 | } else if (Opc == SPUISD::LDRESULT) { |
| 601 | // Custom select instructions for LDRESULT |
| 602 | unsigned VT = N->getValueType(0); |
| 603 | SDOperand Arg = N->getOperand(0); |
| 604 | SDOperand Chain = N->getOperand(1); |
Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 605 | SDNode *Result; |
Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 606 | |
| 607 | AddToISelQueue(Arg); |
Scott Michel | 86c041f | 2007-12-20 00:44:13 +0000 | [diff] [blame] | 608 | if (!MVT::isFloatingPoint(VT)) { |
| 609 | SDOperand Zero = CurDAG->getTargetConstant(0, VT); |
| 610 | const valtype_map_s *vtm = getValueTypeMapEntry(VT); |
| 611 | |
| 612 | if (vtm->ldresult_ins == 0) { |
| 613 | cerr << "LDRESULT for unsupported type: " |
| 614 | << MVT::getValueTypeString(VT) |
| 615 | << "\n"; |
| 616 | abort(); |
| 617 | } else |
| 618 | Opc = vtm->ldresult_ins; |
| 619 | |
| 620 | AddToISelQueue(Zero); |
| 621 | Result = CurDAG->SelectNodeTo(N, Opc, VT, MVT::Other, Arg, Zero, Chain); |
| 622 | } else { |
| 623 | Result = |
| 624 | CurDAG->SelectNodeTo(N, (VT == MVT::f32 ? SPU::ORf32 : SPU::ORf64), |
| 625 | MVT::Other, Arg, Arg, Chain); |
| 626 | } |
| 627 | |
Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 628 | Chain = SDOperand(Result, 1); |
Scott Michel | 86c041f | 2007-12-20 00:44:13 +0000 | [diff] [blame] | 629 | AddToISelQueue(Chain); |
| 630 | |
Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 631 | return Result; |
| 632 | } |
| 633 | |
| 634 | return SelectCode(Op); |
| 635 | } |
| 636 | |
| 637 | /// createPPCISelDag - This pass converts a legalized DAG into a |
| 638 | /// SPU-specific DAG, ready for instruction scheduling. |
| 639 | /// |
| 640 | FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) { |
| 641 | return new SPUDAGToDAGISel(TM); |
| 642 | } |