Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 1 | //==== SPUInstrFormats.td - Cell SPU Instruction Formats ---*- tablegen -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Scott Michel | 266bc8f | 2007-12-04 22:23:35 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | //===----------------------------------------------------------------------===// |
| 11 | // |
| 12 | // Cell SPU instruction formats. Note that these are notationally similar to |
| 13 | // PowerPC, like "A-Form". But the sizes of operands and fields differ. |
| 14 | |
| 15 | // This was kiped from the PPC instruction formats (seemed like a good idea...) |
| 16 | |
| 17 | class I<dag OOL, dag IOL, string asmstr, InstrItinClass itin> |
| 18 | : Instruction { |
| 19 | field bits<32> Inst; |
| 20 | |
| 21 | let Name = ""; |
| 22 | let Namespace = "SPU"; |
| 23 | let OutOperandList = OOL; |
| 24 | let InOperandList = IOL; |
| 25 | let AsmString = asmstr; |
| 26 | let Itinerary = itin; |
| 27 | } |
| 28 | |
| 29 | // RR Format |
| 30 | class RRForm<bits<11> opcode, dag OOL, dag IOL, string asmstr, |
| 31 | InstrItinClass itin, list<dag> pattern> |
| 32 | : I<OOL, IOL, asmstr, itin> { |
| 33 | bits<7> RA; |
| 34 | bits<7> RB; |
| 35 | bits<7> RT; |
| 36 | |
| 37 | let Pattern = pattern; |
| 38 | |
| 39 | let Inst{0-10} = opcode; |
| 40 | let Inst{11-17} = RB; |
| 41 | let Inst{18-24} = RA; |
| 42 | let Inst{25-31} = RT; |
| 43 | } |
| 44 | |
| 45 | let RB = 0 in { |
| 46 | // RR Format, where RB is zeroed (dont care): |
| 47 | class RRForm_1<bits<11> opcode, dag OOL, dag IOL, string asmstr, |
| 48 | InstrItinClass itin, list<dag> pattern> |
| 49 | : RRForm<opcode, OOL, IOL, asmstr, itin, pattern> |
| 50 | { } |
| 51 | |
| 52 | let RA = 0 in { |
| 53 | // RR Format, where RA and RB are zeroed (dont care): |
| 54 | // Used for reads from status control registers (see FPSCRRr32) |
| 55 | class RRForm_2<bits<11> opcode, dag OOL, dag IOL, string asmstr, |
| 56 | InstrItinClass itin, list<dag> pattern> |
| 57 | : RRForm<opcode, OOL, IOL, asmstr, itin, pattern> |
| 58 | { } |
| 59 | } |
| 60 | } |
| 61 | |
| 62 | let RT = 0 in { |
| 63 | // RR Format, where RT is zeroed (don't care), or as the instruction handbook |
| 64 | // says, "RT is a false target." Used in "Halt if" instructions |
| 65 | class RRForm_3<bits<11> opcode, dag OOL, dag IOL, string asmstr, |
| 66 | InstrItinClass itin, list<dag> pattern> |
| 67 | : RRForm<opcode, OOL, IOL, asmstr, itin, pattern> |
| 68 | { } |
| 69 | } |
| 70 | |
| 71 | // RRR Format |
| 72 | class RRRForm<bits<4> opcode, dag OOL, dag IOL, string asmstr, |
| 73 | InstrItinClass itin, list<dag> pattern> |
| 74 | : I<OOL, IOL, asmstr, itin> |
| 75 | { |
| 76 | bits<7> RA; |
| 77 | bits<7> RB; |
| 78 | bits<7> RC; |
| 79 | bits<7> RT; |
| 80 | |
| 81 | let Pattern = pattern; |
| 82 | |
| 83 | let Inst{0-3} = opcode; |
| 84 | let Inst{4-10} = RT; |
| 85 | let Inst{11-17} = RB; |
| 86 | let Inst{18-24} = RA; |
| 87 | let Inst{25-31} = RC; |
| 88 | } |
| 89 | |
| 90 | // RI7 Format |
| 91 | class RI7Form<bits<11> opcode, dag OOL, dag IOL, string asmstr, |
| 92 | InstrItinClass itin, list<dag> pattern> |
| 93 | : I<OOL, IOL, asmstr, itin> |
| 94 | { |
| 95 | bits<7> i7; |
| 96 | bits<7> RA; |
| 97 | bits<7> RT; |
| 98 | |
| 99 | let Pattern = pattern; |
| 100 | |
| 101 | let Inst{0-10} = opcode; |
| 102 | let Inst{11-17} = i7; |
| 103 | let Inst{18-24} = RA; |
| 104 | let Inst{25-31} = RT; |
| 105 | } |
| 106 | |
| 107 | // CVTIntFp Format |
| 108 | class CVTIntFPForm<bits<10> opcode, dag OOL, dag IOL, string asmstr, |
| 109 | InstrItinClass itin, list<dag> pattern> |
| 110 | : I<OOL, IOL, asmstr, itin> |
| 111 | { |
| 112 | bits<7> RA; |
| 113 | bits<7> RT; |
| 114 | |
| 115 | let Pattern = pattern; |
| 116 | |
| 117 | let Inst{0-9} = opcode; |
| 118 | let Inst{10-17} = 0; |
| 119 | let Inst{18-24} = RA; |
| 120 | let Inst{25-31} = RT; |
| 121 | } |
| 122 | |
| 123 | let RA = 0 in { |
| 124 | class BICondForm<bits<11> opcode, string asmstr, list<dag> pattern> |
| 125 | : RRForm<opcode, (outs), (ins R32C:$rA, R32C:$func), asmstr, |
| 126 | BranchResolv, pattern> |
| 127 | { } |
| 128 | |
| 129 | let RT = 0 in { |
| 130 | // Branch instruction format (without D/E flag settings) |
| 131 | class BRForm<bits<11> opcode, dag OOL, dag IOL, string asmstr, |
| 132 | InstrItinClass itin, list<dag> pattern> |
| 133 | : RRForm<opcode, OOL, IOL, asmstr, itin, pattern> |
| 134 | { } |
| 135 | |
| 136 | class BIForm<bits<11> opcode, string asmstr, list<dag> pattern> |
| 137 | : RRForm<opcode, (outs), (ins R32C:$func), asmstr, BranchResolv, |
| 138 | pattern> |
| 139 | { } |
| 140 | |
| 141 | let RB = 0 in { |
| 142 | // Return instruction (bi, branch indirect), RA is zero (LR): |
| 143 | class RETForm<string asmstr, list<dag> pattern> |
| 144 | : BRForm<0b00010101100, (outs), (ins), asmstr, BranchResolv, |
| 145 | pattern> |
| 146 | { } |
| 147 | } |
| 148 | } |
| 149 | } |
| 150 | |
| 151 | // Branch indirect external data forms: |
| 152 | class BISLEDForm<bits<2> DE_flag, string asmstr, list<dag> pattern> |
| 153 | : I<(outs), (ins indcalltarget:$func), asmstr, BranchResolv> |
| 154 | { |
| 155 | bits<7> Rcalldest; |
| 156 | |
| 157 | let Pattern = pattern; |
| 158 | |
| 159 | let Inst{0-10} = 0b11010101100; |
| 160 | let Inst{11} = 0; |
| 161 | let Inst{12-13} = DE_flag; |
| 162 | let Inst{14-17} = 0b0000; |
| 163 | let Inst{18-24} = Rcalldest; |
| 164 | let Inst{25-31} = 0b0000000; |
| 165 | } |
| 166 | |
| 167 | // RI10 Format |
| 168 | class RI10Form<bits<8> opcode, dag OOL, dag IOL, string asmstr, |
| 169 | InstrItinClass itin, list<dag> pattern> |
| 170 | : I<OOL, IOL, asmstr, itin> |
| 171 | { |
| 172 | bits<10> i10; |
| 173 | bits<7> RA; |
| 174 | bits<7> RT; |
| 175 | |
| 176 | let Pattern = pattern; |
| 177 | |
| 178 | let Inst{0-7} = opcode; |
| 179 | let Inst{8-17} = i10; |
| 180 | let Inst{18-24} = RA; |
| 181 | let Inst{25-31} = RT; |
| 182 | } |
| 183 | |
| 184 | // RI10 Format, where the constant is zero (or effectively ignored by the |
| 185 | // SPU) |
| 186 | class RI10Form_1<bits<8> opcode, dag OOL, dag IOL, string asmstr, |
| 187 | InstrItinClass itin, list<dag> pattern> |
| 188 | : I<OOL, IOL, asmstr, itin> |
| 189 | { |
| 190 | bits<7> RA; |
| 191 | bits<7> RT; |
| 192 | |
| 193 | let Pattern = pattern; |
| 194 | |
| 195 | let Inst{0-7} = opcode; |
| 196 | let Inst{8-17} = 0; |
| 197 | let Inst{18-24} = RA; |
| 198 | let Inst{25-31} = RT; |
| 199 | } |
| 200 | |
| 201 | // RI10 Format, where RT is ignored. |
| 202 | // This format is used primarily by the Halt If ... Immediate set of |
| 203 | // instructions |
| 204 | class RI10Form_2<bits<8> opcode, dag OOL, dag IOL, string asmstr, |
| 205 | InstrItinClass itin, list<dag> pattern> |
| 206 | : I<OOL, IOL, asmstr, itin> |
| 207 | { |
| 208 | bits<10> i10; |
| 209 | bits<7> RA; |
| 210 | |
| 211 | let Pattern = pattern; |
| 212 | |
| 213 | let Inst{0-7} = opcode; |
| 214 | let Inst{8-17} = i10; |
| 215 | let Inst{18-24} = RA; |
| 216 | let Inst{25-31} = 0; |
| 217 | } |
| 218 | |
| 219 | // RI16 Format |
| 220 | class RI16Form<bits<9> opcode, dag OOL, dag IOL, string asmstr, |
| 221 | InstrItinClass itin, list<dag> pattern> |
| 222 | : I<OOL, IOL, asmstr, itin> |
| 223 | { |
| 224 | bits<16> i16; |
| 225 | bits<7> RT; |
| 226 | |
| 227 | let Pattern = pattern; |
| 228 | |
| 229 | let Inst{0-8} = opcode; |
| 230 | let Inst{9-24} = i16; |
| 231 | let Inst{25-31} = RT; |
| 232 | } |
| 233 | |
| 234 | // Specialized version of the RI16 Format for unconditional branch relative and |
| 235 | // branch absolute, branch and set link. Note that for branch and set link, the |
| 236 | // link register doesn't have to be $lr, but this is actually hard coded into |
| 237 | // the instruction pattern. |
| 238 | |
| 239 | let RT = 0 in { |
| 240 | class UncondBranch<bits<9> opcode, dag OOL, dag IOL, string asmstr, |
| 241 | list<dag> pattern> |
| 242 | : RI16Form<opcode, OOL, IOL, asmstr, BranchResolv, pattern> |
| 243 | { } |
| 244 | |
| 245 | class BranchSetLink<bits<9> opcode, dag OOL, dag IOL, string asmstr, |
| 246 | list<dag> pattern> |
| 247 | : RI16Form<opcode, OOL, IOL, asmstr, BranchResolv, pattern> |
| 248 | { } |
| 249 | } |
| 250 | |
| 251 | // RI18 Format |
| 252 | class RI18Form<bits<7> opcode, dag OOL, dag IOL, string asmstr, |
| 253 | InstrItinClass itin, list<dag> pattern> |
| 254 | : I<OOL, IOL, asmstr, itin> |
| 255 | { |
| 256 | bits<18> i18; |
| 257 | bits<7> RT; |
| 258 | |
| 259 | let Pattern = pattern; |
| 260 | |
| 261 | let Inst{0-6} = opcode; |
| 262 | let Inst{7-24} = i18; |
| 263 | let Inst{25-31} = RT; |
| 264 | } |
| 265 | |
| 266 | //===----------------------------------------------------------------------===// |
| 267 | // Instruction formats for intrinsics: |
| 268 | //===----------------------------------------------------------------------===// |
| 269 | |
| 270 | // RI10 Format for v8i16 intrinsics |
| 271 | class RI10_Int_v8i16<bits<8> opcode, string opc, InstrItinClass itin, |
| 272 | Intrinsic IntID> : |
| 273 | RI10Form<opcode, (outs VECREG:$rT), (ins s10imm:$val, VECREG:$rA), |
| 274 | !strconcat(opc, " $rT, $rA, $val"), itin, |
| 275 | [(set (v8i16 VECREG:$rT), (IntID (v8i16 VECREG:$rA), |
| 276 | i16ImmSExt10:$val))] >; |
| 277 | |
| 278 | class RI10_Int_v4i32<bits<8> opcode, string opc, InstrItinClass itin, |
| 279 | Intrinsic IntID> : |
| 280 | RI10Form<opcode, (outs VECREG:$rT), (ins s10imm:$val, VECREG:$rA), |
| 281 | !strconcat(opc, " $rT, $rA, $val"), itin, |
| 282 | [(set (v4i32 VECREG:$rT), (IntID (v4i32 VECREG:$rA), |
| 283 | i32ImmSExt10:$val))] >; |
| 284 | |
| 285 | // RR Format for v8i16 intrinsics |
| 286 | class RR_Int_v8i16<bits<11> opcode, string opc, InstrItinClass itin, |
| 287 | Intrinsic IntID> : |
| 288 | RRForm<opcode, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 289 | !strconcat(opc, " $rT, $rA, $rB"), itin, |
| 290 | [(set (v8i16 VECREG:$rT), (IntID (v8i16 VECREG:$rA), |
| 291 | (v8i16 VECREG:$rB)))] >; |
| 292 | |
| 293 | // RR Format for v4i32 intrinsics |
| 294 | class RR_Int_v4i32<bits<11> opcode, string opc, InstrItinClass itin, |
| 295 | Intrinsic IntID> : |
| 296 | RRForm<opcode, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), |
| 297 | !strconcat(opc, " $rT, $rA, $rB"), itin, |
| 298 | [(set (v4i32 VECREG:$rT), (IntID (v4i32 VECREG:$rA), |
| 299 | (v4i32 VECREG:$rB)))] >; |
| 300 | |
| 301 | //===----------------------------------------------------------------------===// |
| 302 | // Pseudo instructions, like call frames: |
| 303 | //===----------------------------------------------------------------------===// |
| 304 | |
| 305 | class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> |
| 306 | : I<OOL, IOL, asmstr, NoItinerary> { |
| 307 | let Pattern = pattern; |
| 308 | let Inst{31-0} = 0; |
| 309 | } |