Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 1 | //===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // Cell SPU Instruction Operands: |
| 10 | //===----------------------------------------------------------------------===// |
| 11 | |
| 12 | def LO16 : SDNodeXForm<imm, [{ |
| 13 | unsigned val = N->getValue(); |
| 14 | // Transformation function: get the low 16 bits. |
| 15 | return getI32Imm(val & 0xffff); |
| 16 | }]>; |
| 17 | |
| 18 | def LO16_vec : SDNodeXForm<scalar_to_vector, [{ |
| 19 | SDOperand OpVal(0, 0); |
| 20 | |
| 21 | // Transformation function: get the low 16 bit immediate from a build_vector |
| 22 | // node. |
| 23 | assert(N->getOpcode() == ISD::BUILD_VECTOR |
| 24 | && "LO16_vec got something other than a BUILD_VECTOR"); |
| 25 | |
| 26 | // Get first constant operand... |
| 27 | for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) { |
| 28 | if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; |
| 29 | if (OpVal.Val == 0) |
| 30 | OpVal = N->getOperand(i); |
| 31 | } |
| 32 | |
| 33 | assert(OpVal.Val != 0 && "LO16_vec did not locate a <defined> node"); |
| 34 | ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal); |
| 35 | return getI32Imm((unsigned)CN->getValue() & 0xffff); |
| 36 | }]>; |
| 37 | |
| 38 | // Transform an immediate, returning the high 16 bits shifted down: |
| 39 | def HI16 : SDNodeXForm<imm, [{ |
| 40 | return getI32Imm((unsigned)N->getValue() >> 16); |
| 41 | }]>; |
| 42 | |
| 43 | // Transformation function: shift the high 16 bit immediate from a build_vector |
| 44 | // node into the low 16 bits, and return a 16-bit constant. |
| 45 | def HI16_vec : SDNodeXForm<scalar_to_vector, [{ |
| 46 | SDOperand OpVal(0, 0); |
| 47 | |
| 48 | assert(N->getOpcode() == ISD::BUILD_VECTOR |
| 49 | && "HI16_vec got something other than a BUILD_VECTOR"); |
| 50 | |
| 51 | // Get first constant operand... |
| 52 | for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) { |
| 53 | if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; |
| 54 | if (OpVal.Val == 0) |
| 55 | OpVal = N->getOperand(i); |
| 56 | } |
| 57 | |
| 58 | assert(OpVal.Val != 0 && "HI16_vec did not locate a <defined> node"); |
| 59 | ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal); |
| 60 | return getI32Imm((unsigned)CN->getValue() >> 16); |
| 61 | }]>; |
| 62 | |
| 63 | // simm7 predicate - True if the immediate fits in an 7-bit signed |
| 64 | // field. |
| 65 | def simm7: PatLeaf<(imm), [{ |
| 66 | int sextVal = ((((int) N->getValue()) << 25) >> 25); |
| 67 | return (sextVal >= -64 && sextVal <= 63); |
| 68 | }]>; |
| 69 | |
| 70 | // uimm7 predicate - True if the immediate fits in an 7-bit unsigned |
| 71 | // field. |
| 72 | def uimm7: PatLeaf<(imm), [{ |
| 73 | return (N->getValue() <= 0x7f); |
| 74 | }]>; |
| 75 | |
| 76 | // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended |
| 77 | // field. |
| 78 | def immSExt8 : PatLeaf<(imm), [{ |
| 79 | int Value = (int) N->getValue(); |
| 80 | int Value8 = (Value << 24) >> 24; |
| 81 | return (Value < 0xff && (Value8 >= -128 && Value8 < 127)); |
| 82 | }]>; |
| 83 | |
| 84 | // immU8: immediate, unsigned 8-bit quantity |
| 85 | def immU8 : PatLeaf<(imm), [{ |
| 86 | return (N->getValue() <= 0xff); |
| 87 | }]>; |
| 88 | |
| 89 | // i64ImmSExt10 predicate - True if the i64 immediate fits in a 10-bit sign |
| 90 | // extended field. Used by RI10Form instructions like 'ldq'. |
| 91 | def i64ImmSExt10 : PatLeaf<(imm), [{ |
| 92 | return isI64IntS10Immediate(N); |
| 93 | }]>; |
| 94 | |
| 95 | // i32ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign |
| 96 | // extended field. Used by RI10Form instructions like 'ldq'. |
| 97 | def i32ImmSExt10 : PatLeaf<(imm), [{ |
| 98 | return isI32IntS10Immediate(N); |
| 99 | }]>; |
| 100 | |
Scott Michel | 504c369 | 2007-12-17 22:32:34 +0000 | [diff] [blame] | 101 | // i32ImmUns10 predicate - True if the i32 immediate fits in a 10-bit unsigned |
| 102 | // field. Used by RI10Form instructions like 'ldq'. |
| 103 | def i32ImmUns10 : PatLeaf<(imm), [{ |
| 104 | return isI32IntU10Immediate(N); |
| 105 | }]>; |
| 106 | |
Scott Michel | ec2a08f | 2007-12-15 00:38:50 +0000 | [diff] [blame] | 107 | // i16ImmSExt10 predicate - True if the i16 immediate fits in a 10-bit sign |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 108 | // extended field. Used by RI10Form instructions like 'ldq'. |
| 109 | def i16ImmSExt10 : PatLeaf<(imm), [{ |
| 110 | return isI16IntS10Immediate(N); |
| 111 | }]>; |
| 112 | |
Scott Michel | 504c369 | 2007-12-17 22:32:34 +0000 | [diff] [blame] | 113 | // i16ImmUns10 predicate - True if the i16 immediate fits into a 10-bit unsigned |
Scott Michel | ec2a08f | 2007-12-15 00:38:50 +0000 | [diff] [blame] | 114 | // value. Used by RI10Form instructions. |
Scott Michel | 504c369 | 2007-12-17 22:32:34 +0000 | [diff] [blame] | 115 | def i16ImmUns10 : PatLeaf<(imm), [{ |
Scott Michel | ec2a08f | 2007-12-15 00:38:50 +0000 | [diff] [blame] | 116 | return isI16IntU10Immediate(N); |
| 117 | }]>; |
| 118 | |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 119 | def immSExt16 : PatLeaf<(imm), [{ |
| 120 | // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended |
| 121 | // field. |
| 122 | short Ignored; |
| 123 | return isIntS16Immediate(N, Ignored); |
| 124 | }]>; |
| 125 | |
| 126 | def immZExt16 : PatLeaf<(imm), [{ |
| 127 | // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended |
| 128 | // field. |
| 129 | return (uint64_t)N->getValue() == (unsigned short)N->getValue(); |
| 130 | }], LO16>; |
| 131 | |
| 132 | def immU16 : PatLeaf<(imm), [{ |
| 133 | // immU16 predicate- True if the immediate fits into a 16-bit unsigned field. |
| 134 | return (uint64_t)N->getValue() == (N->getValue() & 0xffff); |
| 135 | }]>; |
| 136 | |
| 137 | def imm18 : PatLeaf<(imm), [{ |
| 138 | // imm18 predicate: True if the immediate fits into an 18-bit unsigned field. |
| 139 | int Value = (int) N->getValue(); |
| 140 | return ((Value & ((1 << 19) - 1)) == Value); |
| 141 | }]>; |
| 142 | |
| 143 | def hi16 : PatLeaf<(imm), [{ |
| 144 | // hi16 predicate - returns true if the immediate has all zeros in the |
| 145 | // low order bits and is a 32-bit constant: |
| 146 | if (N->getValueType(0) == MVT::i32) { |
| 147 | uint32_t val = N->getValue(); |
| 148 | return ((val & 0xffff0000) == val); |
| 149 | } |
| 150 | |
| 151 | return false; |
| 152 | }], HI16>; |
| 153 | |
| 154 | //===----------------------------------------------------------------------===// |
| 155 | // Floating point operands: |
| 156 | //===----------------------------------------------------------------------===// |
| 157 | |
| 158 | // Transform a float, returning the high 16 bits shifted down, as if |
| 159 | // the float was really an unsigned integer: |
| 160 | def HI16_f32 : SDNodeXForm<fpimm, [{ |
Chris Lattner | 10d724a | 2007-12-16 20:41:33 +0000 | [diff] [blame] | 161 | float fval = N->getValueAPF().convertToFloat(); |
| 162 | return getI32Imm(FloatToBits(fval) >> 16); |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 163 | }]>; |
| 164 | |
| 165 | // Transformation function on floats: get the low 16 bits as if the float was |
| 166 | // an unsigned integer. |
| 167 | def LO16_f32 : SDNodeXForm<fpimm, [{ |
Chris Lattner | 10d724a | 2007-12-16 20:41:33 +0000 | [diff] [blame] | 168 | float fval = N->getValueAPF().convertToFloat(); |
| 169 | return getI32Imm(FloatToBits(fval) & 0xffff); |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 170 | }]>; |
| 171 | |
| 172 | def FPimm_sext16 : SDNodeXForm<fpimm, [{ |
Chris Lattner | 10d724a | 2007-12-16 20:41:33 +0000 | [diff] [blame] | 173 | float fval = N->getValueAPF().convertToFloat(); |
| 174 | return getI32Imm((int) ((FloatToBits(fval) << 16) >> 16)); |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 175 | }]>; |
| 176 | |
| 177 | def FPimm_u18 : SDNodeXForm<fpimm, [{ |
Chris Lattner | 10d724a | 2007-12-16 20:41:33 +0000 | [diff] [blame] | 178 | float fval = N->getValueAPF().convertToFloat(); |
| 179 | return getI32Imm(FloatToBits(fval) & ((1 << 19) - 1)); |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 180 | }]>; |
| 181 | |
| 182 | def fpimmSExt16 : PatLeaf<(fpimm), [{ |
| 183 | short Ignored; |
| 184 | return isFPS16Immediate(N, Ignored); |
| 185 | }], FPimm_sext16>; |
| 186 | |
| 187 | // Does the SFP constant only have upp 16 bits set? |
| 188 | def hi16_f32 : PatLeaf<(fpimm), [{ |
| 189 | if (N->getValueType(0) == MVT::f32) { |
Chris Lattner | 10d724a | 2007-12-16 20:41:33 +0000 | [diff] [blame] | 190 | uint32_t val = FloatToBits(N->getValueAPF().convertToFloat()); |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 191 | return ((val & 0xffff0000) == val); |
| 192 | } |
| 193 | |
| 194 | return false; |
| 195 | }], HI16_f32>; |
| 196 | |
| 197 | // Does the SFP constant fit into 18 bits? |
| 198 | def fpimm18 : PatLeaf<(fpimm), [{ |
| 199 | if (N->getValueType(0) == MVT::f32) { |
Chris Lattner | 10d724a | 2007-12-16 20:41:33 +0000 | [diff] [blame] | 200 | uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat()); |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 201 | return ((Value & ((1 << 19) - 1)) == Value); |
| 202 | } |
| 203 | |
| 204 | return false; |
| 205 | }], FPimm_u18>; |
| 206 | |
| 207 | //===----------------------------------------------------------------------===// |
Scott Michel | ec2a08f | 2007-12-15 00:38:50 +0000 | [diff] [blame] | 208 | // 64-bit operands (TODO): |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 209 | //===----------------------------------------------------------------------===// |
| 210 | |
| 211 | //===----------------------------------------------------------------------===// |
| 212 | // build_vector operands: |
| 213 | //===----------------------------------------------------------------------===// |
| 214 | |
| 215 | // v16i8SExt8Imm_xform function: convert build_vector to 8-bit sign extended |
| 216 | // immediate constant load for v16i8 vectors. N.B.: The incoming constant has |
| 217 | // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a). |
| 218 | def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{ |
| 219 | return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8); |
| 220 | }]>; |
| 221 | |
| 222 | // v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant |
| 223 | // load, works in conjunction with its transform function. N.B.: This relies the |
| 224 | // incoming constant being a 16-bit quantity, where the upper and lower bytes |
| 225 | // are EXACTLY the same (e.g., 0x2a2a) |
| 226 | def v16i8SExt8Imm: PatLeaf<(build_vector), [{ |
| 227 | return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0; |
| 228 | }], v16i8SExt8Imm_xform>; |
| 229 | |
| 230 | // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit |
| 231 | // immediate constant load for v16i8 vectors. N.B.: The incoming constant has |
| 232 | // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a). |
| 233 | def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{ |
| 234 | return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8); |
| 235 | }]>; |
| 236 | |
| 237 | // v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant |
| 238 | // load, works in conjunction with its transform function. N.B.: This relies the |
| 239 | // incoming constant being a 16-bit quantity, where the upper and lower bytes |
| 240 | // are EXACTLY the same (e.g., 0x2a2a) |
| 241 | def v16i8U8Imm: PatLeaf<(build_vector), [{ |
| 242 | return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0; |
| 243 | }], v16i8U8Imm_xform>; |
| 244 | |
| 245 | // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended |
| 246 | // immediate constant load for v8i16 vectors. |
| 247 | def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{ |
| 248 | return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16); |
| 249 | }]>; |
| 250 | |
| 251 | // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant |
| 252 | // load, works in conjunction with its transform function. |
| 253 | def v8i16SExt8Imm: PatLeaf<(build_vector), [{ |
| 254 | return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).Val != 0; |
| 255 | }], v8i16SExt8Imm_xform>; |
| 256 | |
| 257 | // v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended |
| 258 | // immediate constant load for v8i16 vectors. |
| 259 | def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{ |
| 260 | return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16); |
| 261 | }]>; |
| 262 | |
| 263 | // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant |
| 264 | // load, works in conjunction with its transform function. |
| 265 | def v8i16SExt10Imm: PatLeaf<(build_vector), [{ |
| 266 | return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0; |
| 267 | }], v8i16SExt10Imm_xform>; |
| 268 | |
Scott Michel | 504c369 | 2007-12-17 22:32:34 +0000 | [diff] [blame] | 269 | // v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned |
| 270 | // immediate constant load for v8i16 vectors. |
| 271 | def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{ |
| 272 | return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16); |
| 273 | }]>; |
| 274 | |
| 275 | // v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant |
| 276 | // load, works in conjunction with its transform function. |
| 277 | def v8i16Uns10Imm: PatLeaf<(build_vector), [{ |
| 278 | return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0; |
| 279 | }], v8i16Uns10Imm_xform>; |
| 280 | |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 281 | // v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended |
| 282 | // immediate constant load for v8i16 vectors. |
Scott Michel | 504c369 | 2007-12-17 22:32:34 +0000 | [diff] [blame] | 283 | def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{ |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 284 | return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16); |
| 285 | }]>; |
| 286 | |
| 287 | // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant |
| 288 | // load, works in conjunction with its transform function. |
| 289 | def v8i16SExt16Imm: PatLeaf<(build_vector), [{ |
| 290 | return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0; |
Scott Michel | 504c369 | 2007-12-17 22:32:34 +0000 | [diff] [blame] | 291 | }], v8i16Uns16Imm_xform>; |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 292 | |
| 293 | // v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended |
| 294 | // immediate constant load for v4i32 vectors. |
| 295 | def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{ |
| 296 | return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32); |
| 297 | }]>; |
| 298 | |
| 299 | // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant |
| 300 | // load, works in conjunction with its transform function. |
| 301 | def v4i32SExt10Imm: PatLeaf<(build_vector), [{ |
| 302 | return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0; |
| 303 | }], v4i32SExt10Imm_xform>; |
| 304 | |
Scott Michel | 504c369 | 2007-12-17 22:32:34 +0000 | [diff] [blame] | 305 | // v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned |
| 306 | // immediate constant load for v4i32 vectors. |
| 307 | def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{ |
| 308 | return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32); |
| 309 | }]>; |
| 310 | |
| 311 | // v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant |
| 312 | // load, works in conjunction with its transform function. |
| 313 | def v4i32Uns10Imm: PatLeaf<(build_vector), [{ |
| 314 | return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0; |
| 315 | }], v4i32Uns10Imm_xform>; |
| 316 | |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 317 | // v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended |
| 318 | // immediate constant load for v4i32 vectors. |
| 319 | def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{ |
| 320 | return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32); |
| 321 | }]>; |
| 322 | |
| 323 | // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant |
| 324 | // load, works in conjunction with its transform function. |
| 325 | def v4i32SExt16Imm: PatLeaf<(build_vector), [{ |
| 326 | return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).Val != 0; |
| 327 | }], v4i32SExt16Imm_xform>; |
| 328 | |
| 329 | // v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned |
| 330 | // immediate constant load for v4i32 vectors. |
| 331 | def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{ |
| 332 | return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32); |
| 333 | }]>; |
| 334 | |
| 335 | // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load, |
| 336 | // works in conjunction with its transform function. |
| 337 | def v4i32Uns18Imm: PatLeaf<(build_vector), [{ |
| 338 | return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).Val != 0; |
| 339 | }], v4i32Uns18Imm_xform>; |
| 340 | |
| 341 | // ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant |
| 342 | // load. |
| 343 | def ILHUvec_get_imm: SDNodeXForm<build_vector, [{ |
| 344 | return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32); |
| 345 | }]>; |
| 346 | |
| 347 | /// immILHUvec: Predicate test for a ILHU constant vector. |
| 348 | def immILHUvec: PatLeaf<(build_vector), [{ |
| 349 | return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).Val != 0; |
| 350 | }], ILHUvec_get_imm>; |
| 351 | |
| 352 | // Catch-all for any other i32 vector constants |
| 353 | def v4i32_get_imm: SDNodeXForm<build_vector, [{ |
| 354 | return SPU::get_v4i32_imm(N, *CurDAG); |
| 355 | }]>; |
| 356 | |
| 357 | def v4i32Imm: PatLeaf<(build_vector), [{ |
| 358 | return SPU::get_v4i32_imm(N, *CurDAG).Val != 0; |
| 359 | }], v4i32_get_imm>; |
| 360 | |
| 361 | // v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended |
| 362 | // immediate constant load for v2i64 vectors. |
| 363 | def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{ |
| 364 | return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64); |
| 365 | }]>; |
| 366 | |
| 367 | // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant |
| 368 | // load, works in conjunction with its transform function. |
| 369 | def v2i64SExt10Imm: PatLeaf<(build_vector), [{ |
| 370 | return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).Val != 0; |
| 371 | }], v2i64SExt10Imm_xform>; |
| 372 | |
| 373 | // v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended |
| 374 | // immediate constant load for v2i64 vectors. |
| 375 | def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{ |
| 376 | return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64); |
| 377 | }]>; |
| 378 | |
| 379 | // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant |
| 380 | // load, works in conjunction with its transform function. |
| 381 | def v2i64SExt16Imm: PatLeaf<(build_vector), [{ |
| 382 | return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).Val != 0; |
| 383 | }], v2i64SExt16Imm_xform>; |
| 384 | |
| 385 | // v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned |
| 386 | // immediate constant load for v2i64 vectors. |
| 387 | def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{ |
| 388 | return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64); |
| 389 | }]>; |
| 390 | |
| 391 | // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load, |
| 392 | // works in conjunction with its transform function. |
| 393 | def v2i64Uns18Imm: PatLeaf<(build_vector), [{ |
| 394 | return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).Val != 0; |
| 395 | }], v2i64Uns18Imm_xform>; |
| 396 | |
| 397 | /// immILHUvec: Predicate test for a ILHU constant vector. |
| 398 | def immILHUvec_i64: PatLeaf<(build_vector), [{ |
| 399 | return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).Val != 0; |
| 400 | }], ILHUvec_get_imm>; |
| 401 | |
| 402 | // Catch-all for any other i32 vector constants |
| 403 | def v2i64_get_imm: SDNodeXForm<build_vector, [{ |
| 404 | return SPU::get_v2i64_imm(N, *CurDAG); |
| 405 | }]>; |
| 406 | |
| 407 | def v2i64Imm: PatLeaf<(build_vector), [{ |
| 408 | return SPU::get_v2i64_imm(N, *CurDAG).Val != 0; |
| 409 | }], v2i64_get_imm>; |
| 410 | |
| 411 | //===----------------------------------------------------------------------===// |
| 412 | // Operand Definitions. |
| 413 | |
| 414 | def s7imm: Operand<i16> { |
| 415 | let PrintMethod = "printS7ImmOperand"; |
| 416 | } |
| 417 | |
| 418 | def u7imm: Operand<i16> { |
| 419 | let PrintMethod = "printU7ImmOperand"; |
| 420 | } |
| 421 | |
Scott Michel | 504c369 | 2007-12-17 22:32:34 +0000 | [diff] [blame] | 422 | def u7imm_i8: Operand<i8> { |
| 423 | let PrintMethod = "printU7ImmOperand"; |
| 424 | } |
| 425 | |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 426 | def u7imm_i32: Operand<i32> { |
| 427 | let PrintMethod = "printU7ImmOperand"; |
| 428 | } |
| 429 | |
| 430 | // Halfword, signed 10-bit constant |
| 431 | def s10imm : Operand<i16> { |
| 432 | let PrintMethod = "printS10ImmOperand"; |
| 433 | } |
| 434 | |
| 435 | def s10imm_i32: Operand<i32> { |
| 436 | let PrintMethod = "printS10ImmOperand"; |
| 437 | } |
| 438 | |
| 439 | def s10imm_i64: Operand<i64> { |
| 440 | let PrintMethod = "printS10ImmOperand"; |
| 441 | } |
| 442 | |
| 443 | // Unsigned 10-bit integers: |
| 444 | def u10imm: Operand<i16> { |
| 445 | let PrintMethod = "printU10ImmOperand"; |
| 446 | } |
| 447 | |
Scott Michel | 504c369 | 2007-12-17 22:32:34 +0000 | [diff] [blame] | 448 | def u10imm_i8: Operand<i8> { |
| 449 | let PrintMethod = "printU10ImmOperand"; |
| 450 | } |
| 451 | |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 452 | def u10imm_i32: Operand<i32> { |
| 453 | let PrintMethod = "printU10ImmOperand"; |
| 454 | } |
| 455 | |
| 456 | def s16imm : Operand<i16> { |
| 457 | let PrintMethod = "printS16ImmOperand"; |
| 458 | } |
| 459 | |
Scott Michel | 504c369 | 2007-12-17 22:32:34 +0000 | [diff] [blame] | 460 | def s16imm_i8: Operand<i8> { |
| 461 | let PrintMethod = "printS16ImmOperand"; |
| 462 | } |
| 463 | |
Scott Michel | 564427e | 2007-12-05 01:24:05 +0000 | [diff] [blame] | 464 | def s16imm_i32: Operand<i32> { |
| 465 | let PrintMethod = "printS16ImmOperand"; |
| 466 | } |
| 467 | |
| 468 | def s16imm_i64: Operand<i64> { |
| 469 | let PrintMethod = "printS16ImmOperand"; |
| 470 | } |
| 471 | |
| 472 | def s16imm_f32: Operand<f32> { |
| 473 | let PrintMethod = "printS16ImmOperand"; |
| 474 | } |
| 475 | |
| 476 | def s16imm_f64: Operand<f64> { |
| 477 | let PrintMethod = "printS16ImmOperand"; |
| 478 | } |
| 479 | |
| 480 | def u16imm : Operand<i32> { |
| 481 | let PrintMethod = "printU16ImmOperand"; |
| 482 | } |
| 483 | |
| 484 | def f16imm : Operand<f32> { |
| 485 | let PrintMethod = "printU16ImmOperand"; |
| 486 | } |
| 487 | |
| 488 | def s18imm : Operand<i32> { |
| 489 | let PrintMethod = "printS18ImmOperand"; |
| 490 | } |
| 491 | |
| 492 | def u18imm : Operand<i32> { |
| 493 | let PrintMethod = "printU18ImmOperand"; |
| 494 | } |
| 495 | |
| 496 | def u18imm_i64 : Operand<i64> { |
| 497 | let PrintMethod = "printU18ImmOperand"; |
| 498 | } |
| 499 | |
| 500 | def f18imm : Operand<f32> { |
| 501 | let PrintMethod = "printU18ImmOperand"; |
| 502 | } |
| 503 | |
| 504 | def f18imm_f64 : Operand<f64> { |
| 505 | let PrintMethod = "printU18ImmOperand"; |
| 506 | } |
| 507 | |
| 508 | // Negated 7-bit halfword rotate immediate operands |
| 509 | def rothNeg7imm : Operand<i32> { |
| 510 | let PrintMethod = "printROTHNeg7Imm"; |
| 511 | } |
| 512 | |
| 513 | def rothNeg7imm_i16 : Operand<i16> { |
| 514 | let PrintMethod = "printROTHNeg7Imm"; |
| 515 | } |
| 516 | |
| 517 | // Negated 7-bit word rotate immediate operands |
| 518 | def rotNeg7imm : Operand<i32> { |
| 519 | let PrintMethod = "printROTNeg7Imm"; |
| 520 | } |
| 521 | |
| 522 | def rotNeg7imm_i16 : Operand<i16> { |
| 523 | let PrintMethod = "printROTNeg7Imm"; |
| 524 | } |
| 525 | |
| 526 | // Floating point immediate operands |
| 527 | def f32imm : Operand<f32>; |
| 528 | |
| 529 | def target : Operand<OtherVT> { |
| 530 | let PrintMethod = "printBranchOperand"; |
| 531 | } |
| 532 | |
| 533 | // Absolute address call target |
| 534 | def calltarget : Operand<iPTR> { |
| 535 | let PrintMethod = "printCallOperand"; |
| 536 | let MIOperandInfo = (ops u18imm:$calldest); |
| 537 | } |
| 538 | |
| 539 | // Relative call target |
| 540 | def relcalltarget : Operand<iPTR> { |
| 541 | let PrintMethod = "printPCRelativeOperand"; |
| 542 | let MIOperandInfo = (ops s16imm:$calldest); |
| 543 | } |
| 544 | |
| 545 | // Branch targets: |
| 546 | def brtarget : Operand<OtherVT> { |
| 547 | let PrintMethod = "printPCRelativeOperand"; |
| 548 | } |
| 549 | |
| 550 | // Indirect call target |
| 551 | def indcalltarget : Operand<iPTR> { |
| 552 | let PrintMethod = "printCallOperand"; |
| 553 | let MIOperandInfo = (ops ptr_rc:$calldest); |
| 554 | } |
| 555 | |
| 556 | def symbolHi: Operand<i32> { |
| 557 | let PrintMethod = "printSymbolHi"; |
| 558 | } |
| 559 | |
| 560 | def symbolLo: Operand<i32> { |
| 561 | let PrintMethod = "printSymbolLo"; |
| 562 | } |
| 563 | |
| 564 | def symbolLSA: Operand<i32> { |
| 565 | let PrintMethod = "printSymbolLSA"; |
| 566 | } |
| 567 | |
| 568 | // memory s7imm(reg) operaand |
| 569 | def memri7 : Operand<iPTR> { |
| 570 | let PrintMethod = "printMemRegImmS7"; |
| 571 | let MIOperandInfo = (ops s7imm:$imm, ptr_rc:$reg); |
| 572 | } |
| 573 | |
| 574 | // memory s10imm(reg) operand |
| 575 | def memri10 : Operand<iPTR> { |
| 576 | let PrintMethod = "printMemRegImmS10"; |
| 577 | let MIOperandInfo = (ops s10imm:$imm, ptr_rc:$reg); |
| 578 | } |
| 579 | |
| 580 | // 256K local store address |
| 581 | // N.B.: The tblgen code generator expects to have two operands, an offset |
| 582 | // and a pointer. Of these, only the immediate is actually used. |
| 583 | def addr256k : Operand<iPTR> { |
| 584 | let PrintMethod = "printAddr256K"; |
| 585 | let MIOperandInfo = (ops s16imm:$imm, ptr_rc:$reg); |
| 586 | } |
| 587 | |
| 588 | // memory s18imm(reg) operand |
| 589 | def memri18 : Operand<iPTR> { |
| 590 | let PrintMethod = "printMemRegImmS18"; |
| 591 | let MIOperandInfo = (ops s18imm:$imm, ptr_rc:$reg); |
| 592 | } |
| 593 | |
| 594 | // memory register + register operand |
| 595 | def memrr : Operand<iPTR> { |
| 596 | let PrintMethod = "printMemRegReg"; |
| 597 | let MIOperandInfo = (ops ptr_rc:$reg_a, ptr_rc:$reg_b); |
| 598 | } |
| 599 | |
| 600 | // Define SPU-specific addressing modes: These come in three basic |
| 601 | // flavors: |
| 602 | // |
| 603 | // D-form : [r+I10] (10-bit signed offset + reg) |
| 604 | // X-form : [r+r] (reg+reg) |
| 605 | // A-form : abs (256K LSA offset) |
| 606 | // D-form(2): [r+I7] (7-bit signed offset + reg) |
| 607 | |
| 608 | def dform_addr : ComplexPattern<iPTR, 2, "SelectDFormAddr", [], []>; |
| 609 | def xform_addr : ComplexPattern<iPTR, 2, "SelectXFormAddr", [], []>; |
| 610 | def aform_addr : ComplexPattern<iPTR, 2, "SelectAFormAddr", [], []>; |
| 611 | def dform2_addr : ComplexPattern<iPTR, 2, "SelectDForm2Addr", [], []>; |