Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 1 | //===- IA64RegisterInfo.td - Describe the IA64 Register File ----*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file describes the IA64 register file, defining the registers |
| 11 | // themselves, aliases between the registers, and the register classes built |
| 12 | // out of the registers. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
| 16 | //===----------------------------------------------------------------------===// |
| 17 | // Register definitions... |
| 18 | // |
| 19 | |
| 20 | class IA64Register<string n> : Register<n> { |
| 21 | let Namespace = "IA64"; |
| 22 | } |
| 23 | |
| 24 | // GR - One of 128 32-bit general registers |
| 25 | class GR<bits<7> num, string n> : IA64Register<n> { |
| 26 | field bits<7> Num = num; |
| 27 | } |
| 28 | |
| 29 | // FP - One of 128 82-bit floating-point registers |
| 30 | class FP<bits<7> num, string n> : IA64Register<n> { |
| 31 | field bits<7> Num = num; |
| 32 | } |
| 33 | |
| 34 | // PR - One of 64 1-bit predicate registers |
| 35 | class PR<bits<6> num, string n> : IA64Register<n> { |
| 36 | field bits<6> Num = num; |
| 37 | } |
| 38 | |
| 39 | /* general registers */ |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 40 | def r0 : GR< 0, "r0">, DwarfRegNum<[0]>; |
| 41 | def r1 : GR< 1, "r1">, DwarfRegNum<[1]>; |
| 42 | def r2 : GR< 2, "r2">, DwarfRegNum<[2]>; |
| 43 | def r3 : GR< 3, "r3">, DwarfRegNum<[3]>; |
| 44 | def r4 : GR< 4, "r4">, DwarfRegNum<[4]>; |
| 45 | def r5 : GR< 5, "r5">, DwarfRegNum<[5]>; |
| 46 | def r6 : GR< 6, "r6">, DwarfRegNum<[6]>; |
| 47 | def r7 : GR< 7, "r7">, DwarfRegNum<[7]>; |
| 48 | def r8 : GR< 8, "r8">, DwarfRegNum<[8]>; |
| 49 | def r9 : GR< 9, "r9">, DwarfRegNum<[9]>; |
| 50 | def r10 : GR< 10, "r10">, DwarfRegNum<[10]>; |
| 51 | def r11 : GR< 11, "r11">, DwarfRegNum<[11]>; |
| 52 | def r12 : GR< 12, "r12">, DwarfRegNum<[12]>; |
| 53 | def r13 : GR< 13, "r13">, DwarfRegNum<[13]>; |
| 54 | def r14 : GR< 14, "r14">, DwarfRegNum<[14]>; |
| 55 | def r15 : GR< 15, "r15">, DwarfRegNum<[15]>; |
| 56 | def r16 : GR< 16, "r16">, DwarfRegNum<[16]>; |
| 57 | def r17 : GR< 17, "r17">, DwarfRegNum<[17]>; |
| 58 | def r18 : GR< 18, "r18">, DwarfRegNum<[18]>; |
| 59 | def r19 : GR< 19, "r19">, DwarfRegNum<[19]>; |
| 60 | def r20 : GR< 20, "r20">, DwarfRegNum<[20]>; |
| 61 | def r21 : GR< 21, "r21">, DwarfRegNum<[21]>; |
| 62 | def r22 : GR< 22, "r22">, DwarfRegNum<[22]>; |
| 63 | def r23 : GR< 23, "r23">, DwarfRegNum<[23]>; |
| 64 | def r24 : GR< 24, "r24">, DwarfRegNum<[24]>; |
| 65 | def r25 : GR< 25, "r25">, DwarfRegNum<[25]>; |
| 66 | def r26 : GR< 26, "r26">, DwarfRegNum<[26]>; |
| 67 | def r27 : GR< 27, "r27">, DwarfRegNum<[27]>; |
| 68 | def r28 : GR< 28, "r28">, DwarfRegNum<[28]>; |
| 69 | def r29 : GR< 29, "r29">, DwarfRegNum<[29]>; |
| 70 | def r30 : GR< 30, "r30">, DwarfRegNum<[30]>; |
| 71 | def r31 : GR< 31, "r31">, DwarfRegNum<[31]>; |
| 72 | def r32 : GR< 32, "r32">, DwarfRegNum<[32]>; |
| 73 | def r33 : GR< 33, "r33">, DwarfRegNum<[33]>; |
| 74 | def r34 : GR< 34, "r34">, DwarfRegNum<[34]>; |
| 75 | def r35 : GR< 35, "r35">, DwarfRegNum<[35]>; |
| 76 | def r36 : GR< 36, "r36">, DwarfRegNum<[36]>; |
| 77 | def r37 : GR< 37, "r37">, DwarfRegNum<[37]>; |
| 78 | def r38 : GR< 38, "r38">, DwarfRegNum<[38]>; |
| 79 | def r39 : GR< 39, "r39">, DwarfRegNum<[39]>; |
| 80 | def r40 : GR< 40, "r40">, DwarfRegNum<[40]>; |
| 81 | def r41 : GR< 41, "r41">, DwarfRegNum<[41]>; |
| 82 | def r42 : GR< 42, "r42">, DwarfRegNum<[42]>; |
| 83 | def r43 : GR< 43, "r43">, DwarfRegNum<[43]>; |
| 84 | def r44 : GR< 44, "r44">, DwarfRegNum<[44]>; |
| 85 | def r45 : GR< 45, "r45">, DwarfRegNum<[45]>; |
| 86 | def r46 : GR< 46, "r46">, DwarfRegNum<[46]>; |
| 87 | def r47 : GR< 47, "r47">, DwarfRegNum<[47]>; |
| 88 | def r48 : GR< 48, "r48">, DwarfRegNum<[48]>; |
| 89 | def r49 : GR< 49, "r49">, DwarfRegNum<[49]>; |
| 90 | def r50 : GR< 50, "r50">, DwarfRegNum<[50]>; |
| 91 | def r51 : GR< 51, "r51">, DwarfRegNum<[51]>; |
| 92 | def r52 : GR< 52, "r52">, DwarfRegNum<[52]>; |
| 93 | def r53 : GR< 53, "r53">, DwarfRegNum<[53]>; |
| 94 | def r54 : GR< 54, "r54">, DwarfRegNum<[54]>; |
| 95 | def r55 : GR< 55, "r55">, DwarfRegNum<[55]>; |
| 96 | def r56 : GR< 56, "r56">, DwarfRegNum<[56]>; |
| 97 | def r57 : GR< 57, "r57">, DwarfRegNum<[57]>; |
| 98 | def r58 : GR< 58, "r58">, DwarfRegNum<[58]>; |
| 99 | def r59 : GR< 59, "r59">, DwarfRegNum<[59]>; |
| 100 | def r60 : GR< 60, "r60">, DwarfRegNum<[60]>; |
| 101 | def r61 : GR< 61, "r61">, DwarfRegNum<[61]>; |
| 102 | def r62 : GR< 62, "r62">, DwarfRegNum<[62]>; |
| 103 | def r63 : GR< 63, "r63">, DwarfRegNum<[63]>; |
| 104 | def r64 : GR< 64, "r64">, DwarfRegNum<[64]>; |
| 105 | def r65 : GR< 65, "r65">, DwarfRegNum<[65]>; |
| 106 | def r66 : GR< 66, "r66">, DwarfRegNum<[66]>; |
| 107 | def r67 : GR< 67, "r67">, DwarfRegNum<[67]>; |
| 108 | def r68 : GR< 68, "r68">, DwarfRegNum<[68]>; |
| 109 | def r69 : GR< 69, "r69">, DwarfRegNum<[69]>; |
| 110 | def r70 : GR< 70, "r70">, DwarfRegNum<[70]>; |
| 111 | def r71 : GR< 71, "r71">, DwarfRegNum<[71]>; |
| 112 | def r72 : GR< 72, "r72">, DwarfRegNum<[72]>; |
| 113 | def r73 : GR< 73, "r73">, DwarfRegNum<[73]>; |
| 114 | def r74 : GR< 74, "r74">, DwarfRegNum<[74]>; |
| 115 | def r75 : GR< 75, "r75">, DwarfRegNum<[75]>; |
| 116 | def r76 : GR< 76, "r76">, DwarfRegNum<[76]>; |
| 117 | def r77 : GR< 77, "r77">, DwarfRegNum<[77]>; |
| 118 | def r78 : GR< 78, "r78">, DwarfRegNum<[78]>; |
| 119 | def r79 : GR< 79, "r79">, DwarfRegNum<[79]>; |
| 120 | def r80 : GR< 80, "r80">, DwarfRegNum<[80]>; |
| 121 | def r81 : GR< 81, "r81">, DwarfRegNum<[81]>; |
| 122 | def r82 : GR< 82, "r82">, DwarfRegNum<[82]>; |
| 123 | def r83 : GR< 83, "r83">, DwarfRegNum<[83]>; |
| 124 | def r84 : GR< 84, "r84">, DwarfRegNum<[84]>; |
| 125 | def r85 : GR< 85, "r85">, DwarfRegNum<[85]>; |
| 126 | def r86 : GR< 86, "r86">, DwarfRegNum<[86]>; |
| 127 | def r87 : GR< 87, "r87">, DwarfRegNum<[87]>; |
| 128 | def r88 : GR< 88, "r88">, DwarfRegNum<[88]>; |
| 129 | def r89 : GR< 89, "r89">, DwarfRegNum<[89]>; |
| 130 | def r90 : GR< 90, "r90">, DwarfRegNum<[90]>; |
| 131 | def r91 : GR< 91, "r91">, DwarfRegNum<[91]>; |
| 132 | def r92 : GR< 92, "r92">, DwarfRegNum<[92]>; |
| 133 | def r93 : GR< 93, "r93">, DwarfRegNum<[93]>; |
| 134 | def r94 : GR< 94, "r94">, DwarfRegNum<[94]>; |
| 135 | def r95 : GR< 95, "r95">, DwarfRegNum<[95]>; |
| 136 | def r96 : GR< 96, "r96">, DwarfRegNum<[96]>; |
| 137 | def r97 : GR< 97, "r97">, DwarfRegNum<[97]>; |
| 138 | def r98 : GR< 98, "r98">, DwarfRegNum<[98]>; |
| 139 | def r99 : GR< 99, "r99">, DwarfRegNum<[99]>; |
| 140 | def r100 : GR< 100, "r100">, DwarfRegNum<[100]>; |
| 141 | def r101 : GR< 101, "r101">, DwarfRegNum<[101]>; |
| 142 | def r102 : GR< 102, "r102">, DwarfRegNum<[102]>; |
| 143 | def r103 : GR< 103, "r103">, DwarfRegNum<[103]>; |
| 144 | def r104 : GR< 104, "r104">, DwarfRegNum<[104]>; |
| 145 | def r105 : GR< 105, "r105">, DwarfRegNum<[105]>; |
| 146 | def r106 : GR< 106, "r106">, DwarfRegNum<[106]>; |
| 147 | def r107 : GR< 107, "r107">, DwarfRegNum<[107]>; |
| 148 | def r108 : GR< 108, "r108">, DwarfRegNum<[108]>; |
| 149 | def r109 : GR< 109, "r109">, DwarfRegNum<[109]>; |
| 150 | def r110 : GR< 110, "r110">, DwarfRegNum<[110]>; |
| 151 | def r111 : GR< 111, "r111">, DwarfRegNum<[111]>; |
| 152 | def r112 : GR< 112, "r112">, DwarfRegNum<[112]>; |
| 153 | def r113 : GR< 113, "r113">, DwarfRegNum<[113]>; |
| 154 | def r114 : GR< 114, "r114">, DwarfRegNum<[114]>; |
| 155 | def r115 : GR< 115, "r115">, DwarfRegNum<[115]>; |
| 156 | def r116 : GR< 116, "r116">, DwarfRegNum<[116]>; |
| 157 | def r117 : GR< 117, "r117">, DwarfRegNum<[117]>; |
| 158 | def r118 : GR< 118, "r118">, DwarfRegNum<[118]>; |
| 159 | def r119 : GR< 119, "r119">, DwarfRegNum<[119]>; |
| 160 | def r120 : GR< 120, "r120">, DwarfRegNum<[120]>; |
| 161 | def r121 : GR< 121, "r121">, DwarfRegNum<[121]>; |
| 162 | def r122 : GR< 122, "r122">, DwarfRegNum<[122]>; |
| 163 | def r123 : GR< 123, "r123">, DwarfRegNum<[123]>; |
| 164 | def r124 : GR< 124, "r124">, DwarfRegNum<[124]>; |
| 165 | def r125 : GR< 125, "r125">, DwarfRegNum<[125]>; |
| 166 | def r126 : GR< 126, "r126">, DwarfRegNum<[126]>; |
| 167 | def r127 : GR< 127, "r127">, DwarfRegNum<[127]>; |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 168 | |
| 169 | /* floating-point registers */ |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 170 | def F0 : FP< 0, "f0">, DwarfRegNum<[128]>; |
| 171 | def F1 : FP< 1, "f1">, DwarfRegNum<[129]>; |
| 172 | def F2 : FP< 2, "f2">, DwarfRegNum<[130]>; |
| 173 | def F3 : FP< 3, "f3">, DwarfRegNum<[131]>; |
| 174 | def F4 : FP< 4, "f4">, DwarfRegNum<[132]>; |
| 175 | def F5 : FP< 5, "f5">, DwarfRegNum<[133]>; |
| 176 | def F6 : FP< 6, "f6">, DwarfRegNum<[134]>; |
| 177 | def F7 : FP< 7, "f7">, DwarfRegNum<[135]>; |
| 178 | def F8 : FP< 8, "f8">, DwarfRegNum<[136]>; |
| 179 | def F9 : FP< 9, "f9">, DwarfRegNum<[137]>; |
| 180 | def F10 : FP< 10, "f10">, DwarfRegNum<[138]>; |
| 181 | def F11 : FP< 11, "f11">, DwarfRegNum<[139]>; |
| 182 | def F12 : FP< 12, "f12">, DwarfRegNum<[140]>; |
| 183 | def F13 : FP< 13, "f13">, DwarfRegNum<[141]>; |
| 184 | def F14 : FP< 14, "f14">, DwarfRegNum<[142]>; |
| 185 | def F15 : FP< 15, "f15">, DwarfRegNum<[143]>; |
| 186 | def F16 : FP< 16, "f16">, DwarfRegNum<[144]>; |
| 187 | def F17 : FP< 17, "f17">, DwarfRegNum<[145]>; |
| 188 | def F18 : FP< 18, "f18">, DwarfRegNum<[146]>; |
| 189 | def F19 : FP< 19, "f19">, DwarfRegNum<[147]>; |
| 190 | def F20 : FP< 20, "f20">, DwarfRegNum<[148]>; |
| 191 | def F21 : FP< 21, "f21">, DwarfRegNum<[149]>; |
| 192 | def F22 : FP< 22, "f22">, DwarfRegNum<[150]>; |
| 193 | def F23 : FP< 23, "f23">, DwarfRegNum<[151]>; |
| 194 | def F24 : FP< 24, "f24">, DwarfRegNum<[152]>; |
| 195 | def F25 : FP< 25, "f25">, DwarfRegNum<[153]>; |
| 196 | def F26 : FP< 26, "f26">, DwarfRegNum<[154]>; |
| 197 | def F27 : FP< 27, "f27">, DwarfRegNum<[155]>; |
| 198 | def F28 : FP< 28, "f28">, DwarfRegNum<[156]>; |
| 199 | def F29 : FP< 29, "f29">, DwarfRegNum<[157]>; |
| 200 | def F30 : FP< 30, "f30">, DwarfRegNum<[158]>; |
| 201 | def F31 : FP< 31, "f31">, DwarfRegNum<[159]>; |
| 202 | def F32 : FP< 32, "f32">, DwarfRegNum<[160]>; |
| 203 | def F33 : FP< 33, "f33">, DwarfRegNum<[161]>; |
| 204 | def F34 : FP< 34, "f34">, DwarfRegNum<[162]>; |
| 205 | def F35 : FP< 35, "f35">, DwarfRegNum<[163]>; |
| 206 | def F36 : FP< 36, "f36">, DwarfRegNum<[164]>; |
| 207 | def F37 : FP< 37, "f37">, DwarfRegNum<[165]>; |
| 208 | def F38 : FP< 38, "f38">, DwarfRegNum<[166]>; |
| 209 | def F39 : FP< 39, "f39">, DwarfRegNum<[167]>; |
| 210 | def F40 : FP< 40, "f40">, DwarfRegNum<[168]>; |
| 211 | def F41 : FP< 41, "f41">, DwarfRegNum<[169]>; |
| 212 | def F42 : FP< 42, "f42">, DwarfRegNum<[170]>; |
| 213 | def F43 : FP< 43, "f43">, DwarfRegNum<[171]>; |
| 214 | def F44 : FP< 44, "f44">, DwarfRegNum<[172]>; |
| 215 | def F45 : FP< 45, "f45">, DwarfRegNum<[173]>; |
| 216 | def F46 : FP< 46, "f46">, DwarfRegNum<[174]>; |
| 217 | def F47 : FP< 47, "f47">, DwarfRegNum<[175]>; |
| 218 | def F48 : FP< 48, "f48">, DwarfRegNum<[176]>; |
| 219 | def F49 : FP< 49, "f49">, DwarfRegNum<[177]>; |
| 220 | def F50 : FP< 50, "f50">, DwarfRegNum<[178]>; |
| 221 | def F51 : FP< 51, "f51">, DwarfRegNum<[179]>; |
| 222 | def F52 : FP< 52, "f52">, DwarfRegNum<[180]>; |
| 223 | def F53 : FP< 53, "f53">, DwarfRegNum<[181]>; |
| 224 | def F54 : FP< 54, "f54">, DwarfRegNum<[182]>; |
| 225 | def F55 : FP< 55, "f55">, DwarfRegNum<[183]>; |
| 226 | def F56 : FP< 56, "f56">, DwarfRegNum<[184]>; |
| 227 | def F57 : FP< 57, "f57">, DwarfRegNum<[185]>; |
| 228 | def F58 : FP< 58, "f58">, DwarfRegNum<[186]>; |
| 229 | def F59 : FP< 59, "f59">, DwarfRegNum<[187]>; |
| 230 | def F60 : FP< 60, "f60">, DwarfRegNum<[188]>; |
| 231 | def F61 : FP< 61, "f61">, DwarfRegNum<[189]>; |
| 232 | def F62 : FP< 62, "f62">, DwarfRegNum<[190]>; |
| 233 | def F63 : FP< 63, "f63">, DwarfRegNum<[191]>; |
| 234 | def F64 : FP< 64, "f64">, DwarfRegNum<[192]>; |
| 235 | def F65 : FP< 65, "f65">, DwarfRegNum<[193]>; |
| 236 | def F66 : FP< 66, "f66">, DwarfRegNum<[194]>; |
| 237 | def F67 : FP< 67, "f67">, DwarfRegNum<[195]>; |
| 238 | def F68 : FP< 68, "f68">, DwarfRegNum<[196]>; |
| 239 | def F69 : FP< 69, "f69">, DwarfRegNum<[197]>; |
| 240 | def F70 : FP< 70, "f70">, DwarfRegNum<[198]>; |
| 241 | def F71 : FP< 71, "f71">, DwarfRegNum<[199]>; |
| 242 | def F72 : FP< 72, "f72">, DwarfRegNum<[200]>; |
| 243 | def F73 : FP< 73, "f73">, DwarfRegNum<[201]>; |
| 244 | def F74 : FP< 74, "f74">, DwarfRegNum<[202]>; |
| 245 | def F75 : FP< 75, "f75">, DwarfRegNum<[203]>; |
| 246 | def F76 : FP< 76, "f76">, DwarfRegNum<[204]>; |
| 247 | def F77 : FP< 77, "f77">, DwarfRegNum<[205]>; |
| 248 | def F78 : FP< 78, "f78">, DwarfRegNum<[206]>; |
| 249 | def F79 : FP< 79, "f79">, DwarfRegNum<[207]>; |
| 250 | def F80 : FP< 80, "f80">, DwarfRegNum<[208]>; |
| 251 | def F81 : FP< 81, "f81">, DwarfRegNum<[209]>; |
| 252 | def F82 : FP< 82, "f82">, DwarfRegNum<[210]>; |
| 253 | def F83 : FP< 83, "f83">, DwarfRegNum<[211]>; |
| 254 | def F84 : FP< 84, "f84">, DwarfRegNum<[212]>; |
| 255 | def F85 : FP< 85, "f85">, DwarfRegNum<[213]>; |
| 256 | def F86 : FP< 86, "f86">, DwarfRegNum<[214]>; |
| 257 | def F87 : FP< 87, "f87">, DwarfRegNum<[215]>; |
| 258 | def F88 : FP< 88, "f88">, DwarfRegNum<[216]>; |
| 259 | def F89 : FP< 89, "f89">, DwarfRegNum<[217]>; |
| 260 | def F90 : FP< 90, "f90">, DwarfRegNum<[218]>; |
| 261 | def F91 : FP< 91, "f91">, DwarfRegNum<[219]>; |
| 262 | def F92 : FP< 92, "f92">, DwarfRegNum<[220]>; |
| 263 | def F93 : FP< 93, "f93">, DwarfRegNum<[221]>; |
| 264 | def F94 : FP< 94, "f94">, DwarfRegNum<[222]>; |
| 265 | def F95 : FP< 95, "f95">, DwarfRegNum<[223]>; |
| 266 | def F96 : FP< 96, "f96">, DwarfRegNum<[224]>; |
| 267 | def F97 : FP< 97, "f97">, DwarfRegNum<[225]>; |
| 268 | def F98 : FP< 98, "f98">, DwarfRegNum<[226]>; |
| 269 | def F99 : FP< 99, "f99">, DwarfRegNum<[227]>; |
| 270 | def F100 : FP< 100, "f100">, DwarfRegNum<[228]>; |
| 271 | def F101 : FP< 101, "f101">, DwarfRegNum<[229]>; |
| 272 | def F102 : FP< 102, "f102">, DwarfRegNum<[230]>; |
| 273 | def F103 : FP< 103, "f103">, DwarfRegNum<[231]>; |
| 274 | def F104 : FP< 104, "f104">, DwarfRegNum<[232]>; |
| 275 | def F105 : FP< 105, "f105">, DwarfRegNum<[233]>; |
| 276 | def F106 : FP< 106, "f106">, DwarfRegNum<[234]>; |
| 277 | def F107 : FP< 107, "f107">, DwarfRegNum<[235]>; |
| 278 | def F108 : FP< 108, "f108">, DwarfRegNum<[236]>; |
| 279 | def F109 : FP< 109, "f109">, DwarfRegNum<[237]>; |
| 280 | def F110 : FP< 110, "f110">, DwarfRegNum<[238]>; |
| 281 | def F111 : FP< 111, "f111">, DwarfRegNum<[239]>; |
| 282 | def F112 : FP< 112, "f112">, DwarfRegNum<[240]>; |
| 283 | def F113 : FP< 113, "f113">, DwarfRegNum<[241]>; |
| 284 | def F114 : FP< 114, "f114">, DwarfRegNum<[242]>; |
| 285 | def F115 : FP< 115, "f115">, DwarfRegNum<[243]>; |
| 286 | def F116 : FP< 116, "f116">, DwarfRegNum<[244]>; |
| 287 | def F117 : FP< 117, "f117">, DwarfRegNum<[245]>; |
| 288 | def F118 : FP< 118, "f118">, DwarfRegNum<[246]>; |
| 289 | def F119 : FP< 119, "f119">, DwarfRegNum<[247]>; |
| 290 | def F120 : FP< 120, "f120">, DwarfRegNum<[248]>; |
| 291 | def F121 : FP< 121, "f121">, DwarfRegNum<[249]>; |
| 292 | def F122 : FP< 122, "f122">, DwarfRegNum<[250]>; |
| 293 | def F123 : FP< 123, "f123">, DwarfRegNum<[251]>; |
| 294 | def F124 : FP< 124, "f124">, DwarfRegNum<[252]>; |
| 295 | def F125 : FP< 125, "f125">, DwarfRegNum<[253]>; |
| 296 | def F126 : FP< 126, "f126">, DwarfRegNum<[254]>; |
| 297 | def F127 : FP< 127, "f127">, DwarfRegNum<[255]>; |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 298 | |
| 299 | /* predicate registers */ |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 300 | def p0 : PR< 0, "p0">, DwarfRegNum<[256]>; |
| 301 | def p1 : PR< 1, "p1">, DwarfRegNum<[257]>; |
| 302 | def p2 : PR< 2, "p2">, DwarfRegNum<[258]>; |
| 303 | def p3 : PR< 3, "p3">, DwarfRegNum<[259]>; |
| 304 | def p4 : PR< 4, "p4">, DwarfRegNum<[260]>; |
| 305 | def p5 : PR< 5, "p5">, DwarfRegNum<[261]>; |
| 306 | def p6 : PR< 6, "p6">, DwarfRegNum<[262]>; |
| 307 | def p7 : PR< 7, "p7">, DwarfRegNum<[263]>; |
| 308 | def p8 : PR< 8, "p8">, DwarfRegNum<[264]>; |
| 309 | def p9 : PR< 9, "p9">, DwarfRegNum<[265]>; |
| 310 | def p10 : PR< 10, "p10">, DwarfRegNum<[266]>; |
| 311 | def p11 : PR< 11, "p11">, DwarfRegNum<[267]>; |
| 312 | def p12 : PR< 12, "p12">, DwarfRegNum<[268]>; |
| 313 | def p13 : PR< 13, "p13">, DwarfRegNum<[269]>; |
| 314 | def p14 : PR< 14, "p14">, DwarfRegNum<[270]>; |
| 315 | def p15 : PR< 15, "p15">, DwarfRegNum<[271]>; |
| 316 | def p16 : PR< 16, "p16">, DwarfRegNum<[272]>; |
| 317 | def p17 : PR< 17, "p17">, DwarfRegNum<[273]>; |
| 318 | def p18 : PR< 18, "p18">, DwarfRegNum<[274]>; |
| 319 | def p19 : PR< 19, "p19">, DwarfRegNum<[275]>; |
| 320 | def p20 : PR< 20, "p20">, DwarfRegNum<[276]>; |
| 321 | def p21 : PR< 21, "p21">, DwarfRegNum<[277]>; |
| 322 | def p22 : PR< 22, "p22">, DwarfRegNum<[278]>; |
| 323 | def p23 : PR< 23, "p23">, DwarfRegNum<[279]>; |
| 324 | def p24 : PR< 24, "p24">, DwarfRegNum<[280]>; |
| 325 | def p25 : PR< 25, "p25">, DwarfRegNum<[281]>; |
| 326 | def p26 : PR< 26, "p26">, DwarfRegNum<[282]>; |
| 327 | def p27 : PR< 27, "p27">, DwarfRegNum<[283]>; |
| 328 | def p28 : PR< 28, "p28">, DwarfRegNum<[284]>; |
| 329 | def p29 : PR< 29, "p29">, DwarfRegNum<[285]>; |
| 330 | def p30 : PR< 30, "p30">, DwarfRegNum<[286]>; |
| 331 | def p31 : PR< 31, "p31">, DwarfRegNum<[287]>; |
| 332 | def p32 : PR< 32, "p32">, DwarfRegNum<[288]>; |
| 333 | def p33 : PR< 33, "p33">, DwarfRegNum<[289]>; |
| 334 | def p34 : PR< 34, "p34">, DwarfRegNum<[290]>; |
| 335 | def p35 : PR< 35, "p35">, DwarfRegNum<[291]>; |
| 336 | def p36 : PR< 36, "p36">, DwarfRegNum<[292]>; |
| 337 | def p37 : PR< 37, "p37">, DwarfRegNum<[293]>; |
| 338 | def p38 : PR< 38, "p38">, DwarfRegNum<[294]>; |
| 339 | def p39 : PR< 39, "p39">, DwarfRegNum<[295]>; |
| 340 | def p40 : PR< 40, "p40">, DwarfRegNum<[296]>; |
| 341 | def p41 : PR< 41, "p41">, DwarfRegNum<[297]>; |
| 342 | def p42 : PR< 42, "p42">, DwarfRegNum<[298]>; |
| 343 | def p43 : PR< 43, "p43">, DwarfRegNum<[299]>; |
| 344 | def p44 : PR< 44, "p44">, DwarfRegNum<[300]>; |
| 345 | def p45 : PR< 45, "p45">, DwarfRegNum<[301]>; |
| 346 | def p46 : PR< 46, "p46">, DwarfRegNum<[302]>; |
| 347 | def p47 : PR< 47, "p47">, DwarfRegNum<[303]>; |
| 348 | def p48 : PR< 48, "p48">, DwarfRegNum<[304]>; |
| 349 | def p49 : PR< 49, "p49">, DwarfRegNum<[305]>; |
| 350 | def p50 : PR< 50, "p50">, DwarfRegNum<[306]>; |
| 351 | def p51 : PR< 51, "p51">, DwarfRegNum<[307]>; |
| 352 | def p52 : PR< 52, "p52">, DwarfRegNum<[308]>; |
| 353 | def p53 : PR< 53, "p53">, DwarfRegNum<[309]>; |
| 354 | def p54 : PR< 54, "p54">, DwarfRegNum<[310]>; |
| 355 | def p55 : PR< 55, "p55">, DwarfRegNum<[311]>; |
| 356 | def p56 : PR< 56, "p56">, DwarfRegNum<[312]>; |
| 357 | def p57 : PR< 57, "p57">, DwarfRegNum<[313]>; |
| 358 | def p58 : PR< 58, "p58">, DwarfRegNum<[314]>; |
| 359 | def p59 : PR< 59, "p59">, DwarfRegNum<[315]>; |
| 360 | def p60 : PR< 60, "p60">, DwarfRegNum<[316]>; |
| 361 | def p61 : PR< 61, "p61">, DwarfRegNum<[317]>; |
| 362 | def p62 : PR< 62, "p62">, DwarfRegNum<[318]>; |
| 363 | def p63 : PR< 63, "p63">, DwarfRegNum<[319]>; |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 364 | |
| 365 | // XXX : this is temporary, we'll eventually have the output registers |
| 366 | // in the general purpose register class too? |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 367 | def out0 : GR<0, "out0">, DwarfRegNum<[120]>; |
| 368 | def out1 : GR<1, "out1">, DwarfRegNum<[121]>; |
| 369 | def out2 : GR<2, "out2">, DwarfRegNum<[122]>; |
| 370 | def out3 : GR<3, "out3">, DwarfRegNum<[123]>; |
| 371 | def out4 : GR<4, "out4">, DwarfRegNum<[124]>; |
| 372 | def out5 : GR<5, "out5">, DwarfRegNum<[125]>; |
| 373 | def out6 : GR<6, "out6">, DwarfRegNum<[126]>; |
| 374 | def out7 : GR<7, "out7">, DwarfRegNum<[127]>; |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 375 | |
| 376 | // application (special) registers: |
| 377 | |
Duraid Madina | f2db9b8 | 2005-10-28 17:46:35 +0000 | [diff] [blame] | 378 | // "previous function state" application register |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 379 | def AR_PFS : GR<0, "ar.pfs">, DwarfRegNum<[331]>; |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 380 | |
| 381 | // "return pointer" (this is really branch register b0) |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 382 | def rp : GR<0, "rp">, DwarfRegNum<[-1]>; |
Jim Laskey | 47622e3 | 2006-03-24 21:15:58 +0000 | [diff] [blame] | 383 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 384 | // branch reg 6 |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 385 | def B6 : GR<0, "b6">, DwarfRegNum<[326]>; |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 386 | |
| 387 | //===----------------------------------------------------------------------===// |
| 388 | // Register Class Definitions... now that we have all of the pieces, define the |
| 389 | // top-level register classes. The order specified in the register list is |
| 390 | // implicitly defined to be the register allocation order. |
| 391 | // |
| 392 | |
| 393 | // these are the scratch (+stacked) general registers |
Duraid Madina | b9bcd18 | 2006-01-23 06:08:46 +0000 | [diff] [blame] | 394 | // FIXME/XXX we also reserve a frame pointer (r5) |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 395 | // FIXME/XXX we also reserve r2 for spilling/filling predicates |
| 396 | // in IA64RegisterInfo.cpp |
| 397 | // FIXME/XXX we also reserve r22 for calculating addresses |
| 398 | // in IA64RegisterInfo.cpp |
| 399 | |
Nate Begeman | 6510b22 | 2005-12-01 04:51:06 +0000 | [diff] [blame] | 400 | def GR : RegisterClass<"IA64", [i64], 64, |
Duraid Madina | e8fd25f | 2005-04-12 18:42:59 +0000 | [diff] [blame] | 401 | [ |
| 402 | |
Duraid Madina | a0a11d2 | 2005-12-22 03:56:03 +0000 | [diff] [blame] | 403 | //FIXME!: for both readability and performance, we don't want the out |
| 404 | // registers to be the first ones allocated |
Duraid Madina | e8fd25f | 2005-04-12 18:42:59 +0000 | [diff] [blame] | 405 | |
| 406 | out7, out6, out5, out4, out3, out2, out1, out0, |
Duraid Madina | b9bcd18 | 2006-01-23 06:08:46 +0000 | [diff] [blame] | 407 | r3, r8, r9, r10, r11, r14, r15, |
Duraid Madina | 4ee131f | 2005-04-06 06:17:54 +0000 | [diff] [blame] | 408 | r16, r17, r18, r19, r20, r21, r23, |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 409 | r24, r25, r26, r27, r28, r29, r30, r31, |
| 410 | r32, r33, r34, r35, r36, r37, r38, r39, |
| 411 | r40, r41, r42, r43, r44, r45, r46, r47, |
| 412 | r48, r49, r50, r51, r52, r53, r54, r55, |
| 413 | r56, r57, r58, r59, r60, r61, r62, r63, |
| 414 | r64, r65, r66, r67, r68, r69, r70, r71, |
| 415 | r72, r73, r74, r75, r76, r77, r78, r79, |
| 416 | r80, r81, r82, r83, r84, r85, r86, r87, |
| 417 | r88, r89, r90, r91, r92, r93, r94, r95, |
| 418 | r96, r97, r98, r99, r100, r101, r102, r103, |
| 419 | r104, r105, r106, r107, r108, r109, r110, r111, |
| 420 | r112, r113, r114, r115, r116, r117, r118, r119, |
Duraid Madina | 4ee131f | 2005-04-06 06:17:54 +0000 | [diff] [blame] | 421 | r120, r121, r122, r123, r124, r125, r126, r127, |
Duraid Madina | b9bcd18 | 2006-01-23 06:08:46 +0000 | [diff] [blame] | 422 | r0, r1, r2, r5, r12, r13, r22, rp]> // the last 16 are special (look down) |
Duraid Madina | 4ee131f | 2005-04-06 06:17:54 +0000 | [diff] [blame] | 423 | { |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 424 | let MethodProtos = [{ |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 425 | iterator allocation_order_begin(const MachineFunction &MF) const; |
| 426 | iterator allocation_order_end(const MachineFunction &MF) const; |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 427 | }]; |
| 428 | let MethodBodies = [{ |
| 429 | GRClass::iterator |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 430 | GRClass::allocation_order_begin(const MachineFunction &MF) const { |
Duraid Madina | f2db9b8 | 2005-10-28 17:46:35 +0000 | [diff] [blame] | 431 | // hide the 8 out? registers appropriately: |
Duraid Madina | e8fd25f | 2005-04-12 18:42:59 +0000 | [diff] [blame] | 432 | return begin()+(8-(MF.getInfo<IA64FunctionInfo>()->outRegsUsed)); |
| 433 | } |
| 434 | |
Chris Lattner | ecbce61 | 2005-08-19 19:13:20 +0000 | [diff] [blame] | 435 | GRClass::iterator |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 436 | GRClass::allocation_order_end(const MachineFunction &MF) const { |
Duraid Madina | b9bcd18 | 2006-01-23 06:08:46 +0000 | [diff] [blame] | 437 | int numReservedRegs=8; // the 8 special registers r0,r1,r2,r5,r12,r13 etc |
Duraid Madina | e8fd25f | 2005-04-12 18:42:59 +0000 | [diff] [blame] | 438 | |
Duraid Madina | e00e5de | 2005-04-09 11:53:00 +0000 | [diff] [blame] | 439 | // we also can't allocate registers for use as locals if they're |
| 440 | // already required as 'out' registers |
| 441 | numReservedRegs+=MF.getInfo<IA64FunctionInfo>()->outRegsUsed; |
| 442 | |
| 443 | return end()-numReservedRegs; // hide registers appropriately |
Duraid Madina | 4ee131f | 2005-04-06 06:17:54 +0000 | [diff] [blame] | 444 | } |
| 445 | }]; |
| 446 | } |
| 447 | |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 448 | |
| 449 | // these are the scratch (+stacked) FP registers |
Duraid Madina | 362071d | 2006-01-17 02:04:52 +0000 | [diff] [blame] | 450 | |
Duraid Madina | b063604 | 2006-01-26 09:45:03 +0000 | [diff] [blame] | 451 | def FP : RegisterClass<"IA64", [f64], 64, |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 452 | [F6, F7, |
| 453 | F8, F9, F10, F11, F12, F13, F14, F15, |
| 454 | F32, F33, F34, F35, F36, F37, F38, F39, |
| 455 | F40, F41, F42, F43, F44, F45, F46, F47, |
| 456 | F48, F49, F50, F51, F52, F53, F54, F55, |
| 457 | F56, F57, F58, F59, F60, F61, F62, F63, |
| 458 | F64, F65, F66, F67, F68, F69, F70, F71, |
| 459 | F72, F73, F74, F75, F76, F77, F78, F79, |
| 460 | F80, F81, F82, F83, F84, F85, F86, F87, |
| 461 | F88, F89, F90, F91, F92, F93, F94, F95, |
| 462 | F96, F97, F98, F99, F100, F101, F102, F103, |
| 463 | F104, F105, F106, F107, F108, F109, F110, F111, |
| 464 | F112, F113, F114, F115, F116, F117, F118, F119, |
Duraid Madina | a2df2ae | 2005-11-02 07:30:39 +0000 | [diff] [blame] | 465 | F120, F121, F122, F123, F124, F125, F126, F127, |
| 466 | F0, F1]> // these last two are hidden |
| 467 | { |
Duraid Madina | b063604 | 2006-01-26 09:45:03 +0000 | [diff] [blame] | 468 | // the 128s here are to make stf.spill/ldf.fill happy, |
| 469 | // when storing full (82-bit) FP regs to stack slots |
| 470 | // we need to 16-byte align |
| 471 | let Size=128; |
| 472 | let Alignment=128; |
| 473 | |
Duraid Madina | a2df2ae | 2005-11-02 07:30:39 +0000 | [diff] [blame] | 474 | let MethodProtos = [{ |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 475 | iterator allocation_order_begin(const MachineFunction &MF) const; |
| 476 | iterator allocation_order_end(const MachineFunction &MF) const; |
Duraid Madina | a2df2ae | 2005-11-02 07:30:39 +0000 | [diff] [blame] | 477 | }]; |
| 478 | let MethodBodies = [{ |
| 479 | FPClass::iterator |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 480 | FPClass::allocation_order_begin(const MachineFunction &MF) const { |
Duraid Madina | a2df2ae | 2005-11-02 07:30:39 +0000 | [diff] [blame] | 481 | return begin(); // we don't hide any FP regs from the start |
| 482 | } |
| 483 | |
| 484 | FPClass::iterator |
Chris Lattner | 5ea64fd | 2006-08-17 22:00:08 +0000 | [diff] [blame] | 485 | FPClass::allocation_order_end(const MachineFunction &MF) const { |
Duraid Madina | a2df2ae | 2005-11-02 07:30:39 +0000 | [diff] [blame] | 486 | return end()-2; // we hide regs F0, F1 from the end |
| 487 | } |
| 488 | }]; |
| 489 | } |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 490 | |
| 491 | // these are the predicate registers, p0 (1/TRUE) is not here |
Nate Begeman | 6510b22 | 2005-12-01 04:51:06 +0000 | [diff] [blame] | 492 | def PR : RegisterClass<"IA64", [i1], 64, |
Duraid Madina | 9b9d45f | 2005-03-17 18:17:03 +0000 | [diff] [blame] | 493 | |
| 494 | // for now, let's be wimps and only have the scratch predicate regs |
| 495 | [p6, p7, p8, p9, p10, p11, p12, p13, p14, p15]> { |
| 496 | let Size = 64; |
| 497 | } |
| 498 | |
| 499 | /* |
| 500 | [p1, p2, p3, p4, p5, p6, p7, |
| 501 | p8, p9, p10, p11, p12, p13, p14, p15, |
| 502 | p16, p17, p18, p19, p20, p21, p22, p23, |
| 503 | p24, p25, p26, p27, p28, p29, p30, p31, |
| 504 | p32, p33, p34, p35, p36, p37, p38, p39, |
| 505 | p40, p41, p42, p43, p44, p45, p46, p47, |
| 506 | p48, p49, p50, p51, p52, p53, p54, p55, |
| 507 | p56, p57, p58, p59, p60, p61, p62, p63]>; |
| 508 | */ |