Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 1 | //===- MipsInstrInfo.td - Mips Register defs --------------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | //===----------------------------------------------------------------------===// |
| 11 | // Instruction format superclass |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | include "MipsInstrFormats.td" |
| 15 | |
| 16 | //===----------------------------------------------------------------------===// |
| 17 | // Mips profiles and nodes |
| 18 | //===----------------------------------------------------------------------===// |
| 19 | |
| 20 | // Call |
| 21 | def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; |
| 22 | def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain, |
| 23 | SDNPOutFlag]>; |
| 24 | |
Bruno Cardoso Lopes | c7db561 | 2007-11-05 03:02:32 +0000 | [diff] [blame] | 25 | // Hi and Lo nodes are used to handle global addresses. Used on |
| 26 | // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol |
| 27 | // static model. (nothing to do with Mips Registers Hi and Lo) |
| 28 | def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>; |
| 29 | def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; |
Bruno Cardoso Lopes | e78080c | 2007-10-09 02:55:31 +0000 | [diff] [blame] | 30 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 31 | // Return |
| 32 | def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| 33 | def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain, |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 34 | SDNPOptInFlag]>; |
| 35 | |
| 36 | // These are target-independent nodes, but have target-specific formats. |
Bill Wendling | c69107c | 2007-11-13 09:19:02 +0000 | [diff] [blame] | 37 | def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; |
| 38 | def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, |
| 39 | SDTCisVT<1, i32>]>; |
Bill Wendling | 0f8d9c0 | 2007-11-13 00:44:25 +0000 | [diff] [blame] | 40 | |
Bill Wendling | c69107c | 2007-11-13 09:19:02 +0000 | [diff] [blame] | 41 | def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 42 | [SDNPHasChain, SDNPOutFlag]>; |
Bill Wendling | c69107c | 2007-11-13 09:19:02 +0000 | [diff] [blame] | 43 | def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, |
Bill Wendling | 0f8d9c0 | 2007-11-13 00:44:25 +0000 | [diff] [blame] | 44 | [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 45 | |
Bruno Cardoso Lopes | e78080c | 2007-10-09 02:55:31 +0000 | [diff] [blame] | 46 | //===----------------------------------------------------------------------===// |
| 47 | // Mips Instruction Predicate Definitions. |
| 48 | //===----------------------------------------------------------------------===// |
| 49 | def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; |
| 50 | |
| 51 | //===----------------------------------------------------------------------===// |
| 52 | // Mips Operand, Complex Patterns and Transformations Definitions. |
| 53 | //===----------------------------------------------------------------------===// |
| 54 | |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 55 | // Instruction operand types |
| 56 | def brtarget : Operand<OtherVT>; |
| 57 | def calltarget : Operand<i32>; |
| 58 | def uimm16 : Operand<i32>; |
| 59 | def simm16 : Operand<i32>; |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 60 | def shamt : Operand<i32>; |
Bruno Cardoso Lopes | e78080c | 2007-10-09 02:55:31 +0000 | [diff] [blame] | 61 | def addrlabel : Operand<i32>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 62 | |
| 63 | // Address operand |
| 64 | def mem : Operand<i32> { |
| 65 | let PrintMethod = "printMemOperand"; |
| 66 | let MIOperandInfo = (ops simm16, CPURegs); |
| 67 | } |
| 68 | |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 69 | // Transformation Function - get the lower 16 bits. |
| 70 | def LO16 : SDNodeXForm<imm, [{ |
| 71 | return getI32Imm((unsigned)N->getValue() & 0xFFFF); |
| 72 | }]>; |
| 73 | |
| 74 | // Transformation Function - get the higher 16 bits. |
| 75 | def HI16 : SDNodeXForm<imm, [{ |
| 76 | return getI32Imm((unsigned)N->getValue() >> 16); |
| 77 | }]>; |
| 78 | |
| 79 | // Node immediate fits as 16-bit sign extended on target immediate. |
| 80 | // e.g. addi, andi |
| 81 | def immSExt16 : PatLeaf<(imm), [{ |
| 82 | if (N->getValueType(0) == MVT::i32) |
| 83 | return (int32_t)N->getValue() == (short)N->getValue(); |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 84 | else |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 85 | return (int64_t)N->getValue() == (short)N->getValue(); |
| 86 | }]>; |
| 87 | |
| 88 | // Node immediate fits as 16-bit zero extended on target immediate. |
| 89 | // The LO16 param means that only the lower 16 bits of the node |
| 90 | // immediate are caught. |
| 91 | // e.g. addiu, sltiu |
| 92 | def immZExt16 : PatLeaf<(imm), [{ |
Bruno Cardoso Lopes | 332a3d2 | 2007-07-11 22:47:02 +0000 | [diff] [blame] | 93 | if (N->getValueType(0) == MVT::i32) |
| 94 | return (uint32_t)N->getValue() == (unsigned short)N->getValue(); |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 95 | else |
Bruno Cardoso Lopes | 332a3d2 | 2007-07-11 22:47:02 +0000 | [diff] [blame] | 96 | return (uint64_t)N->getValue() == (unsigned short)N->getValue(); |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 97 | }], LO16>; |
| 98 | |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 99 | // Node immediate fits as 32-bit zero extended on target immediate. |
| 100 | //def immZExt32 : PatLeaf<(imm), [{ |
| 101 | // return (uint64_t)N->getValue() == (uint32_t)N->getValue(); |
| 102 | //}], LO16>; |
| 103 | |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 104 | // shamt field must fit in 5 bits. |
| 105 | def immZExt5 : PatLeaf<(imm), [{ |
| 106 | return N->getValue() == ((N->getValue()) & 0x1f) ; |
| 107 | }]>; |
| 108 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 109 | // Mips Address Mode! SDNode frameindex could possibily be a match |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 110 | // since load and store instructions from stack used it. |
| 111 | def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>; |
| 112 | |
| 113 | //===----------------------------------------------------------------------===// |
| 114 | // Instructions specific format |
| 115 | //===----------------------------------------------------------------------===// |
| 116 | |
| 117 | // Arithmetic 3 register operands |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 118 | let isCommutable = 1 in |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 119 | class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode, |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 120 | InstrItinClass itin>: |
| 121 | FR< op, |
| 122 | func, |
| 123 | (outs CPURegs:$dst), |
| 124 | (ins CPURegs:$b, CPURegs:$c), |
| 125 | !strconcat(instr_asm, " $dst, $b, $c"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 126 | [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 127 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 128 | let isCommutable = 1 in |
| 129 | class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>: |
| 130 | FR< op, |
| 131 | func, |
| 132 | (outs CPURegs:$dst), |
| 133 | (ins CPURegs:$b, CPURegs:$c), |
| 134 | !strconcat(instr_asm, " $dst, $b, $c"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 135 | [], IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 136 | |
| 137 | // Arithmetic 2 register operands |
| 138 | let isCommutable = 1 in |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 139 | class ArithI<bits<6> op, string instr_asm, SDNode OpNode, |
| 140 | Operand Od, PatLeaf imm_type> : |
| 141 | FI< op, |
| 142 | (outs CPURegs:$dst), |
| 143 | (ins CPURegs:$b, Od:$c), |
| 144 | !strconcat(instr_asm, " $dst, $b, $c"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 145 | [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 146 | |
| 147 | // Arithmetic Multiply ADD/SUB |
| 148 | let rd=0 in |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 149 | class MArithR<bits<6> func, string instr_asm> : |
| 150 | FR< 0x1c, |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 151 | func, |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 152 | (outs CPURegs:$rs), |
| 153 | (ins CPURegs:$rt), |
| 154 | !strconcat(instr_asm, " $rs, $rt"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 155 | [], IIImul>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 156 | |
| 157 | // Logical |
| 158 | class LogicR<bits<6> func, string instr_asm, SDNode OpNode>: |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 159 | FR< 0x00, |
| 160 | func, |
| 161 | (outs CPURegs:$dst), |
| 162 | (ins CPURegs:$b, CPURegs:$c), |
| 163 | !strconcat(instr_asm, " $dst, $b, $c"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 164 | [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 165 | |
| 166 | class LogicI<bits<6> op, string instr_asm, SDNode OpNode>: |
| 167 | FI< op, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 168 | (outs CPURegs:$dst), |
| 169 | (ins CPURegs:$b, uimm16:$c), |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 170 | !strconcat(instr_asm, " $dst, $b, $c"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 171 | [(set CPURegs:$dst, (OpNode CPURegs:$b, immSExt16:$c))], IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 172 | |
| 173 | class LogicNOR<bits<6> op, bits<6> func, string instr_asm>: |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 174 | FR< op, |
| 175 | func, |
| 176 | (outs CPURegs:$dst), |
| 177 | (ins CPURegs:$b, CPURegs:$c), |
| 178 | !strconcat(instr_asm, " $dst, $b, $c"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 179 | [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 180 | |
| 181 | // Shifts |
| 182 | let rt = 0 in |
| 183 | class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>: |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 184 | FR< 0x00, |
| 185 | func, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 186 | (outs CPURegs:$dst), |
| 187 | (ins CPURegs:$b, shamt:$c), |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 188 | !strconcat(instr_asm, " $dst, $b, $c"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 189 | [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 190 | |
| 191 | class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>: |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 192 | FR< 0x00, |
| 193 | func, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 194 | (outs CPURegs:$dst), |
| 195 | (ins CPURegs:$b, CPURegs:$c), |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 196 | !strconcat(instr_asm, " $dst, $b, $c"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 197 | [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 198 | |
| 199 | // Load Upper Imediate |
| 200 | class LoadUpper<bits<6> op, string instr_asm>: |
| 201 | FI< op, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 202 | (outs CPURegs:$dst), |
| 203 | (ins uimm16:$imm), |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 204 | !strconcat(instr_asm, " $dst, $imm"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 205 | [], IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 206 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 207 | // Memory Load/Store |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 208 | let isLoad = 1, hasDelaySlot = 1 in |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 209 | class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>: |
| 210 | FI< op, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 211 | (outs CPURegs:$dst), |
| 212 | (ins mem:$addr), |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 213 | !strconcat(instr_asm, " $dst, $addr"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 214 | [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 215 | |
| 216 | let isStore = 1 in |
| 217 | class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>: |
| 218 | FI< op, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 219 | (outs), |
| 220 | (ins CPURegs:$dst, mem:$addr), |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 221 | !strconcat(instr_asm, " $dst, $addr"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 222 | [(OpNode CPURegs:$dst, addr:$addr)], IIStore>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 223 | |
| 224 | // Conditional Branch |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 225 | let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in { |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 226 | class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>: |
| 227 | FI< op, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 228 | (outs), |
| 229 | (ins CPURegs:$a, CPURegs:$b, brtarget:$offset), |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 230 | !strconcat(instr_asm, " $a, $b, $offset"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 231 | [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)], |
| 232 | IIBranch>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 233 | |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 234 | |
| 235 | class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>: |
| 236 | FI< op, |
| 237 | (outs), |
| 238 | (ins CPURegs:$src, brtarget:$offset), |
| 239 | !strconcat(instr_asm, " $src, $offset"), |
| 240 | [(brcond (cond_op CPURegs:$src, 0), bb:$offset)], |
| 241 | IIBranch>; |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 242 | } |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 243 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 244 | // SetCC |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 245 | class SetCC_R<bits<6> op, bits<6> func, string instr_asm, |
| 246 | PatFrag cond_op>: |
| 247 | FR< op, |
| 248 | func, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 249 | (outs CPURegs:$dst), |
| 250 | (ins CPURegs:$b, CPURegs:$c), |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 251 | !strconcat(instr_asm, " $dst, $b, $c"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 252 | [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))], |
| 253 | IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 254 | |
| 255 | class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, |
| 256 | Operand Od, PatLeaf imm_type>: |
| 257 | FI< op, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 258 | (outs CPURegs:$dst), |
| 259 | (ins CPURegs:$b, Od:$c), |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 260 | !strconcat(instr_asm, " $dst, $b, $c"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 261 | [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))], |
| 262 | IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 263 | |
| 264 | // Unconditional branch |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 265 | let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 266 | class JumpFJ<bits<6> op, string instr_asm>: |
| 267 | FJ< op, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 268 | (outs), |
| 269 | (ins brtarget:$target), |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 270 | !strconcat(instr_asm, " $target"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 271 | [(br bb:$target)], IIBranch>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 272 | |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 273 | let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 274 | class JumpFR<bits<6> op, bits<6> func, string instr_asm>: |
| 275 | FR< op, |
| 276 | func, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 277 | (outs), |
| 278 | (ins CPURegs:$target), |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 279 | !strconcat(instr_asm, " $target"), |
Bruno Cardoso Lopes | 753a987 | 2007-11-12 19:49:57 +0000 | [diff] [blame] | 280 | [(brind CPURegs:$target)], IIBranch>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 281 | |
| 282 | // Jump and Link (Call) |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 283 | let isCall=1, hasDelaySlot=1, |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 284 | // All calls clobber the non-callee saved registers... |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 285 | Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, |
Bruno Cardoso Lopes | 753a987 | 2007-11-12 19:49:57 +0000 | [diff] [blame] | 286 | T3, T4, T5, T6, T7, T8, T9, K0, K1], Uses = [GP] in { |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 287 | class JumpLink<bits<6> op, string instr_asm>: |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 288 | FJ< op, |
| 289 | (outs), |
| 290 | (ins calltarget:$target), |
| 291 | !strconcat(instr_asm, " $target"), |
| 292 | [(MipsJmpLink imm:$target)], IIBranch>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 293 | |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 294 | let rd=31 in |
| 295 | class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>: |
| 296 | FR< op, |
| 297 | func, |
| 298 | (outs), |
| 299 | (ins CPURegs:$rs), |
| 300 | !strconcat(instr_asm, " $rs"), |
| 301 | [(MipsJmpLink CPURegs:$rs)], IIBranch>; |
| 302 | |
| 303 | class BranchLink<string instr_asm>: |
| 304 | FI< 0x1, |
| 305 | (outs), |
| 306 | (ins CPURegs:$rs, brtarget:$target), |
| 307 | !strconcat(instr_asm, " $rs, $target"), |
| 308 | [], IIBranch>; |
| 309 | } |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 310 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 311 | // Mul, Div |
| 312 | class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>: |
| 313 | FR< 0x00, |
| 314 | func, |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 315 | (outs), |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 316 | (ins CPURegs:$a, CPURegs:$b), |
| 317 | !strconcat(instr_asm, " $a, $b"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 318 | [], itin>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 319 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 320 | // Move from Hi/Lo |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 321 | class MoveFromTo<bits<6> func, string instr_asm>: |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 322 | FR< 0x00, |
| 323 | func, |
| 324 | (outs CPURegs:$dst), |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 325 | (ins), |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 326 | !strconcat(instr_asm, " $dst"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 327 | [], IIHiLo>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 328 | |
| 329 | // Count Leading Ones/Zeros in Word |
| 330 | class CountLeading<bits<6> func, string instr_asm>: |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 331 | FR< 0x1c, |
| 332 | func, |
| 333 | (outs CPURegs:$dst), |
| 334 | (ins CPURegs:$src), |
| 335 | !strconcat(instr_asm, " $dst, $src"), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 336 | [], IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 337 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 338 | class EffectiveAddress<string instr_asm> : |
| 339 | FI<0x09, |
| 340 | (outs CPURegs:$dst), |
Bruno Cardoso Lopes | b42abeb | 2007-09-24 20:15:11 +0000 | [diff] [blame] | 341 | (ins mem:$addr), |
| 342 | instr_asm, |
| 343 | [(set CPURegs:$dst, addr:$addr)], IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 344 | |
| 345 | //===----------------------------------------------------------------------===// |
| 346 | // Pseudo instructions |
| 347 | //===----------------------------------------------------------------------===// |
| 348 | |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 349 | // As stack alignment is always done with addiu, we need a 16-bit immediate |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 350 | let Defs = [SP], Uses = [SP] in { |
Bruno Cardoso Lopes | e78080c | 2007-10-09 02:55:31 +0000 | [diff] [blame] | 351 | def ADJCALLSTACKDOWN : PseudoInstMips<(outs), (ins uimm16:$amt), |
| 352 | "!ADJCALLSTACKDOWN $amt", |
| 353 | [(callseq_start imm:$amt)]>; |
Bill Wendling | 0f8d9c0 | 2007-11-13 00:44:25 +0000 | [diff] [blame] | 354 | def ADJCALLSTACKUP : PseudoInstMips<(outs), (ins uimm16:$amt1, uimm16:$amt2), |
| 355 | "!ADJCALLSTACKUP $amt1", |
| 356 | [(callseq_end imm:$amt1, imm:$amt2)]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 357 | } |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 358 | |
Evan Cheng | 6e141fd | 2007-12-12 23:12:09 +0000 | [diff] [blame] | 359 | let isImplicitDef = 1 in |
Bruno Cardoso Lopes | e78080c | 2007-10-09 02:55:31 +0000 | [diff] [blame] | 360 | def IMPLICIT_DEF_CPURegs : PseudoInstMips<(outs CPURegs:$dst), (ins), |
| 361 | "!IMPLICIT_DEF $dst", |
| 362 | [(set CPURegs:$dst, (undef))]>; |
| 363 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 364 | // When handling PIC code the assembler needs .cpload and .cprestore |
| 365 | // directives. If the real instructions corresponding these directives |
| 366 | // are used, we have the same behavior, but get also a bunch of warnings |
Bruno Cardoso Lopes | e78080c | 2007-10-09 02:55:31 +0000 | [diff] [blame] | 367 | // from the assembler. |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 368 | def CPLOAD: PseudoInstMips<(outs), (ins CPURegs:$reg), |
Bruno Cardoso Lopes | c7db561 | 2007-11-05 03:02:32 +0000 | [diff] [blame] | 369 | ".set noreorder\n\t.cpload $reg\n\t.set reorder\n", []>; |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 370 | def CPRESTORE: PseudoInstMips<(outs), (ins uimm16:$loc), |
Bruno Cardoso Lopes | c7db561 | 2007-11-05 03:02:32 +0000 | [diff] [blame] | 371 | ".cprestore $loc\n", []>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 372 | |
| 373 | //===----------------------------------------------------------------------===// |
| 374 | // Instruction definition |
| 375 | //===----------------------------------------------------------------------===// |
| 376 | |
| 377 | //===----------------------------------------------------------------------===// |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 378 | // MipsI Instructions |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 379 | //===----------------------------------------------------------------------===// |
| 380 | |
| 381 | // Arithmetic |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 382 | |
| 383 | // ADDiu just accept 16-bit immediates but we handle this on Pat's. |
| 384 | // immZExt32 is used here so it can match GlobalAddress immediates. |
Bruno Cardoso Lopes | c7db561 | 2007-11-05 03:02:32 +0000 | [diff] [blame] | 385 | def ADDiu : ArithI<0x09, "addiu", add, uimm16, immZExt16>; |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 386 | def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>; |
| 387 | def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>; |
| 388 | def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>; |
| 389 | def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 390 | def ADD : ArithOverflowR<0x00, 0x20, "add">; |
| 391 | def SUB : ArithOverflowR<0x00, 0x22, "sub">; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 392 | |
| 393 | // Logical |
| 394 | def AND : LogicR<0x24, "and", and>; |
| 395 | def OR : LogicR<0x25, "or", or>; |
| 396 | def XOR : LogicR<0x26, "xor", xor>; |
| 397 | def ANDi : LogicI<0x0c, "andi", and>; |
| 398 | def ORi : LogicI<0x0d, "ori", or>; |
| 399 | def XORi : LogicI<0x0e, "xori", xor>; |
| 400 | def NOR : LogicNOR<0x00, 0x27, "nor">; |
| 401 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 402 | // Shifts |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 403 | def SLL : LogicR_shift_imm<0x00, "sll", shl>; |
| 404 | def SRL : LogicR_shift_imm<0x02, "srl", srl>; |
| 405 | def SRA : LogicR_shift_imm<0x03, "sra", sra>; |
| 406 | def SLLV : LogicR_shift_reg<0x04, "sllv", shl>; |
| 407 | def SRLV : LogicR_shift_reg<0x06, "srlv", srl>; |
| 408 | def SRAV : LogicR_shift_reg<0x07, "srav", sra>; |
| 409 | |
| 410 | // Load Upper Immediate |
| 411 | def LUi : LoadUpper<0x0f, "lui">; |
| 412 | |
| 413 | // Load/Store |
| 414 | def LB : LoadM<0x20, "lb", sextloadi8>; |
| 415 | def LBu : LoadM<0x24, "lbu", zextloadi8>; |
| 416 | def LH : LoadM<0x21, "lh", sextloadi16>; |
| 417 | def LHu : LoadM<0x25, "lhu", zextloadi16>; |
| 418 | def LW : LoadM<0x23, "lw", load>; |
| 419 | def SB : StoreM<0x28, "sb", truncstorei8>; |
| 420 | def SH : StoreM<0x29, "sh", truncstorei16>; |
| 421 | def SW : StoreM<0x2b, "sw", store>; |
| 422 | |
| 423 | // Conditional Branch |
| 424 | def BEQ : CBranch<0x04, "beq", seteq>; |
| 425 | def BNE : CBranch<0x05, "bne", setne>; |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 426 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 427 | let rt=1 in |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 428 | def BGEZ : CBranchZero<0x01, "bgez", setge>; |
| 429 | |
| 430 | let rt=0 in { |
| 431 | def BGTZ : CBranchZero<0x07, "bgtz", setgt>; |
| 432 | def BLEZ : CBranchZero<0x07, "blez", setle>; |
| 433 | def BLTZ : CBranchZero<0x01, "bltz", setlt>; |
| 434 | } |
| 435 | |
| 436 | // Set Condition Code |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 437 | def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>; |
| 438 | def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>; |
| 439 | def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>; |
| 440 | def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>; |
| 441 | |
| 442 | // Unconditional jump |
| 443 | def J : JumpFJ<0x02, "j">; |
| 444 | def JR : JumpFR<0x00, 0x08, "jr">; |
| 445 | |
| 446 | // Jump and Link (Call) |
| 447 | def JAL : JumpLink<0x03, "jal">; |
| 448 | def JALR : JumpLinkReg<0x00, 0x09, "jalr">; |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 449 | def BGEZAL : BranchLink<"bgezal">; |
| 450 | def BLTZAL : BranchLink<"bltzal">; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 451 | |
| 452 | // MulDiv and Move From Hi/Lo operations, have |
| 453 | // their correpondent SDNodes created on ISelDAG. |
| 454 | // Special Mul, Div operations |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 455 | def MULT : MulDiv<0x18, "mult", IIImul>; |
| 456 | def MULTu : MulDiv<0x19, "multu", IIImul>; |
| 457 | def DIV : MulDiv<0x1a, "div", IIIdiv>; |
| 458 | def DIVu : MulDiv<0x1b, "divu", IIIdiv>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 459 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 460 | // Move From Hi/Lo |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 461 | def MFHI : MoveFromTo<0x10, "mfhi">; |
| 462 | def MFLO : MoveFromTo<0x12, "mflo">; |
| 463 | def MTHI : MoveFromTo<0x11, "mthi">; |
| 464 | def MTLO : MoveFromTo<0x13, "mtlo">; |
| 465 | |
| 466 | // Count Leading |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 467 | // CLO/CLZ are part of the newer MIPS32(tm) instruction |
| 468 | // set and not older Mips I keep this for future use |
Bruno Cardoso Lopes | c7db561 | 2007-11-05 03:02:32 +0000 | [diff] [blame] | 469 | // though. |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 470 | //def CLO : CountLeading<0x21, "clo">; |
| 471 | //def CLZ : CountLeading<0x20, "clz">; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 472 | |
Bruno Cardoso Lopes | c7db561 | 2007-11-05 03:02:32 +0000 | [diff] [blame] | 473 | // MADD*/MSUB* are not part of MipsI either. |
| 474 | //def MADD : MArithR<0x00, "madd">; |
| 475 | //def MADDU : MArithR<0x01, "maddu">; |
| 476 | //def MSUB : MArithR<0x04, "msub">; |
| 477 | //def MSUBU : MArithR<0x05, "msubu">; |
| 478 | |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 479 | // No operation |
| 480 | let addr=0 in |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 481 | def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 482 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 483 | // Ret instruction - as mips does not have "ret" a |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 484 | // jr $ra must be generated. |
Evan Cheng | ffbacca | 2007-07-21 00:34:19 +0000 | [diff] [blame] | 485 | let isReturn=1, isTerminator=1, hasDelaySlot=1, |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 486 | isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 487 | { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 488 | def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 489 | "jr $target", [(MipsRet CPURegs:$target)], IIBranch>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 490 | } |
| 491 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 492 | // FrameIndexes are legalized when they are operands from load/store |
Bruno Cardoso Lopes | b42abeb | 2007-09-24 20:15:11 +0000 | [diff] [blame] | 493 | // instructions. The same not happens for stack address copies, so an |
| 494 | // add op with mem ComplexPattern is used and the stack address copy |
| 495 | // can be matched. It's similar to Sparc LEA_ADDRi |
| 496 | def LEA_ADDiu : EffectiveAddress<"addiu $dst, ${addr:stackloc}">; |
| 497 | |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 498 | //===----------------------------------------------------------------------===// |
| 499 | // Arbitrary patterns that map to one or more instructions |
| 500 | //===----------------------------------------------------------------------===// |
| 501 | |
| 502 | // Small immediates |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 503 | def : Pat<(i32 immSExt16:$in), |
Bruno Cardoso Lopes | 332a3d2 | 2007-07-11 22:47:02 +0000 | [diff] [blame] | 504 | (ADDiu ZERO, imm:$in)>; |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 505 | def : Pat<(i32 immZExt16:$in), |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 506 | (ORi ZERO, imm:$in)>; |
| 507 | |
| 508 | // Arbitrary immediates |
| 509 | def : Pat<(i32 imm:$imm), |
| 510 | (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; |
| 511 | |
| 512 | // Call |
| 513 | def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)), |
| 514 | (JAL tglobaladdr:$dst)>; |
| 515 | def : Pat<(MipsJmpLink (i32 texternalsym:$dst)), |
| 516 | (JAL texternalsym:$dst)>; |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 517 | def : Pat<(MipsJmpLink CPURegs:$dst), |
| 518 | (JALR CPURegs:$dst)>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 519 | |
| 520 | // GlobalAddress, Constant Pool, ExternalSymbol, and JumpTable |
| 521 | def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; |
| 522 | def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; |
Bruno Cardoso Lopes | c7db561 | 2007-11-05 03:02:32 +0000 | [diff] [blame] | 523 | def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 524 | (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; |
Bruno Cardoso Lopes | 753a987 | 2007-11-12 19:49:57 +0000 | [diff] [blame] | 525 | def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; |
| 526 | def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; |
| 527 | def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), |
| 528 | (ADDiu CPURegs:$hi, tjumptable:$lo)>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 529 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 530 | // Mips does not have not, so we increase the operation |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 531 | def : Pat<(not CPURegs:$in), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 532 | (NOR CPURegs:$in, ZERO)>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 533 | |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 534 | // extended load and stores |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 535 | def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 536 | def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; |
| 537 | def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 538 | def : Pat<(truncstorei1 CPURegs:$src, addr:$addr), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 539 | (SB CPURegs:$src, addr:$addr)>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 540 | |
Bruno Cardoso Lopes | c7db561 | 2007-11-05 03:02:32 +0000 | [diff] [blame] | 541 | // some peepholes |
| 542 | def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; |
| 543 | |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 544 | /// |
| 545 | /// brcond patterns |
| 546 | /// |
| 547 | |
| 548 | // direct match equal/notequal zero branches |
| 549 | def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst), |
Bruno Cardoso Lopes | 332a3d2 | 2007-07-11 22:47:02 +0000 | [diff] [blame] | 550 | (BNE CPURegs:$lhs, ZERO, bb:$dst)>; |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 551 | def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst), |
| 552 | (BEQ CPURegs:$lhs, ZERO, bb:$dst)>; |
Bruno Cardoso Lopes | 332a3d2 | 2007-07-11 22:47:02 +0000 | [diff] [blame] | 553 | |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 554 | def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 555 | (BGEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 556 | def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 557 | (BGEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 558 | |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 559 | def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst), |
| 560 | (BGTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; |
| 561 | def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst), |
| 562 | (BGTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; |
| 563 | |
| 564 | def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst), |
| 565 | (BLEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; |
| 566 | def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst), |
| 567 | (BLEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; |
| 568 | |
| 569 | def : Pat<(brcond (setlt CPURegs:$lhs, immSExt16:$rhs), bb:$dst), |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 570 | (BNE (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; |
Bruno Cardoso Lopes | 972f589 | 2007-06-06 07:42:06 +0000 | [diff] [blame] | 571 | def : Pat<(brcond (setult CPURegs:$lhs, immZExt16:$rhs), bb:$dst), |
| 572 | (BNE (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>; |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 573 | def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst), |
| 574 | (BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>; |
| 575 | def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst), |
| 576 | (BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>; |
| 577 | |
| 578 | def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst), |
| 579 | (BLTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; |
| 580 | def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst), |
| 581 | (BLTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>; |
| 582 | |
| 583 | // generic brcond pattern |
| 584 | def : Pat<(brcond CPURegs:$cond, bb:$dst), |
| 585 | (BNE CPURegs:$cond, ZERO, bb:$dst)>; |
| 586 | |
| 587 | /// |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 588 | /// setcc patterns, only matched when there |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 589 | /// is no brcond following a setcc operation |
| 590 | /// |
| 591 | |
| 592 | // setcc 2 register operands |
| 593 | def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs), |
| 594 | (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>; |
| 595 | def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs), |
| 596 | (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>; |
| 597 | |
| 598 | def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs), |
| 599 | (SLT CPURegs:$rhs, CPURegs:$lhs)>; |
| 600 | def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs), |
| 601 | (SLTu CPURegs:$rhs, CPURegs:$lhs)>; |
| 602 | |
| 603 | def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs), |
| 604 | (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>; |
| 605 | def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs), |
| 606 | (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>; |
| 607 | |
| 608 | def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs), |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 609 | (OR (SLT CPURegs:$lhs, CPURegs:$rhs), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 610 | (SLT CPURegs:$rhs, CPURegs:$lhs))>; |
| 611 | |
| 612 | def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs), |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 613 | (XORi (OR (SLT CPURegs:$lhs, CPURegs:$rhs), |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 614 | (SLT CPURegs:$rhs, CPURegs:$lhs)), 1)>; |
Eric Christopher | 3c999a2 | 2007-10-26 04:00:13 +0000 | [diff] [blame] | 615 | |
Bruno Cardoso Lopes | 9710536 | 2007-08-18 02:37:46 +0000 | [diff] [blame] | 616 | // setcc reg/imm operands |
| 617 | def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs), |
| 618 | (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>; |
| 619 | def : Pat<(setuge CPURegs:$lhs, immZExt16:$rhs), |
| 620 | (XORi (SLTiu CPURegs:$lhs, immZExt16:$rhs), 1)>; |