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Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001//===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MIPS implementation of the MRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "mips-reg-info"
15
16#include "Mips.h"
17#include "MipsRegisterInfo.h"
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +000018#include "MipsMachineFunction.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000019#include "llvm/Constants.h"
20#include "llvm/Type.h"
21#include "llvm/Function.h"
22#include "llvm/CodeGen/ValueTypes.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineLocation.h"
27#include "llvm/Target/TargetFrameInfo.h"
28#include "llvm/Target/TargetMachine.h"
29#include "llvm/Target/TargetOptions.h"
30#include "llvm/Target/TargetInstrInfo.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/ADT/BitVector.h"
34#include "llvm/ADT/STLExtras.h"
35//#include "MipsSubtarget.h"
36
37using namespace llvm;
38
39// TODO: add subtarget support
40MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
41 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
42 TII(tii) {}
43
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +000044/// getRegisterNumbering - Given the enum value for some register, e.g.
45/// Mips::RA, return the number that it corresponds to (e.g. 31).
46unsigned MipsRegisterInfo::
47getRegisterNumbering(unsigned RegEnum)
48{
49 switch (RegEnum) {
50 case Mips::ZERO : return 0;
51 case Mips::AT : return 1;
52 case Mips::V0 : return 2;
53 case Mips::V1 : return 3;
54 case Mips::A0 : return 4;
55 case Mips::A1 : return 5;
56 case Mips::A2 : return 6;
57 case Mips::A3 : return 7;
58 case Mips::T0 : return 8;
59 case Mips::T1 : return 9;
60 case Mips::T2 : return 10;
61 case Mips::T3 : return 11;
62 case Mips::T4 : return 12;
63 case Mips::T5 : return 13;
64 case Mips::T6 : return 14;
65 case Mips::T7 : return 15;
66 case Mips::T8 : return 16;
67 case Mips::T9 : return 17;
68 case Mips::S0 : return 18;
69 case Mips::S1 : return 19;
70 case Mips::S2 : return 20;
71 case Mips::S3 : return 21;
72 case Mips::S4 : return 22;
73 case Mips::S5 : return 23;
74 case Mips::S6 : return 24;
75 case Mips::S7 : return 25;
76 case Mips::K0 : return 26;
77 case Mips::K1 : return 27;
78 case Mips::GP : return 28;
79 case Mips::SP : return 29;
80 case Mips::FP : return 30;
81 case Mips::RA : return 31;
82 default: assert(0 && "Unknown register number!");
83 }
84}
85
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000086void MipsRegisterInfo::
87storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
Evan Chengd64b5c82007-12-05 03:14:33 +000088 unsigned SrcReg, bool isKill, int FI,
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000089 const TargetRegisterClass *RC) const
90{
91 if (RC == Mips::CPURegsRegisterClass)
Evan Chengd64b5c82007-12-05 03:14:33 +000092 BuildMI(MBB, I, TII.get(Mips::SW)).addReg(SrcReg, false, false, isKill)
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +000093 .addImm(0).addFrameIndex(FI);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000094 else
95 assert(0 && "Can't store this register to stack slot");
96}
97
Evan Cheng66f0f642007-10-05 01:32:41 +000098void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
Evan Chengd64b5c82007-12-05 03:14:33 +000099 bool isKill,
Evan Chengf0a0cdd2007-10-18 22:40:57 +0000100 SmallVectorImpl<MachineOperand> &Addr,
Evan Cheng66f0f642007-10-05 01:32:41 +0000101 const TargetRegisterClass *RC,
Evan Cheng58184e62007-10-18 21:29:24 +0000102 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Evan Cheng66f0f642007-10-05 01:32:41 +0000103 if (RC != Mips::CPURegsRegisterClass)
104 assert(0 && "Can't store this register");
105 MachineInstrBuilder MIB = BuildMI(TII.get(Mips::SW))
Evan Chengd64b5c82007-12-05 03:14:33 +0000106 .addReg(SrcReg, false, false, isKill);
Evan Cheng66f0f642007-10-05 01:32:41 +0000107 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
108 MachineOperand &MO = Addr[i];
109 if (MO.isRegister())
110 MIB.addReg(MO.getReg());
111 else if (MO.isImmediate())
112 MIB.addImm(MO.getImmedValue());
113 else
114 MIB.addFrameIndex(MO.getFrameIndex());
115 }
116 NewMIs.push_back(MIB);
117 return;
118}
119
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000120void MipsRegisterInfo::
121loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
122 unsigned DestReg, int FI,
123 const TargetRegisterClass *RC) const
124{
125 if (RC == Mips::CPURegsRegisterClass)
126 BuildMI(MBB, I, TII.get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
127 else
128 assert(0 && "Can't load this register from stack slot");
129}
130
Evan Cheng66f0f642007-10-05 01:32:41 +0000131void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Chengf0a0cdd2007-10-18 22:40:57 +0000132 SmallVectorImpl<MachineOperand> &Addr,
Evan Cheng66f0f642007-10-05 01:32:41 +0000133 const TargetRegisterClass *RC,
Evan Cheng58184e62007-10-18 21:29:24 +0000134 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Evan Cheng66f0f642007-10-05 01:32:41 +0000135 if (RC != Mips::CPURegsRegisterClass)
136 assert(0 && "Can't load this register");
137 MachineInstrBuilder MIB = BuildMI(TII.get(Mips::LW), DestReg);
138 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
139 MachineOperand &MO = Addr[i];
140 if (MO.isRegister())
141 MIB.addReg(MO.getReg());
142 else if (MO.isImmediate())
143 MIB.addImm(MO.getImmedValue());
144 else
145 MIB.addFrameIndex(MO.getFrameIndex());
146 }
147 NewMIs.push_back(MIB);
148 return;
149}
150
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000151void MipsRegisterInfo::
152copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
153 unsigned DestReg, unsigned SrcReg,
Evan Cheng9efce632007-09-26 06:25:56 +0000154 const TargetRegisterClass *DestRC,
155 const TargetRegisterClass *SrcRC) const
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000156{
Evan Cheng9efce632007-09-26 06:25:56 +0000157 if (DestRC != SrcRC) {
158 cerr << "Not yet supported!";
159 abort();
160 }
161
162 if (DestRC == Mips::CPURegsRegisterClass)
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000163 BuildMI(MBB, I, TII.get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
164 .addReg(SrcReg);
165 else
166 assert (0 && "Can't copy this register");
167}
168
169void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator I,
171 unsigned DestReg,
172 const MachineInstr *Orig) const
173{
174 MachineInstr *MI = Orig->clone();
175 MI->getOperand(0).setReg(DestReg);
176 MBB.insert(I, MI);
177}
178
179MachineInstr *MipsRegisterInfo::
Evan Chengaee4af62007-12-02 08:30:39 +0000180foldMemoryOperand(MachineInstr* MI,
181 SmallVectorImpl<unsigned> &Ops, int FI) const
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000182{
Evan Chengaee4af62007-12-02 08:30:39 +0000183 if (Ops.size() != 1) return NULL;
184
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000185 MachineInstr *NewMI = NULL;
186
187 switch (MI->getOpcode())
188 {
189 case Mips::ADDu:
190 if ((MI->getOperand(0).isRegister()) &&
191 (MI->getOperand(1).isRegister()) &&
192 (MI->getOperand(1).getReg() == Mips::ZERO) &&
193 (MI->getOperand(2).isRegister()))
194 {
Evan Chengaee4af62007-12-02 08:30:39 +0000195 if (Ops[0] == 0) // COPY -> STORE
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000196 NewMI = BuildMI(TII.get(Mips::SW)).addFrameIndex(FI)
197 .addImm(0).addReg(MI->getOperand(2).getReg());
Evan Chengaee4af62007-12-02 08:30:39 +0000198 else // COPY -> LOAD
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000199 NewMI = BuildMI(TII.get(Mips::LW), MI->getOperand(0)
200 .getReg()).addImm(0).addFrameIndex(FI);
201 }
202 break;
203 }
204
205 if (NewMI)
206 NewMI->copyKillDeadInfo(MI);
207 return NewMI;
208}
209
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000210//===----------------------------------------------------------------------===//
211//
212// Callee Saved Registers methods
213//
214//===----------------------------------------------------------------------===//
215
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000216/// Mips Callee Saved Registers
217const unsigned* MipsRegisterInfo::
Evan Cheng64d80e32007-07-19 01:14:50 +0000218getCalleeSavedRegs(const MachineFunction *MF) const
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000219{
220 // Mips calle-save register range is $16-$26(s0-s7)
221 static const unsigned CalleeSavedRegs[] = {
222 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
223 Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
224 };
225 return CalleeSavedRegs;
226}
227
228/// Mips Callee Saved Register Classes
229const TargetRegisterClass* const*
Evan Cheng64d80e32007-07-19 01:14:50 +0000230MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000231{
232 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
233 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
234 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
235 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
236 &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 0
237 };
238 return CalleeSavedRegClasses;
239}
240
241BitVector MipsRegisterInfo::
242getReservedRegs(const MachineFunction &MF) const
243{
244 BitVector Reserved(getNumRegs());
245 Reserved.set(Mips::ZERO);
246 Reserved.set(Mips::AT);
247 Reserved.set(Mips::K0);
248 Reserved.set(Mips::K1);
249 Reserved.set(Mips::GP);
250 Reserved.set(Mips::SP);
251 Reserved.set(Mips::FP);
252 Reserved.set(Mips::RA);
253 return Reserved;
254}
255
256//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000257//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000258// Stack Frame Processing methods
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000259// +----------------------------+
260//
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000261// The stack is allocated decrementing the stack pointer on
262// the first instruction of a function prologue. Once decremented,
263// all stack referencesare are done thought a positive offset
264// from the stack/frame pointer, so the stack is considering
265// to grow up! Otherwise terrible hacks would have to be made
266// to get this stack ABI compliant :)
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000267//
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000268// The stack frame required by the ABI:
269// Offset
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000270//
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000271// 0 ----------
272// 4 Args to pass
273// . saved $GP (used in PIC - not supported yet)
274// . Local Area
275// . saved "Callee Saved" Registers
276// . saved FP
277// . saved RA
278// StackSize -----------
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000279//
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000280// Offset - offset from sp after stack allocation on function prologue
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000281//
282// The sp is the stack pointer subtracted/added from the stack size
283// at the Prologue/Epilogue
284//
285// References to the previous stack (to obtain arguments) are done
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000286// with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000287//
288// Examples:
289// - reference to the actual stack frame
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000290// for any local area var there is smt like : FI >= 0, StackOffset: 4
291// sw REGX, 4(SP)
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000292//
293// - reference to previous stack frame
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000294// suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000295// The emitted instruction will be something like:
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000296// lw REGX, 16+StackSize(SP)
297//
298// Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all
299// stack references (ObjectOffset) created to reference the function
300// arguments, are negative numbers. This way, on eliminateFrameIndex it's
301// possible to detect those references and the offsets are adjusted to
302// their real location.
303//
304//
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000305//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000306//===----------------------------------------------------------------------===//
307
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000308// hasFP - Return true if the specified function should have a dedicated frame
309// pointer register. This is true if the function has variable sized allocas or
310// if frame pointer elimination is disabled.
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000311bool MipsRegisterInfo::
312hasFP(const MachineFunction &MF) const {
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000313 return (NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000314}
315
316// This function eliminate ADJCALLSTACKDOWN,
317// ADJCALLSTACKUP pseudo instructions
318void MipsRegisterInfo::
319eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
320 MachineBasicBlock::iterator I) const {
321 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
322 MBB.erase(I);
323}
324
325// FrameIndex represent objects inside a abstract stack.
326// We must replace FrameIndex with an stack/frame pointer
327// direct reference.
328void MipsRegisterInfo::
329eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
330 RegScavenger *RS) const
331{
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +0000332 MachineInstr &MI = *II;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000333 MachineFunction &MF = *MI.getParent()->getParent();
334
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000335 unsigned i = 0;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000336 while (!MI.getOperand(i).isFrameIndex()) {
337 ++i;
338 assert(i < MI.getNumOperands() &&
339 "Instr doesn't have FrameIndex operand!");
340 }
341
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000342 int FrameIndex = MI.getOperand(i).getFrameIndex();
343 int stackSize = MF.getFrameInfo()->getStackSize();
344 int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
345
346 #ifndef NDEBUG
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000347 DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
348 DOUT << "<--------->\n";
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000349 MI.print(DOUT);
350 DOUT << "FrameIndex : " << FrameIndex << "\n";
351 DOUT << "spOffset : " << spOffset << "\n";
352 DOUT << "stackSize : " << stackSize << "\n";
353 #endif
354
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000355 // as explained on LowerFORMAL_ARGUMENTS, detect negative offsets
356 // and adjust SPOffsets considering the final stack size.
357 int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
358 Offset += MI.getOperand(i-1).getImm();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000359
360 #ifndef NDEBUG
361 DOUT << "Offset : " << Offset << "\n";
362 DOUT << "<--------->\n";
363 #endif
364
365 MI.getOperand(i-1).ChangeToImmediate(Offset);
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +0000366 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000367}
368
369void MipsRegisterInfo::
370emitPrologue(MachineFunction &MF) const
371{
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000372 MachineBasicBlock &MBB = MF.front();
373 MachineFrameInfo *MFI = MF.getFrameInfo();
374 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
375 MachineBasicBlock::iterator MBBI = MBB.begin();
Bruno Cardoso Lopes8262df32007-10-09 03:15:11 +0000376 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000377
Bruno Cardoso Lopes8262df32007-10-09 03:15:11 +0000378 // Replace the dummy '0' SPOffset by the negative
379 // offsets, as explained on LowerFORMAL_ARGUMENTS
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000380 MipsFI->adjustLoadArgsFI(MFI);
381 MipsFI->adjustStoreVarArgsFI(MFI);
382
Bruno Cardoso Lopes055c7eb2007-08-18 02:19:09 +0000383 // Get the number of bytes to allocate from the FrameInfo.
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000384 int NumBytes = (int) MFI->getStackSize();
385
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000386 #ifndef NDEBUG
Bruno Cardoso Lopes055c7eb2007-08-18 02:19:09 +0000387 DOUT << "\n<--- EMIT PROLOGUE --->\n";
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000388 DOUT << "Actual Stack size :" << NumBytes << "\n";
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000389 #endif
390
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000391 // No need to allocate space on the stack.
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000392 if (NumBytes == 0) return;
393
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000394 int FPOffset, RAOffset;
395
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000396 // Allocate space for saved RA and FP when needed
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000397 if ((hasFP(MF)) && (MFI->hasCalls())) {
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000398 FPOffset = NumBytes;
399 RAOffset = (NumBytes+4);
400 NumBytes += 8;
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000401 } else if ((!hasFP(MF)) && (MFI->hasCalls())) {
402 FPOffset = 0;
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000403 RAOffset = NumBytes;
404 NumBytes += 4;
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000405 } else if ((hasFP(MF)) && (!MFI->hasCalls())) {
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000406 FPOffset = NumBytes;
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000407 RAOffset = 0;
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000408 NumBytes += 4;
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000409 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000410
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000411 MFI->setObjectOffset(MFI->CreateStackObject(4,4), FPOffset);
412 MFI->setObjectOffset(MFI->CreateStackObject(4,4), RAOffset);
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000413 MipsFI->setFPStackOffset(FPOffset);
414 MipsFI->setRAStackOffset(RAOffset);
415
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000416 // Align stack.
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000417 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
418 NumBytes = ((NumBytes+Align-1)/Align*Align);
419
420 #ifndef NDEBUG
Bruno Cardoso Lopes51195af2007-08-28 05:13:42 +0000421 DOUT << "FPOffset :" << FPOffset << "\n";
422 DOUT << "RAOffset :" << RAOffset << "\n";
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000423 DOUT << "New stack size :" << NumBytes << "\n\n";
424 #endif
425
426 // Update frame info
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000427 MFI->setStackSize(NumBytes);
428
Bruno Cardoso Lopes8262df32007-10-09 03:15:11 +0000429 // PIC speficic function prologue
430 if (isPIC)
431 BuildMI(MBB, MBBI, TII.get(Mips::CPLOAD)).addReg(Mips::T9);
432
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000433 // Adjust stack : addi sp, sp, (-imm)
434 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
435 .addReg(Mips::SP).addImm(-NumBytes);
436
437 // Save the return address only if the function isnt a leaf one.
438 // sw $ra, stack_loc($sp)
439 if (MFI->hasCalls()) {
440 BuildMI(MBB, MBBI, TII.get(Mips::SW))
441 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
442 }
443
444 // if framepointer enabled, save it and set it
445 // to point to the stack pointer
446 if (hasFP(MF)) {
447 // sw $fp,stack_loc($sp)
448 BuildMI(MBB, MBBI, TII.get(Mips::SW))
449 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
450
451 // move $fp, $sp
452 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::FP)
453 .addReg(Mips::SP).addReg(Mips::ZERO);
454 }
Bruno Cardoso Lopes8262df32007-10-09 03:15:11 +0000455
456 // PIC speficic function prologue
457 if ((isPIC) && (MFI->hasCalls()))
458 BuildMI(MBB, MBBI, TII.get(Mips::CPRESTORE))
459 .addImm(MipsFI->getGPStackOffset());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000460}
461
462void MipsRegisterInfo::
463emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
464{
465 MachineBasicBlock::iterator MBBI = prior(MBB.end());
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000466 MachineFrameInfo *MFI = MF.getFrameInfo();
467 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000468
469 // Get the number of bytes from FrameInfo
470 int NumBytes = (int) MFI->getStackSize();
471
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000472 // Get the FI's where RA and FP are saved.
473 int FPOffset = MipsFI->getFPStackOffset();
474 int RAOffset = MipsFI->getRAStackOffset();
475
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000476 // if framepointer enabled, restore it and restore the
477 // stack pointer
478 if (hasFP(MF)) {
479 // move $sp, $fp
480 BuildMI(MBB, MBBI, TII.get(Mips::ADDu), Mips::SP)
481 .addReg(Mips::FP).addReg(Mips::ZERO);
482
483 // lw $fp,stack_loc($sp)
484 BuildMI(MBB, MBBI, TII.get(Mips::LW))
485 .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
486 }
487
488 // Restore the return address only if the function isnt a leaf one.
489 // lw $ra, stack_loc($sp)
490 if (MFI->hasCalls()) {
491 BuildMI(MBB, MBBI, TII.get(Mips::LW))
492 .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
493 }
494
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000495 // adjust stack : insert addi sp, sp, (imm)
496 if (NumBytes) {
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000497 BuildMI(MBB, MBBI, TII.get(Mips::ADDiu), Mips::SP)
498 .addReg(Mips::SP).addImm(NumBytes);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000499 }
500}
501
502void MipsRegisterInfo::
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000503processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +0000504 // Set the SPOffset on the FI where GP must be saved/loaded.
505 MachineFrameInfo *MFI = MF.getFrameInfo();
506 if (MFI->hasCalls()) {
507 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
508 #ifndef NDEBUG
509 DOUT << "processFunctionBeforeFrameFinalized\n";
510 DOUT << "GPOffset :" << MipsFI->getGPStackOffset() << "\n";
511 DOUT << "FI :" << MipsFI->getGPFI() << "\n";
512 #endif
513 MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
514 }
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000515}
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000516
517unsigned MipsRegisterInfo::
518getRARegister() const {
519 return Mips::RA;
520}
521
522unsigned MipsRegisterInfo::
523getFrameRegister(MachineFunction &MF) const {
Bruno Cardoso Lopes7b155fb2007-07-11 23:21:31 +0000524 return hasFP(MF) ? Mips::FP : Mips::SP;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000525}
526
527unsigned MipsRegisterInfo::
528getEHExceptionRegister() const {
529 assert(0 && "What is the exception register");
530 return 0;
531}
532
533unsigned MipsRegisterInfo::
534getEHHandlerRegister() const {
535 assert(0 && "What is the exception handler register");
536 return 0;
537}
538
Anton Korobeynikovf191c802007-11-11 19:50:10 +0000539int MipsRegisterInfo::
Dale Johannesenb97aec62007-11-13 19:13:01 +0000540getDwarfRegNum(unsigned RegNum, bool isEH) const {
Anton Korobeynikovf191c802007-11-11 19:50:10 +0000541 assert(0 && "What is the dwarf register number");
542 return -1;
543}
544
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000545#include "MipsGenRegisterInfo.inc"
546