Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 1 | //===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame^] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | //===----------------------------------------------------------------------===// |
| 11 | // X86 Instruction Format Definitions. |
| 12 | // |
| 13 | |
| 14 | // Format specifies the encoding used by the instruction. This is part of the |
| 15 | // ad-hoc solution used to emit machine instruction encodings by our machine |
| 16 | // code emitter. |
| 17 | class Format<bits<6> val> { |
| 18 | bits<6> Value = val; |
| 19 | } |
| 20 | |
| 21 | def Pseudo : Format<0>; def RawFrm : Format<1>; |
| 22 | def AddRegFrm : Format<2>; def MRMDestReg : Format<3>; |
| 23 | def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>; |
| 24 | def MRMSrcMem : Format<6>; |
| 25 | def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>; |
| 26 | def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>; |
| 27 | def MRM6r : Format<22>; def MRM7r : Format<23>; |
| 28 | def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; |
| 29 | def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; |
| 30 | def MRM6m : Format<30>; def MRM7m : Format<31>; |
| 31 | def MRMInitReg : Format<32>; |
| 32 | |
| 33 | |
| 34 | // ImmType - This specifies the immediate type used by an instruction. This is |
| 35 | // part of the ad-hoc solution used to emit machine instruction encodings by our |
| 36 | // machine code emitter. |
| 37 | class ImmType<bits<3> val> { |
| 38 | bits<3> Value = val; |
| 39 | } |
| 40 | def NoImm : ImmType<0>; |
| 41 | def Imm8 : ImmType<1>; |
| 42 | def Imm16 : ImmType<2>; |
| 43 | def Imm32 : ImmType<3>; |
| 44 | def Imm64 : ImmType<4>; |
| 45 | |
| 46 | // FPFormat - This specifies what form this FP instruction has. This is used by |
| 47 | // the Floating-Point stackifier pass. |
| 48 | class FPFormat<bits<3> val> { |
| 49 | bits<3> Value = val; |
| 50 | } |
| 51 | def NotFP : FPFormat<0>; |
| 52 | def ZeroArgFP : FPFormat<1>; |
| 53 | def OneArgFP : FPFormat<2>; |
| 54 | def OneArgFPRW : FPFormat<3>; |
| 55 | def TwoArgFP : FPFormat<4>; |
| 56 | def CompareFP : FPFormat<5>; |
| 57 | def CondMovFP : FPFormat<6>; |
| 58 | def SpecialFP : FPFormat<7>; |
| 59 | |
| 60 | // Prefix byte classes which are used to indicate to the ad-hoc machine code |
| 61 | // emitter that various prefix bytes are required. |
| 62 | class OpSize { bit hasOpSizePrefix = 1; } |
| 63 | class AdSize { bit hasAdSizePrefix = 1; } |
| 64 | class REX_W { bit hasREX_WPrefix = 1; } |
| 65 | class TB { bits<4> Prefix = 1; } |
| 66 | class REP { bits<4> Prefix = 2; } |
| 67 | class D8 { bits<4> Prefix = 3; } |
| 68 | class D9 { bits<4> Prefix = 4; } |
| 69 | class DA { bits<4> Prefix = 5; } |
| 70 | class DB { bits<4> Prefix = 6; } |
| 71 | class DC { bits<4> Prefix = 7; } |
| 72 | class DD { bits<4> Prefix = 8; } |
| 73 | class DE { bits<4> Prefix = 9; } |
| 74 | class DF { bits<4> Prefix = 10; } |
| 75 | class XD { bits<4> Prefix = 11; } |
| 76 | class XS { bits<4> Prefix = 12; } |
| 77 | class T8 { bits<4> Prefix = 13; } |
| 78 | class TA { bits<4> Prefix = 14; } |
| 79 | |
| 80 | class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins, |
| 81 | string AsmStr> |
| 82 | : Instruction { |
| 83 | let Namespace = "X86"; |
| 84 | |
| 85 | bits<8> Opcode = opcod; |
| 86 | Format Form = f; |
| 87 | bits<6> FormBits = Form.Value; |
| 88 | ImmType ImmT = i; |
| 89 | bits<3> ImmTypeBits = ImmT.Value; |
| 90 | |
| 91 | dag OutOperandList = outs; |
| 92 | dag InOperandList = ins; |
| 93 | string AsmString = AsmStr; |
| 94 | |
| 95 | // |
| 96 | // Attributes specific to X86 instructions... |
| 97 | // |
| 98 | bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? |
| 99 | bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix? |
| 100 | |
| 101 | bits<4> Prefix = 0; // Which prefix byte does this inst have? |
| 102 | bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix? |
| 103 | FPFormat FPForm; // What flavor of FP instruction is this? |
| 104 | bits<3> FPFormBits = 0; |
| 105 | } |
| 106 | |
| 107 | class I<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern> |
| 108 | : X86Inst<o, f, NoImm, outs, ins, asm> { |
| 109 | let Pattern = pattern; |
| 110 | let CodeSize = 3; |
| 111 | } |
| 112 | class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern> |
| 113 | : X86Inst<o, f, Imm8 , outs, ins, asm> { |
| 114 | let Pattern = pattern; |
| 115 | let CodeSize = 3; |
| 116 | } |
| 117 | class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern> |
| 118 | : X86Inst<o, f, Imm16, outs, ins, asm> { |
| 119 | let Pattern = pattern; |
| 120 | let CodeSize = 3; |
| 121 | } |
| 122 | class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern> |
| 123 | : X86Inst<o, f, Imm32, outs, ins, asm> { |
| 124 | let Pattern = pattern; |
| 125 | let CodeSize = 3; |
| 126 | } |
| 127 | |
| 128 | // FPStack Instruction Templates: |
| 129 | // FPI - Floating Point Instruction template. |
| 130 | class FPI<bits<8> o, Format F, dag outs, dag ins, string asm> |
| 131 | : I<o, F, outs, ins, asm, []> {} |
| 132 | |
| 133 | // FpI_ - Floating Point Psuedo Instruction template. Not Predicated. |
| 134 | class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern> |
| 135 | : X86Inst<0, Pseudo, NoImm, outs, ins, ""> { |
| 136 | let FPForm = fp; let FPFormBits = FPForm.Value; |
| 137 | let Pattern = pattern; |
| 138 | } |
| 139 | |
| 140 | // SSE1 Instruction Templates: |
| 141 | // |
| 142 | // SSI - SSE1 instructions with XS prefix. |
| 143 | // PSI - SSE1 instructions with TB prefix. |
| 144 | // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix. |
| 145 | |
| 146 | class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 147 | : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>; |
Chris Lattner | d7610e1 | 2007-12-16 20:12:41 +0000 | [diff] [blame] | 148 | class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 149 | : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>; |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 150 | class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 151 | : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>; |
| 152 | class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, |
| 153 | list<dag> pattern> |
| 154 | : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>; |
| 155 | |
| 156 | // SSE2 Instruction Templates: |
| 157 | // |
| 158 | // SDI - SSE2 instructions with XD prefix. |
Evan Cheng | 700a0fb | 2007-12-20 19:57:09 +0000 | [diff] [blame] | 159 | // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 160 | // PDI - SSE2 instructions with TB and OpSize prefixes. |
| 161 | // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes. |
| 162 | |
| 163 | class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 164 | : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>; |
Evan Cheng | 700a0fb | 2007-12-20 19:57:09 +0000 | [diff] [blame] | 165 | class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, |
| 166 | list<dag> pattern> |
| 167 | : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>; |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 168 | class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 169 | : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>; |
| 170 | class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, |
| 171 | list<dag> pattern> |
| 172 | : Ii8<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>; |
| 173 | |
| 174 | // SSE3 Instruction Templates: |
| 175 | // |
| 176 | // S3I - SSE3 instructions with TB and OpSize prefixes. |
| 177 | // S3SI - SSE3 instructions with XS prefix. |
| 178 | // S3DI - SSE3 instructions with XD prefix. |
| 179 | |
| 180 | class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 181 | : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE3]>; |
| 182 | class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 183 | : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE3]>; |
| 184 | class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 185 | : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>; |
| 186 | |
| 187 | |
| 188 | // X86-64 Instruction templates... |
| 189 | // |
| 190 | |
| 191 | class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 192 | : I<o, F, outs, ins, asm, pattern>, REX_W; |
| 193 | class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm, |
| 194 | list<dag> pattern> |
| 195 | : Ii8<o, F, outs, ins, asm, pattern>, REX_W; |
| 196 | class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm, |
| 197 | list<dag> pattern> |
| 198 | : Ii32<o, F, outs, ins, asm, pattern>, REX_W; |
| 199 | |
| 200 | class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm, |
| 201 | list<dag> pattern> |
| 202 | : X86Inst<o, f, Imm64, outs, ins, asm>, REX_W { |
| 203 | let Pattern = pattern; |
| 204 | let CodeSize = 3; |
| 205 | } |
| 206 | |
| 207 | class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm, |
| 208 | list<dag> pattern> |
| 209 | : SSI<o, F, outs, ins, asm, pattern>, REX_W; |
| 210 | class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm, |
| 211 | list<dag> pattern> |
| 212 | : SDI<o, F, outs, ins, asm, pattern>, REX_W; |
| 213 | class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm, |
| 214 | list<dag> pattern> |
| 215 | : PDI<o, F, outs, ins, asm, pattern>, REX_W; |
| 216 | |
| 217 | // MMX Instruction templates |
| 218 | // |
| 219 | |
| 220 | // MMXI - MMX instructions with TB prefix. |
| 221 | // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes. |
| 222 | // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. |
| 223 | // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix. |
| 224 | // MMXID - MMX instructions with XD prefix. |
| 225 | // MMXIS - MMX instructions with XS prefix. |
| 226 | class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 227 | : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>; |
| 228 | class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 229 | : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>; |
| 230 | class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 231 | : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>; |
| 232 | class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 233 | : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>; |
| 234 | class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 235 | : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>; |
| 236 | class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> |
| 237 | : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>; |
| 238 | |