Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 1 | //===-- SparcV9RegInfo.cpp - SparcV9 Target Register Information --------------===// |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | ed5171e | 2002-02-03 07:52:04 +0000 | [diff] [blame] | 9 | // |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 10 | // This file contains implementation of SparcV9 specific helper methods |
Chris Lattner | ed5171e | 2002-02-03 07:52:04 +0000 | [diff] [blame] | 11 | // used for register allocation. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Misha Brukman | fce1143 | 2002-10-28 00:28:31 +0000 | [diff] [blame] | 15 | #include "llvm/CodeGen/MachineFunction.h" |
Chris Lattner | 1b849be | 2002-12-28 20:21:29 +0000 | [diff] [blame] | 16 | #include "llvm/CodeGen/MachineFunctionInfo.h" |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 17 | #include "llvm/CodeGen/InstrSelection.h" |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 18 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Anand Shukla | 55afc33 | 2003-06-01 02:48:23 +0000 | [diff] [blame] | 19 | #include "llvm/CodeGen/MachineCodeForInstruction.h" |
Chris Lattner | 08d4963 | 2004-02-29 19:12:51 +0000 | [diff] [blame] | 20 | #include "MachineInstrAnnot.h" |
Chris Lattner | 1d415a9 | 2004-01-09 16:17:09 +0000 | [diff] [blame] | 21 | #include "RegAlloc/LiveRangeInfo.h" |
| 22 | #include "RegAlloc/LiveRange.h" |
Misha Brukman | d71295a | 2003-12-17 22:04:00 +0000 | [diff] [blame] | 23 | #include "llvm/DerivedTypes.h" |
| 24 | #include "llvm/Function.h" |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 25 | #include "llvm/iTerminators.h" |
| 26 | #include "llvm/iOther.h" |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 27 | #include "SparcV9Internals.h" |
| 28 | #include "SparcV9RegClassInfo.h" |
| 29 | #include "SparcV9RegInfo.h" |
| 30 | #include "SparcV9TargetMachine.h" |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 31 | |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 32 | namespace llvm { |
| 33 | |
Chris Lattner | 92ba2aa | 2003-01-14 23:05:08 +0000 | [diff] [blame] | 34 | enum { |
| 35 | BadRegClass = ~0 |
| 36 | }; |
| 37 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 38 | SparcV9RegInfo::SparcV9RegInfo(const SparcV9TargetMachine &tgt) |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 39 | : TargetRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32) |
| 40 | { |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 41 | MachineRegClassArr.push_back(new SparcV9IntRegClass(IntRegClassID)); |
| 42 | MachineRegClassArr.push_back(new SparcV9FloatRegClass(FloatRegClassID)); |
| 43 | MachineRegClassArr.push_back(new SparcV9IntCCRegClass(IntCCRegClassID)); |
| 44 | MachineRegClassArr.push_back(new SparcV9FloatCCRegClass(FloatCCRegClassID)); |
| 45 | MachineRegClassArr.push_back(new SparcV9SpecialRegClass(SpecialRegClassID)); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 46 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 47 | assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 && |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 48 | "32 Float regs are used for float arg passing"); |
| 49 | } |
| 50 | |
| 51 | |
Vikram S. Adve | f1c15ee | 2002-03-18 03:12:16 +0000 | [diff] [blame] | 52 | // getZeroRegNum - returns the register that contains always zero. |
| 53 | // this is the unified register number |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 54 | // |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 55 | unsigned SparcV9RegInfo::getZeroRegNum() const { |
| 56 | return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, |
| 57 | SparcV9IntRegClass::g0); |
Vikram S. Adve | f1c15ee | 2002-03-18 03:12:16 +0000 | [diff] [blame] | 58 | } |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 59 | |
| 60 | // getCallAddressReg - returns the reg used for pushing the address when a |
| 61 | // method is called. This can be used for other purposes between calls |
| 62 | // |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 63 | unsigned SparcV9RegInfo::getCallAddressReg() const { |
| 64 | return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, |
| 65 | SparcV9IntRegClass::o7); |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | // Returns the register containing the return address. |
| 69 | // It should be made sure that this register contains the return |
| 70 | // value when a return instruction is reached. |
| 71 | // |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 72 | unsigned SparcV9RegInfo::getReturnAddressReg() const { |
| 73 | return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, |
| 74 | SparcV9IntRegClass::i7); |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | // Register get name implementations... |
| 78 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 79 | // Int register names in same order as enum in class SparcV9IntRegClass |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 80 | static const char * const IntRegNames[] = { |
| 81 | "o0", "o1", "o2", "o3", "o4", "o5", "o7", |
| 82 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
| 83 | "i0", "i1", "i2", "i3", "i4", "i5", |
| 84 | "i6", "i7", |
| 85 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
| 86 | "o6" |
| 87 | }; |
| 88 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 89 | const char * const SparcV9IntRegClass::getRegName(unsigned reg) const { |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 90 | assert(reg < NumOfAllRegs); |
| 91 | return IntRegNames[reg]; |
| 92 | } |
| 93 | |
| 94 | static const char * const FloatRegNames[] = { |
| 95 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", |
| 96 | "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", |
| 97 | "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", |
| 98 | "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
| 99 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", |
| 100 | "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", |
| 101 | "f60", "f61", "f62", "f63" |
| 102 | }; |
| 103 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 104 | const char * const SparcV9FloatRegClass::getRegName(unsigned reg) const { |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 105 | assert (reg < NumOfAllRegs); |
| 106 | return FloatRegNames[reg]; |
| 107 | } |
| 108 | |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 109 | static const char * const IntCCRegNames[] = { |
Vikram S. Adve | 786833a | 2003-07-06 20:13:59 +0000 | [diff] [blame] | 110 | "xcc", "icc", "ccr" |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 111 | }; |
| 112 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 113 | const char * const SparcV9IntCCRegClass::getRegName(unsigned reg) const { |
Vikram S. Adve | 786833a | 2003-07-06 20:13:59 +0000 | [diff] [blame] | 114 | assert(reg < 3); |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 115 | return IntCCRegNames[reg]; |
| 116 | } |
| 117 | |
| 118 | static const char * const FloatCCRegNames[] = { |
| 119 | "fcc0", "fcc1", "fcc2", "fcc3" |
| 120 | }; |
| 121 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 122 | const char * const SparcV9FloatCCRegClass::getRegName(unsigned reg) const { |
Brian Gaeke | 03b562a | 2004-04-19 18:53:43 +0000 | [diff] [blame] | 123 | assert (reg < 4); |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 124 | return FloatCCRegNames[reg]; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 125 | } |
| 126 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 127 | static const char * const SpecialRegNames[] = { |
| 128 | "fsr" |
| 129 | }; |
| 130 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 131 | const char * const SparcV9SpecialRegClass::getRegName(unsigned reg) const { |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 132 | assert (reg < 1); |
| 133 | return SpecialRegNames[reg]; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 134 | } |
| 135 | |
Vikram S. Adve | f1c15ee | 2002-03-18 03:12:16 +0000 | [diff] [blame] | 136 | // Get unified reg number for frame pointer |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 137 | unsigned SparcV9RegInfo::getFramePointer() const { |
| 138 | return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, |
| 139 | SparcV9IntRegClass::i6); |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 140 | } |
| 141 | |
Vikram S. Adve | f1c15ee | 2002-03-18 03:12:16 +0000 | [diff] [blame] | 142 | // Get unified reg number for stack pointer |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 143 | unsigned SparcV9RegInfo::getStackPointer() const { |
| 144 | return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, |
| 145 | SparcV9IntRegClass::o6); |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 149 | //--------------------------------------------------------------------------- |
| 150 | // Finds whether a call is an indirect call |
| 151 | //--------------------------------------------------------------------------- |
| 152 | |
| 153 | inline bool |
| 154 | isVarArgsFunction(const Type *funcType) { |
| 155 | return cast<FunctionType>(cast<PointerType>(funcType) |
| 156 | ->getElementType())->isVarArg(); |
| 157 | } |
| 158 | |
| 159 | inline bool |
| 160 | isVarArgsCall(const MachineInstr *CallMI) { |
| 161 | Value* callee = CallMI->getOperand(0).getVRegValue(); |
| 162 | // const Type* funcType = isa<Function>(callee)? callee->getType() |
| 163 | // : cast<PointerType>(callee->getType())->getElementType(); |
| 164 | const Type* funcType = callee->getType(); |
| 165 | return isVarArgsFunction(funcType); |
| 166 | } |
| 167 | |
| 168 | |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 169 | // Get the register number for the specified argument #argNo, |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 170 | // |
| 171 | // Return value: |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 172 | // getInvalidRegNum(), if there is no int register available for the arg. |
| 173 | // regNum, otherwise (this is NOT the unified reg. num). |
| 174 | // regClassId is set to the register class ID. |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 175 | // |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 176 | int |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 177 | SparcV9RegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 178 | unsigned argNo, unsigned& regClassId) const |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 179 | { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 180 | regClassId = IntRegClassID; |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 181 | if (argNo >= NumOfIntArgRegs) |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 182 | return getInvalidRegNum(); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 183 | else |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 184 | return argNo + (inCallee? SparcV9IntRegClass::i0 : SparcV9IntRegClass::o0); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 185 | } |
| 186 | |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 187 | // Get the register number for the specified FP argument #argNo, |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 188 | // Use INT regs for FP args if this is a varargs call. |
| 189 | // |
| 190 | // Return value: |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 191 | // getInvalidRegNum(), if there is no int register available for the arg. |
| 192 | // regNum, otherwise (this is NOT the unified reg. num). |
| 193 | // regClassId is set to the register class ID. |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 194 | // |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 195 | int |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 196 | SparcV9RegInfo::regNumForFPArg(unsigned regType, |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 197 | bool inCallee, bool isVarArgsCall, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 198 | unsigned argNo, unsigned& regClassId) const |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 199 | { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 200 | if (isVarArgsCall) |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 201 | return regNumForIntArg(inCallee, isVarArgsCall, argNo, regClassId); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 202 | else |
| 203 | { |
| 204 | regClassId = FloatRegClassID; |
| 205 | if (regType == FPSingleRegType) |
| 206 | return (argNo*2+1 >= NumOfFloatArgRegs)? |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 207 | getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2 + 1); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 208 | else if (regType == FPDoubleRegType) |
| 209 | return (argNo*2 >= NumOfFloatArgRegs)? |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 210 | getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 211 | else |
| 212 | assert(0 && "Illegal FP register type"); |
Chris Lattner | b82d97e | 2002-07-25 06:08:32 +0000 | [diff] [blame] | 213 | return 0; |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 214 | } |
Vikram S. Adve | a44c6c0 | 2002-03-31 19:04:50 +0000 | [diff] [blame] | 215 | } |
| 216 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 217 | |
| 218 | //--------------------------------------------------------------------------- |
| 219 | // Finds the return address of a call sparc specific call instruction |
| 220 | //--------------------------------------------------------------------------- |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 221 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 222 | // The following 4 methods are used to find the RegType (SparcV9Internals.h) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 223 | // of a LiveRange, a Value, and for a given register unified reg number. |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 224 | // |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 225 | int SparcV9RegInfo::getRegTypeForClassAndType(unsigned regClassID, |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 226 | const Type* type) const |
| 227 | { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 228 | switch (regClassID) { |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 229 | case IntRegClassID: return IntRegType; |
| 230 | case FloatRegClassID: |
| 231 | if (type == Type::FloatTy) return FPSingleRegType; |
| 232 | else if (type == Type::DoubleTy) return FPDoubleRegType; |
| 233 | assert(0 && "Unknown type in FloatRegClass"); return 0; |
| 234 | case IntCCRegClassID: return IntCCRegType; |
| 235 | case FloatCCRegClassID: return FloatCCRegType; |
| 236 | case SpecialRegClassID: return SpecialRegType; |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 237 | default: assert( 0 && "Unknown reg class ID"); return 0; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 238 | } |
| 239 | } |
| 240 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 241 | int SparcV9RegInfo::getRegTypeForDataType(const Type* type) const |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 242 | { |
| 243 | return getRegTypeForClassAndType(getRegClassIDOfType(type), type); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 244 | } |
| 245 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 246 | int SparcV9RegInfo::getRegTypeForLR(const LiveRange *LR) const |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 247 | { |
| 248 | return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType()); |
| 249 | } |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 250 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 251 | int SparcV9RegInfo::getRegType(int unifiedRegNum) const |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 252 | { |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 253 | if (unifiedRegNum < 32) |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 254 | return IntRegType; |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 255 | else if (unifiedRegNum < (32 + 32)) |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 256 | return FPSingleRegType; |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 257 | else if (unifiedRegNum < (64 + 32)) |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 258 | return FPDoubleRegType; |
Brian Gaeke | 6896a7d | 2004-04-21 17:53:58 +0000 | [diff] [blame^] | 259 | else if (unifiedRegNum < (64+32+3)) |
| 260 | return IntCCRegType; |
| 261 | else if (unifiedRegNum < (64+32+3+4)) |
| 262 | return FloatCCRegType; |
| 263 | else if (unifiedRegNum < (64+32+3+4+1)) |
Brian Gaeke | 3f083d5 | 2004-04-20 20:12:57 +0000 | [diff] [blame] | 264 | return SpecialRegType; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 265 | else |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 266 | assert(0 && "Invalid unified register number in getRegType"); |
Chris Lattner | 49b8a9c | 2002-02-24 23:02:40 +0000 | [diff] [blame] | 267 | return 0; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 268 | } |
| 269 | |
| 270 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 271 | // To find the register class used for a specified Type |
| 272 | // |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 273 | unsigned SparcV9RegInfo::getRegClassIDOfType(const Type *type, |
Chris Lattner | b82d97e | 2002-07-25 06:08:32 +0000 | [diff] [blame] | 274 | bool isCCReg) const { |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 275 | Type::PrimitiveID ty = type->getPrimitiveID(); |
| 276 | unsigned res; |
| 277 | |
| 278 | // FIXME: Comparing types like this isn't very safe... |
| 279 | if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) || |
| 280 | (ty == Type::FunctionTyID) || (ty == Type::PointerTyID) ) |
| 281 | res = IntRegClassID; // sparc int reg (ty=0: void) |
| 282 | else if (ty <= Type::DoubleTyID) |
| 283 | res = FloatRegClassID; // sparc float reg class |
| 284 | else { |
| 285 | //std::cerr << "TypeID: " << ty << "\n"; |
| 286 | assert(0 && "Cannot resolve register class for type"); |
| 287 | return 0; |
| 288 | } |
| 289 | |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 290 | if (isCCReg) |
| 291 | return res + 2; // corresponding condition code register |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 292 | else |
| 293 | return res; |
| 294 | } |
| 295 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 296 | unsigned SparcV9RegInfo::getRegClassIDOfRegType(int regType) const { |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 297 | switch(regType) { |
| 298 | case IntRegType: return IntRegClassID; |
| 299 | case FPSingleRegType: |
| 300 | case FPDoubleRegType: return FloatRegClassID; |
| 301 | case IntCCRegType: return IntCCRegClassID; |
| 302 | case FloatCCRegType: return FloatCCRegClassID; |
Brian Gaeke | 6896a7d | 2004-04-21 17:53:58 +0000 | [diff] [blame^] | 303 | case SpecialRegType: return SpecialRegClassID; |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 304 | default: |
| 305 | assert(0 && "Invalid register type in getRegClassIDOfRegType"); |
| 306 | return 0; |
| 307 | } |
| 308 | } |
| 309 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 310 | //--------------------------------------------------------------------------- |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 311 | // Suggests a register for the ret address in the RET machine instruction. |
| 312 | // We always suggest %i7 by convention. |
| 313 | //--------------------------------------------------------------------------- |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 314 | void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI, |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 315 | LiveRangeInfo& LRI) const { |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 316 | |
Brian Gaeke | 12c1d2c | 2004-02-11 20:47:34 +0000 | [diff] [blame] | 317 | assert(target.getInstrInfo().isReturn(RetMI->getOpcode())); |
Vikram S. Adve | 53fec86 | 2001-10-22 13:41:12 +0000 | [diff] [blame] | 318 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 319 | // return address is always mapped to i7 so set it immediately |
| 320 | RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID, |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 321 | SparcV9IntRegClass::i7)); |
Vikram S. Adve | 53fec86 | 2001-10-22 13:41:12 +0000 | [diff] [blame] | 322 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 323 | // Possible Optimization: |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 324 | // Instead of setting the color, we can suggest one. In that case, |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 325 | // we have to test later whether it received the suggested color. |
| 326 | // In that case, a LR has to be created at the start of method. |
| 327 | // It has to be done as follows (remove the setRegVal above): |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 328 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 329 | // MachineOperand & MO = RetMI->getOperand(0); |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 330 | // const Value *RetAddrVal = MO.getVRegValue(); |
| 331 | // assert( RetAddrVal && "LR for ret address must be created at start"); |
| 332 | // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal); |
| 333 | // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID, |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 334 | // SparcV9IntRegOrdr::i7) ); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | |
| 338 | //--------------------------------------------------------------------------- |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 339 | // Suggests a register for the ret address in the JMPL/CALL machine instr. |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 340 | // SparcV9 ABI dictates that %o7 be used for this purpose. |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 341 | //--------------------------------------------------------------------------- |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 342 | void |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 343 | SparcV9RegInfo::suggestReg4CallAddr(MachineInstr * CallMI, |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 344 | LiveRangeInfo& LRI) const |
| 345 | { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 346 | CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); |
| 347 | const Value *RetAddrVal = argDesc->getReturnAddrReg(); |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 348 | assert(RetAddrVal && "INTERNAL ERROR: Return address value is required"); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 349 | |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 350 | // A LR must already exist for the return address. |
| 351 | LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal); |
| 352 | assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!"); |
| 353 | |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 354 | unsigned RegClassID = RetAddrLR->getRegClassID(); |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 355 | RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcV9IntRegClass::o7)); |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 356 | } |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 357 | |
| 358 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 359 | |
| 360 | //--------------------------------------------------------------------------- |
| 361 | // This method will suggest colors to incoming args to a method. |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 362 | // According to the SparcV9 ABI, the first 6 incoming args are in |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 363 | // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float). |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 364 | // If the arg is passed on stack due to the lack of regs, NOTHING will be |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 365 | // done - it will be colored (or spilled) as a normal live range. |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 366 | //--------------------------------------------------------------------------- |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 367 | void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth, |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 368 | LiveRangeInfo& LRI) const |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 369 | { |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 370 | // Check if this is a varArgs function. needed for choosing regs. |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 371 | bool isVarArgs = isVarArgsFunction(Meth->getType()); |
| 372 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 373 | // Count the arguments, *ignoring* whether they are int or FP args. |
| 374 | // Use this common arg numbering to pick the right int or fp register. |
| 375 | unsigned argNo=0; |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 376 | for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend(); |
| 377 | I != E; ++I, ++argNo) { |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 378 | LiveRange *LR = LRI.getLiveRangeForValue(I); |
| 379 | assert(LR && "No live range found for method arg"); |
| 380 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 381 | unsigned regType = getRegTypeForLR(LR); |
| 382 | unsigned regClassIDOfArgReg = BadRegClass; // for chosen reg (unused) |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 383 | |
| 384 | int regNum = (regType == IntRegType) |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 385 | ? regNumForIntArg(/*inCallee*/ true, isVarArgs, argNo, regClassIDOfArgReg) |
| 386 | : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, argNo, |
| 387 | regClassIDOfArgReg); |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 388 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 389 | if (regNum != getInvalidRegNum()) |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 390 | LR->setSuggestedColor(regNum); |
| 391 | } |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 392 | } |
| 393 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 394 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 395 | //--------------------------------------------------------------------------- |
| 396 | // This method is called after graph coloring to move incoming args to |
| 397 | // the correct hardware registers if they did not receive the correct |
| 398 | // (suggested) color through graph coloring. |
| 399 | //--------------------------------------------------------------------------- |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 400 | void SparcV9RegInfo::colorMethodArgs(const Function *Meth, |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 401 | LiveRangeInfo &LRI, |
| 402 | std::vector<MachineInstr*>& InstrnsBefore, |
| 403 | std::vector<MachineInstr*>& InstrnsAfter) const { |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 404 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 405 | // check if this is a varArgs function. needed for choosing regs. |
| 406 | bool isVarArgs = isVarArgsFunction(Meth->getType()); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 407 | MachineInstr *AdMI; |
| 408 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 409 | // for each argument |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 410 | // for each argument. count INT and FP arguments separately. |
| 411 | unsigned argNo=0, intArgNo=0, fpArgNo=0; |
| 412 | for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend(); |
| 413 | I != E; ++I, ++argNo) { |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 414 | // get the LR of arg |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 415 | LiveRange *LR = LRI.getLiveRangeForValue(I); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 416 | assert( LR && "No live range found for method arg"); |
| 417 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 418 | unsigned regType = getRegTypeForLR(LR); |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 419 | unsigned RegClassID = LR->getRegClassID(); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 420 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 421 | // Find whether this argument is coming in a register (if not, on stack) |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 422 | // Also find the correct register the argument must use (UniArgReg) |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 423 | // |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 424 | bool isArgInReg = false; |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 425 | unsigned UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with |
Chris Lattner | 92ba2aa | 2003-01-14 23:05:08 +0000 | [diff] [blame] | 426 | unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 427 | |
| 428 | int regNum = (regType == IntRegType) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 429 | ? regNumForIntArg(/*inCallee*/ true, isVarArgs, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 430 | argNo, regClassIDOfArgReg) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 431 | : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 432 | argNo, regClassIDOfArgReg); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 433 | |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 434 | if(regNum != getInvalidRegNum()) { |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 435 | isArgInReg = true; |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 436 | UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 437 | } |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 438 | |
Vikram S. Adve | b15f8d4 | 2003-07-10 19:42:11 +0000 | [diff] [blame] | 439 | if( ! LR->isMarkedForSpill() ) { // if this arg received a register |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 440 | |
Ruchira Sasanka | c74a720 | 2001-10-24 15:56:58 +0000 | [diff] [blame] | 441 | unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() ); |
| 442 | |
| 443 | // if LR received the correct color, nothing to do |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 444 | // |
Ruchira Sasanka | c74a720 | 2001-10-24 15:56:58 +0000 | [diff] [blame] | 445 | if( UniLRReg == UniArgReg ) |
| 446 | continue; |
| 447 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 448 | // We are here because the LR did not receive the suggested |
| 449 | // but LR received another register. |
| 450 | // Now we have to copy the %i reg (or stack pos of arg) |
| 451 | // to the register the LR was colored with. |
Ruchira Sasanka | c74a720 | 2001-10-24 15:56:58 +0000 | [diff] [blame] | 452 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 453 | // if the arg is coming in UniArgReg register, it MUST go into |
Ruchira Sasanka | c74a720 | 2001-10-24 15:56:58 +0000 | [diff] [blame] | 454 | // the UniLRReg register |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 455 | // |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 456 | if( isArgInReg ) { |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 457 | if( regClassIDOfArgReg != RegClassID ) { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 458 | assert(0 && "This could should work but it is not tested yet"); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 459 | |
| 460 | // It is a variable argument call: the float reg must go in a %o reg. |
| 461 | // We have to move an int reg to a float reg via memory. |
| 462 | // |
| 463 | assert(isVarArgs && |
| 464 | RegClassID == FloatRegClassID && |
| 465 | regClassIDOfArgReg == IntRegClassID && |
| 466 | "This should only be an Int register for an FP argument"); |
| 467 | |
Chris Lattner | 1b849be | 2002-12-28 20:21:29 +0000 | [diff] [blame] | 468 | int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue( |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 469 | getSpilledRegSize(regType)); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 470 | cpReg2MemMI(InstrnsBefore, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 471 | UniArgReg, getFramePointer(), TmpOff, IntRegType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 472 | |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 473 | cpMem2RegMI(InstrnsBefore, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 474 | getFramePointer(), TmpOff, UniLRReg, regType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 475 | } |
| 476 | else { |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 477 | cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 478 | } |
| 479 | } |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 480 | else { |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 481 | |
Misha Brukman | cf00c4a | 2003-10-10 17:57:28 +0000 | [diff] [blame] | 482 | // Now the arg is coming on stack. Since the LR received a register, |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 483 | // we just have to load the arg on stack into that register |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 484 | // |
Chris Lattner | 1b849be | 2002-12-28 20:21:29 +0000 | [diff] [blame] | 485 | const TargetFrameInfo& frameInfo = target.getFrameInfo(); |
Vikram S. Adve | 1c0fba6 | 2001-11-08 04:56:41 +0000 | [diff] [blame] | 486 | int offsetFromFP = |
Misha Brukman | fce1143 | 2002-10-28 00:28:31 +0000 | [diff] [blame] | 487 | frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 488 | argNo); |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 489 | |
| 490 | // float arguments on stack are right justified so adjust the offset! |
| 491 | // int arguments are also right justified but they are always loaded as |
| 492 | // a full double-word so the offset does not need to be adjusted. |
| 493 | if (regType == FPSingleRegType) { |
| 494 | unsigned argSize = target.getTargetData().getTypeSize(LR->getType()); |
| 495 | unsigned slotSize = frameInfo.getSizeOfEachArgOnStack(); |
| 496 | assert(argSize <= slotSize && "Insufficient slot size!"); |
| 497 | offsetFromFP += slotSize - argSize; |
| 498 | } |
| 499 | |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 500 | cpMem2RegMI(InstrnsBefore, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 501 | getFramePointer(), offsetFromFP, UniLRReg, regType); |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 502 | } |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 503 | |
| 504 | } // if LR received a color |
| 505 | |
| 506 | else { |
| 507 | |
| 508 | // Now, the LR did not receive a color. But it has a stack offset for |
| 509 | // spilling. |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 510 | // So, if the arg is coming in UniArgReg register, we can just move |
| 511 | // that on to the stack pos of LR |
| 512 | |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 513 | if( isArgInReg ) { |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 514 | |
| 515 | if( regClassIDOfArgReg != RegClassID ) { |
| 516 | assert(0 && |
| 517 | "FP arguments to a varargs function should be explicitly " |
| 518 | "copied to/from int registers by instruction selection!"); |
| 519 | |
| 520 | // It must be a float arg for a variable argument call, which |
| 521 | // must come in a %o reg. Move the int reg to the stack. |
| 522 | // |
| 523 | assert(isVarArgs && regClassIDOfArgReg == IntRegClassID && |
| 524 | "This should only be an Int register for an FP argument"); |
| 525 | |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 526 | cpReg2MemMI(InstrnsBefore, UniArgReg, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 527 | getFramePointer(), LR->getSpillOffFromFP(), IntRegType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 528 | } |
| 529 | else { |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 530 | cpReg2MemMI(InstrnsBefore, UniArgReg, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 531 | getFramePointer(), LR->getSpillOffFromFP(), regType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 532 | } |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 533 | } |
| 534 | |
| 535 | else { |
| 536 | |
| 537 | // Now the arg is coming on stack. Since the LR did NOT |
Misha Brukman | cf00c4a | 2003-10-10 17:57:28 +0000 | [diff] [blame] | 538 | // received a register as well, it is allocated a stack position. We |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 539 | // can simply change the stack position of the LR. We can do this, |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 540 | // since this method is called before any other method that makes |
| 541 | // uses of the stack pos of the LR (e.g., updateMachineInstr) |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 542 | // |
Chris Lattner | 1b849be | 2002-12-28 20:21:29 +0000 | [diff] [blame] | 543 | const TargetFrameInfo& frameInfo = target.getFrameInfo(); |
Vikram S. Adve | 1c0fba6 | 2001-11-08 04:56:41 +0000 | [diff] [blame] | 544 | int offsetFromFP = |
Misha Brukman | fce1143 | 2002-10-28 00:28:31 +0000 | [diff] [blame] | 545 | frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 546 | argNo); |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 547 | |
| 548 | // FP arguments on stack are right justified so adjust offset! |
| 549 | // int arguments are also right justified but they are always loaded as |
| 550 | // a full double-word so the offset does not need to be adjusted. |
| 551 | if (regType == FPSingleRegType) { |
| 552 | unsigned argSize = target.getTargetData().getTypeSize(LR->getType()); |
| 553 | unsigned slotSize = frameInfo.getSizeOfEachArgOnStack(); |
| 554 | assert(argSize <= slotSize && "Insufficient slot size!"); |
| 555 | offsetFromFP += slotSize - argSize; |
| 556 | } |
Vikram S. Adve | 1c0fba6 | 2001-11-08 04:56:41 +0000 | [diff] [blame] | 557 | |
| 558 | LR->modifySpillOffFromFP( offsetFromFP ); |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 559 | } |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 560 | |
| 561 | } |
| 562 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 563 | } // for each incoming argument |
| 564 | |
| 565 | } |
| 566 | |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 567 | |
| 568 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 569 | //--------------------------------------------------------------------------- |
| 570 | // This method is called before graph coloring to suggest colors to the |
| 571 | // outgoing call args and the return value of the call. |
| 572 | //--------------------------------------------------------------------------- |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 573 | void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI, |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 574 | LiveRangeInfo& LRI) const { |
Brian Gaeke | 12c1d2c | 2004-02-11 20:47:34 +0000 | [diff] [blame] | 575 | assert ( (target.getInstrInfo()).isCall(CallMI->getOpcode()) ); |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 576 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 577 | CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 578 | |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 579 | suggestReg4CallAddr(CallMI, LRI); |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 580 | |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 581 | // First color the return value of the call instruction, if any. |
| 582 | // The return value will be in %o0 if the value is an integer type, |
| 583 | // or in %f0 if the value is a float type. |
| 584 | // |
| 585 | if (const Value *RetVal = argDesc->getReturnValue()) { |
| 586 | LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal); |
| 587 | assert(RetValLR && "No LR for return Value of call!"); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 588 | |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 589 | unsigned RegClassID = RetValLR->getRegClassID(); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 590 | |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 591 | // now suggest a register depending on the register class of ret arg |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 592 | if( RegClassID == IntRegClassID ) |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 593 | RetValLR->setSuggestedColor(SparcV9IntRegClass::o0); |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 594 | else if (RegClassID == FloatRegClassID ) |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 595 | RetValLR->setSuggestedColor(SparcV9FloatRegClass::f0 ); |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 596 | else assert( 0 && "Unknown reg class for return value of call\n"); |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 597 | } |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 598 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 599 | // Now suggest colors for arguments (operands) of the call instruction. |
| 600 | // Colors are suggested only if the arg number is smaller than the |
| 601 | // the number of registers allocated for argument passing. |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 602 | // Now, go thru call args - implicit operands of the call MI |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 603 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 604 | unsigned NumOfCallArgs = argDesc->getNumArgs(); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 605 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 606 | for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0; |
| 607 | i < NumOfCallArgs; ++i, ++argNo) { |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 608 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 609 | const Value *CallArg = argDesc->getArgInfo(i).getArgVal(); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 610 | |
| 611 | // get the LR of call operand (parameter) |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 612 | LiveRange *const LR = LRI.getLiveRangeForValue(CallArg); |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 613 | if (!LR) |
| 614 | continue; // no live ranges for constants and labels |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 615 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 616 | unsigned regType = getRegTypeForLR(LR); |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 617 | unsigned regClassIDOfArgReg = BadRegClass; // chosen reg class (unused) |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 618 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 619 | // Choose a register for this arg depending on whether it is |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 620 | // an INT or FP value. Here we ignore whether or not it is a |
| 621 | // varargs calls, because FP arguments will be explicitly copied |
| 622 | // to an integer Value and handled under (argCopy != NULL) below. |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 623 | int regNum = (regType == IntRegType) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 624 | ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 625 | argNo, regClassIDOfArgReg) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 626 | : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 627 | argNo, regClassIDOfArgReg); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 628 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 629 | // If a register could be allocated, use it. |
| 630 | // If not, do NOTHING as this will be colored as a normal value. |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 631 | if(regNum != getInvalidRegNum()) |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 632 | LR->setSuggestedColor(regNum); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 633 | } // for all call arguments |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 634 | } |
| 635 | |
| 636 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 637 | //--------------------------------------------------------------------------- |
Anand Shukla | 55afc33 | 2003-06-01 02:48:23 +0000 | [diff] [blame] | 638 | // this method is called for an LLVM return instruction to identify which |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 639 | // values will be returned from this method and to suggest colors. |
| 640 | //--------------------------------------------------------------------------- |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 641 | void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI, |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 642 | LiveRangeInfo& LRI) const { |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 643 | |
Brian Gaeke | 12c1d2c | 2004-02-11 20:47:34 +0000 | [diff] [blame] | 644 | assert( (target.getInstrInfo()).isReturn( RetMI->getOpcode() ) ); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 645 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 646 | suggestReg4RetAddr(RetMI, LRI); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 647 | |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 648 | // To find the return value (if any), we can get the LLVM return instr. |
| 649 | // from the return address register, which is the first operand |
| 650 | Value* tmpI = RetMI->getOperand(0).getVRegValue(); |
| 651 | ReturnInst* retI=cast<ReturnInst>(cast<TmpInstruction>(tmpI)->getOperand(0)); |
| 652 | if (const Value *RetVal = retI->getReturnValue()) |
| 653 | if (LiveRange *const LR = LRI.getLiveRangeForValue(RetVal)) |
| 654 | LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 655 | ? (unsigned) SparcV9IntRegClass::i0 |
| 656 | : (unsigned) SparcV9FloatRegClass::f0); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 657 | } |
| 658 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 659 | //--------------------------------------------------------------------------- |
| 660 | // Check if a specified register type needs a scratch register to be |
| 661 | // copied to/from memory. If it does, the reg. type that must be used |
| 662 | // for scratch registers is returned in scratchRegType. |
| 663 | // |
| 664 | // Only the int CC register needs such a scratch register. |
| 665 | // The FP CC registers can (and must) be copied directly to/from memory. |
| 666 | //--------------------------------------------------------------------------- |
| 667 | |
| 668 | bool |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 669 | SparcV9RegInfo::regTypeNeedsScratchReg(int RegType, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 670 | int& scratchRegType) const |
| 671 | { |
| 672 | if (RegType == IntCCRegType) |
| 673 | { |
| 674 | scratchRegType = IntRegType; |
| 675 | return true; |
| 676 | } |
| 677 | return false; |
| 678 | } |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 679 | |
| 680 | //--------------------------------------------------------------------------- |
| 681 | // Copy from a register to register. Register number must be the unified |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 682 | // register number. |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 683 | //--------------------------------------------------------------------------- |
| 684 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 685 | void |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 686 | SparcV9RegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 687 | unsigned SrcReg, |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 688 | unsigned DestReg, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 689 | int RegType) const { |
Misha Brukman | d36e30e | 2003-06-06 09:52:23 +0000 | [diff] [blame] | 690 | assert( ((int)SrcReg != getInvalidRegNum()) && |
| 691 | ((int)DestReg != getInvalidRegNum()) && |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 692 | "Invalid Register"); |
| 693 | |
| 694 | MachineInstr * MI = NULL; |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 695 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 696 | switch( RegType ) { |
| 697 | |
Ruchira Sasanka | 735d6e3 | 2001-10-18 22:38:52 +0000 | [diff] [blame] | 698 | case IntCCRegType: |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 699 | if (getRegType(DestReg) == IntRegType) { |
| 700 | // copy intCC reg to int reg |
Vikram S. Adve | b15f8d4 | 2003-07-10 19:42:11 +0000 | [diff] [blame] | 701 | MI = (BuildMI(V9::RDCCR, 2) |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 702 | .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID, |
| 703 | SparcV9IntCCRegClass::ccr)) |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 704 | .addMReg(DestReg,MachineOperand::Def)); |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 705 | } else { |
| 706 | // copy int reg to intCC reg |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 707 | assert(getRegType(SrcReg) == IntRegType |
| 708 | && "Can only copy CC reg to/from integer reg"); |
Vikram S. Adve | b15f8d4 | 2003-07-10 19:42:11 +0000 | [diff] [blame] | 709 | MI = (BuildMI(V9::WRCCRr, 3) |
| 710 | .addMReg(SrcReg) |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 711 | .addMReg(SparcV9IntRegClass::g0) |
| 712 | .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID, |
| 713 | SparcV9IntCCRegClass::ccr), |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 714 | MachineOperand::Def)); |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 715 | } |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 716 | break; |
| 717 | |
Ruchira Sasanka | 735d6e3 | 2001-10-18 22:38:52 +0000 | [diff] [blame] | 718 | case FloatCCRegType: |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 719 | assert(0 && "Cannot copy FPCC register to any other register"); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 720 | break; |
| 721 | |
| 722 | case IntRegType: |
Misha Brukman | af6f38e | 2003-05-27 22:40:34 +0000 | [diff] [blame] | 723 | MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum()) |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 724 | .addMReg(DestReg, MachineOperand::Def); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 725 | break; |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 726 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 727 | case FPSingleRegType: |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 728 | MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg) |
| 729 | .addMReg(DestReg, MachineOperand::Def); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 730 | break; |
| 731 | |
| 732 | case FPDoubleRegType: |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 733 | MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg) |
| 734 | .addMReg(DestReg, MachineOperand::Def); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 735 | break; |
| 736 | |
| 737 | default: |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 738 | assert(0 && "Unknown RegType"); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 739 | break; |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 740 | } |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 741 | |
| 742 | if (MI) |
| 743 | mvec.push_back(MI); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 744 | } |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 745 | |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 746 | //--------------------------------------------------------------------------- |
Ruchira Sasanka | 7dcd612 | 2001-10-24 22:05:34 +0000 | [diff] [blame] | 747 | // Copy from a register to memory (i.e., Store). Register number must |
| 748 | // be the unified register number |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 749 | //--------------------------------------------------------------------------- |
| 750 | |
| 751 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 752 | void |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 753 | SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 754 | unsigned SrcReg, |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 755 | unsigned PtrReg, |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 756 | int Offset, int RegType, |
Chris Lattner | b82d97e | 2002-07-25 06:08:32 +0000 | [diff] [blame] | 757 | int scratchReg) const { |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 758 | MachineInstr * MI = NULL; |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 759 | int OffReg = -1; |
| 760 | |
| 761 | // If the Offset will not fit in the signed-immediate field, find an |
| 762 | // unused register to hold the offset value. This takes advantage of |
| 763 | // the fact that all the opcodes used below have the same size immed. field. |
| 764 | // Use the register allocator, PRA, to find an unused reg. at this MI. |
| 765 | // |
| 766 | if (RegType != IntCCRegType) // does not use offset below |
| 767 | if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) { |
| 768 | #ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY |
| 769 | RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType)); |
| 770 | OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef); |
| 771 | #else |
Brian Gaeke | 641271d | 2003-11-08 18:12:24 +0000 | [diff] [blame] | 772 | // Default to using register g4 for holding large offsets |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 773 | OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, |
| 774 | SparcV9IntRegClass::g4); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 775 | #endif |
| 776 | assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg."); |
| 777 | mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg)); |
| 778 | } |
| 779 | |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 780 | switch (RegType) { |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 781 | case IntRegType: |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 782 | if (target.getInstrInfo().constantFitsInImmedField(V9::STXi, Offset)) |
| 783 | MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset); |
| 784 | else |
| 785 | MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 786 | break; |
| 787 | |
| 788 | case FPSingleRegType: |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 789 | if (target.getInstrInfo().constantFitsInImmedField(V9::STFi, Offset)) |
| 790 | MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset); |
| 791 | else |
| 792 | MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 793 | break; |
| 794 | |
| 795 | case FPDoubleRegType: |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 796 | if (target.getInstrInfo().constantFitsInImmedField(V9::STDFi, Offset)) |
| 797 | MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset); |
| 798 | else |
| 799 | MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 800 | break; |
| 801 | |
Ruchira Sasanka | 3839e6e | 2001-11-03 19:59:59 +0000 | [diff] [blame] | 802 | case IntCCRegType: |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 803 | assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory"); |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 804 | assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); |
Vikram S. Adve | b15f8d4 | 2003-07-10 19:42:11 +0000 | [diff] [blame] | 805 | MI = (BuildMI(V9::RDCCR, 2) |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 806 | .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID, |
| 807 | SparcV9IntCCRegClass::ccr)) |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 808 | .addMReg(scratchReg, MachineOperand::Def)); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 809 | mvec.push_back(MI); |
| 810 | |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 811 | cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType); |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 812 | return; |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 813 | |
Brian Gaeke | 0eb6103 | 2004-04-19 19:12:12 +0000 | [diff] [blame] | 814 | case SpecialRegType: // used only for %fsr itself. |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 815 | case FloatCCRegType: { |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 816 | unsigned fsrReg = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID, |
| 817 | SparcV9SpecialRegClass::fsr); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 818 | if (target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset)) |
| 819 | MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset); |
| 820 | else |
| 821 | MI=BuildMI(V9::STXFSRr,3).addMReg(fsrReg).addMReg(PtrReg).addMReg(OffReg); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 822 | break; |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 823 | } |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 824 | default: |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 825 | assert(0 && "Unknown RegType in cpReg2MemMI"); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 826 | } |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 827 | mvec.push_back(MI); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 828 | } |
| 829 | |
| 830 | |
| 831 | //--------------------------------------------------------------------------- |
Ruchira Sasanka | 7dcd612 | 2001-10-24 22:05:34 +0000 | [diff] [blame] | 832 | // Copy from memory to a reg (i.e., Load) Register number must be the unified |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 833 | // register number |
| 834 | //--------------------------------------------------------------------------- |
| 835 | |
| 836 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 837 | void |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 838 | SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec, |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 839 | unsigned PtrReg, |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 840 | int Offset, |
| 841 | unsigned DestReg, |
| 842 | int RegType, |
Chris Lattner | b82d97e | 2002-07-25 06:08:32 +0000 | [diff] [blame] | 843 | int scratchReg) const { |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 844 | MachineInstr * MI = NULL; |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 845 | int OffReg = -1; |
| 846 | |
| 847 | // If the Offset will not fit in the signed-immediate field, find an |
| 848 | // unused register to hold the offset value. This takes advantage of |
| 849 | // the fact that all the opcodes used below have the same size immed. field. |
| 850 | // Use the register allocator, PRA, to find an unused reg. at this MI. |
| 851 | // |
| 852 | if (RegType != IntCCRegType) // does not use offset below |
| 853 | if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) { |
| 854 | #ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY |
| 855 | RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType)); |
| 856 | OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef); |
| 857 | #else |
Brian Gaeke | 641271d | 2003-11-08 18:12:24 +0000 | [diff] [blame] | 858 | // Default to using register g4 for holding large offsets |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 859 | OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID, |
| 860 | SparcV9IntRegClass::g4); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 861 | #endif |
| 862 | assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg."); |
| 863 | mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg)); |
| 864 | } |
| 865 | |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 866 | switch (RegType) { |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 867 | case IntRegType: |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 868 | if (target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 869 | MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset) |
| 870 | .addMReg(DestReg, MachineOperand::Def); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 871 | else |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 872 | MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg) |
| 873 | .addMReg(DestReg, MachineOperand::Def); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 874 | break; |
| 875 | |
| 876 | case FPSingleRegType: |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 877 | if (target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset)) |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 878 | MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset) |
| 879 | .addMReg(DestReg, MachineOperand::Def); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 880 | else |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 881 | MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg) |
| 882 | .addMReg(DestReg, MachineOperand::Def); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 883 | break; |
| 884 | |
| 885 | case FPDoubleRegType: |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 886 | if (target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset)) |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 887 | MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset) |
| 888 | .addMReg(DestReg, MachineOperand::Def); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 889 | else |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 890 | MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg) |
| 891 | .addMReg(DestReg, MachineOperand::Def); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 892 | break; |
| 893 | |
Ruchira Sasanka | 3839e6e | 2001-11-03 19:59:59 +0000 | [diff] [blame] | 894 | case IntCCRegType: |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 895 | assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory"); |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 896 | assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 897 | cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType); |
Vikram S. Adve | b15f8d4 | 2003-07-10 19:42:11 +0000 | [diff] [blame] | 898 | MI = (BuildMI(V9::WRCCRr, 3) |
| 899 | .addMReg(scratchReg) |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 900 | .addMReg(SparcV9IntRegClass::g0) |
| 901 | .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID, |
| 902 | SparcV9IntCCRegClass::ccr), MachineOperand::Def)); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 903 | break; |
| 904 | |
Brian Gaeke | 0eb6103 | 2004-04-19 19:12:12 +0000 | [diff] [blame] | 905 | case SpecialRegType: // used only for %fsr itself |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 906 | case FloatCCRegType: { |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 907 | unsigned fsrRegNum = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID, |
| 908 | SparcV9SpecialRegClass::fsr); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 909 | if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset)) |
| 910 | MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset) |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 911 | .addMReg(fsrRegNum, MachineOperand::UseAndDef); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 912 | else |
| 913 | MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg) |
Alkis Evlogimenos | 890f923 | 2004-02-22 19:23:26 +0000 | [diff] [blame] | 914 | .addMReg(fsrRegNum, MachineOperand::UseAndDef); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 915 | break; |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 916 | } |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 917 | default: |
Ruchira Sasanka | ae4bcd7 | 2001-11-10 21:20:43 +0000 | [diff] [blame] | 918 | assert(0 && "Unknown RegType in cpMem2RegMI"); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 919 | } |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 920 | mvec.push_back(MI); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 921 | } |
| 922 | |
| 923 | |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 924 | //--------------------------------------------------------------------------- |
| 925 | // Generate a copy instruction to copy a value to another. Temporarily |
| 926 | // used by PhiElimination code. |
| 927 | //--------------------------------------------------------------------------- |
| 928 | |
| 929 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 930 | void |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 931 | SparcV9RegInfo::cpValue2Value(Value *Src, Value *Dest, |
Misha Brukman | ee563cb | 2003-05-21 17:59:06 +0000 | [diff] [blame] | 932 | std::vector<MachineInstr*>& mvec) const { |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 933 | int RegType = getRegTypeForDataType(Src->getType()); |
Ruchira Sasanka | ef1b0cb | 2001-11-03 17:13:27 +0000 | [diff] [blame] | 934 | MachineInstr * MI = NULL; |
| 935 | |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 936 | switch( RegType ) { |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 937 | case IntRegType: |
Misha Brukman | af6f38e | 2003-05-27 22:40:34 +0000 | [diff] [blame] | 938 | MI = BuildMI(V9::ADDr, 3).addReg(Src).addMReg(getZeroRegNum()) |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 939 | .addRegDef(Dest); |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 940 | break; |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 941 | case FPSingleRegType: |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 942 | MI = BuildMI(V9::FMOVS, 2).addReg(Src).addRegDef(Dest); |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 943 | break; |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 944 | case FPDoubleRegType: |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 945 | MI = BuildMI(V9::FMOVD, 2).addReg(Src).addRegDef(Dest); |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 946 | break; |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 947 | default: |
| 948 | assert(0 && "Unknow RegType in CpValu2Value"); |
| 949 | } |
Ruchira Sasanka | ef1b0cb | 2001-11-03 17:13:27 +0000 | [diff] [blame] | 950 | |
Chris Lattner | 0fa600d | 2002-10-28 20:10:56 +0000 | [diff] [blame] | 951 | mvec.push_back(MI); |
Ruchira Sasanka | ef1b0cb | 2001-11-03 17:13:27 +0000 | [diff] [blame] | 952 | } |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 953 | |
| 954 | |
| 955 | |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 956 | //--------------------------------------------------------------------------- |
| 957 | // Print the register assigned to a LR |
| 958 | //--------------------------------------------------------------------------- |
| 959 | |
Brian Gaeke | e3d6807 | 2004-02-25 18:44:15 +0000 | [diff] [blame] | 960 | void SparcV9RegInfo::printReg(const LiveRange *LR) const { |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 961 | unsigned RegClassID = LR->getRegClassID(); |
Chris Lattner | fdba393 | 2003-09-01 19:58:02 +0000 | [diff] [blame] | 962 | std::cerr << " Node "; |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 963 | |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 964 | if (!LR->hasColor()) { |
Misha Brukman | ee563cb | 2003-05-21 17:59:06 +0000 | [diff] [blame] | 965 | std::cerr << " - could not find a color\n"; |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 966 | return; |
| 967 | } |
| 968 | |
| 969 | // if a color is found |
| 970 | |
Misha Brukman | ee563cb | 2003-05-21 17:59:06 +0000 | [diff] [blame] | 971 | std::cerr << " colored with color "<< LR->getColor(); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 972 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 973 | unsigned uRegName = getUnifiedRegNum(RegClassID, LR->getColor()); |
| 974 | |
| 975 | std::cerr << "["; |
| 976 | std::cerr<< getUnifiedRegName(uRegName); |
| 977 | if (RegClassID == FloatRegClassID && LR->getType() == Type::DoubleTy) |
| 978 | std::cerr << "+" << getUnifiedRegName(uRegName+1); |
| 979 | std::cerr << "]\n"; |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 980 | } |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 981 | |
| 982 | } // End llvm namespace |