Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1 | //===- README.txt - Notes for improving CellSPU-specific code gen ---------===// |
| 2 | |
Scott Michel | f9105d3 | 2007-12-03 23:09:49 +0000 | [diff] [blame] | 3 | This code was contributed by a team from the Computer Systems Research |
| 4 | Department in The Aerospace Corporation: |
| 5 | |
| 6 | - Scott Michel (head bottle washer and much of the non-floating point |
| 7 | instructions) |
| 8 | - Mark Thomas (floating point instructions) |
| 9 | - Michael AuYeung (intrinsics) |
| 10 | - Chandler Carruth (LLVM expertise) |
Scott Michel | 8c67fa4 | 2009-01-21 04:58:48 +0000 | [diff] [blame] | 11 | - Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise) |
Scott Michel | f9105d3 | 2007-12-03 23:09:49 +0000 | [diff] [blame] | 12 | |
| 13 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 14 | IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 15 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR |
| 16 | OTHERWISE. IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES |
| 17 | OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING |
| 18 | OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT |
| 19 | LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR |
| 20 | REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL, |
| 21 | OR PUNITIVE DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR |
Misha Brukman | fc18915 | 2008-12-29 20:08:23 +0000 | [diff] [blame] | 22 | SUCH DAMAGES ARE FORESEEABLE. |
Scott Michel | f9105d3 | 2007-12-03 23:09:49 +0000 | [diff] [blame] | 23 | |
| 24 | --------------------------------------------------------------------------- |
Scott Michel | 3c8a4b2 | 2007-12-05 02:01:41 +0000 | [diff] [blame] | 25 | --WARNING--: |
Scott Michel | f9105d3 | 2007-12-03 23:09:49 +0000 | [diff] [blame] | 26 | --WARNING--: The CellSPU work is work-in-progress and "alpha" quality code. |
Scott Michel | 3c8a4b2 | 2007-12-05 02:01:41 +0000 | [diff] [blame] | 27 | --WARNING--: |
| 28 | |
| 29 | If you are brave enough to try this code or help to hack on it, be sure |
| 30 | to add 'spu' to configure's --enable-targets option, e.g.: |
| 31 | |
Scott Michel | 5a6f17b | 2008-01-30 02:55:46 +0000 | [diff] [blame] | 32 | ./configure <your_configure_flags_here> \ |
| 33 | --enable-targets=x86,x86_64,powerpc,spu |
Scott Michel | 3c8a4b2 | 2007-12-05 02:01:41 +0000 | [diff] [blame] | 34 | |
Scott Michel | f9105d3 | 2007-12-03 23:09:49 +0000 | [diff] [blame] | 35 | --------------------------------------------------------------------------- |
| 36 | |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 37 | TODO: |
Scott Michel | a5e7538 | 2009-01-06 03:51:14 +0000 | [diff] [blame] | 38 | * Create a machine pass for performing dual-pipeline scheduling specifically |
Scott Michel | 8c67fa4 | 2009-01-21 04:58:48 +0000 | [diff] [blame] | 39 | for CellSPU, and insert branch prediction instructions as needed. |
Scott Michel | f9105d3 | 2007-12-03 23:09:49 +0000 | [diff] [blame] | 40 | |
Scott Michel | a5e7538 | 2009-01-06 03:51:14 +0000 | [diff] [blame] | 41 | * i32 instructions: |
| 42 | |
| 43 | * i32 division (work-in-progress) |
| 44 | |
| 45 | * i64 support (see i64operations.c test harness): |
| 46 | |
| 47 | * shifts and comparison operators: done |
| 48 | * sign and zero extension: done |
| 49 | * addition: done |
| 50 | * subtraction: needed |
Scott Michel | 8c67fa4 | 2009-01-21 04:58:48 +0000 | [diff] [blame] | 51 | * multiplication: done |
Scott Michel | a5e7538 | 2009-01-06 03:51:14 +0000 | [diff] [blame] | 52 | |
| 53 | * i128 support: |
| 54 | |
Scott Michel | 8c67fa4 | 2009-01-21 04:58:48 +0000 | [diff] [blame] | 55 | * zero extension, any extension: done |
Scott Michel | a5e7538 | 2009-01-06 03:51:14 +0000 | [diff] [blame] | 56 | * sign extension: needed |
| 57 | * arithmetic operators (add, sub, mul, div): needed |
Scott Michel | 8c67fa4 | 2009-01-21 04:58:48 +0000 | [diff] [blame] | 58 | * logical operations (and, or, shl, srl, sra, xor, nor, nand): needed |
Scott Michel | f9105d3 | 2007-12-03 23:09:49 +0000 | [diff] [blame] | 59 | |
Scott Michel | 8c67fa4 | 2009-01-21 04:58:48 +0000 | [diff] [blame] | 60 | * or: done |
Scott Michel | f9105d3 | 2007-12-03 23:09:49 +0000 | [diff] [blame] | 61 | |
Scott Michel | 8c67fa4 | 2009-01-21 04:58:48 +0000 | [diff] [blame] | 62 | * f64 support |
| 63 | |
| 64 | * Comparison operators: |
| 65 | SETOEQ unimplemented |
| 66 | SETOGT unimplemented |
| 67 | SETOGE unimplemented |
| 68 | SETOLT unimplemented |
| 69 | SETOLE unimplemented |
| 70 | SETONE unimplemented |
| 71 | SETO done (lowered) |
| 72 | SETUO done (lowered) |
| 73 | SETUEQ unimplemented |
| 74 | SETUGT unimplemented |
| 75 | SETUGE unimplemented |
| 76 | SETULT unimplemented |
| 77 | SETULE unimplemented |
| 78 | SETUNE unimplemented |
| 79 | |
| 80 | * LLVM vector suport |
| 81 | |
| 82 | * VSETCC needs to be implemented. It's pretty straightforward to code, but |
| 83 | needs implementation. |
Scott Michel | f9105d3 | 2007-12-03 23:09:49 +0000 | [diff] [blame] | 84 | |
| 85 | * Intrinsics |
| 86 | |
Scott Michel | 8c67fa4 | 2009-01-21 04:58:48 +0000 | [diff] [blame] | 87 | * spu.h instrinsics added but not tested. Need to have an operational |
| 88 | llvm-spu-gcc in order to write a unit test harness. |
Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 89 | |
| 90 | ===-------------------------------------------------------------------------=== |