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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.h - Virtual Register Map -*- C++ -*--------===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00007//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements a virtual register map. This maps virtual registers to
11// physical registers and virtual registers to stack slots. It is created and
12// updated by a register allocator and then used by a machine code rewriter that
13// adds spill code and rewrites virtual into physical register references.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000014//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_VIRTREGMAP_H
18#define LLVM_CODEGEN_VIRTREGMAP_H
19
Owen Anderson49c8aa02009-03-13 05:55:11 +000020#include "llvm/CodeGen/MachineFunctionPass.h"
Lang Hames86511252009-09-04 20:41:11 +000021#include "llvm/CodeGen/LiveInterval.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +000022#include "llvm/Target/TargetRegisterInfo.h"
Evan Cheng4cce6b42008-04-11 17:53:36 +000023#include "llvm/ADT/BitVector.h"
Evan Chengc781a242009-05-03 18:32:42 +000024#include "llvm/ADT/DenseMap.h"
Chris Lattner94c002a2007-02-01 05:32:05 +000025#include "llvm/ADT/IndexedMap.h"
Evan Chengd3653122008-02-27 03:04:06 +000026#include "llvm/ADT/SmallPtrSet.h"
Dan Gohmand68a0762009-01-05 17:59:02 +000027#include "llvm/ADT/SmallVector.h"
Alkis Evlogimenos5f375022004-03-01 20:05:10 +000028#include <map>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000029
30namespace llvm {
Evan Chengc781a242009-05-03 18:32:42 +000031 class LiveIntervals;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000032 class MachineInstr;
David Greene7e231462007-08-07 16:34:05 +000033 class MachineFunction;
Evan Cheng90f95f82009-06-14 20:22:55 +000034 class MachineRegisterInfo;
Chris Lattner29268692006-09-05 02:12:02 +000035 class TargetInstrInfo;
Mike Stumpfe095f32009-05-04 18:40:41 +000036 class TargetRegisterInfo;
Daniel Dunbar1cd1d982009-07-24 10:36:58 +000037 class raw_ostream;
Jakob Stoklund Olesenba05c012011-02-18 22:03:18 +000038 class SlotIndexes;
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000039
Owen Anderson49c8aa02009-03-13 05:55:11 +000040 class VirtRegMap : public MachineFunctionPass {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000041 public:
Evan Cheng2638e1a2007-03-20 08:13:50 +000042 enum {
43 NO_PHYS_REG = 0,
Evan Cheng91935142007-04-04 07:40:01 +000044 NO_STACK_SLOT = (1L << 30)-1,
45 MAX_STACK_SLOT = (1L << 18)-1
Evan Cheng2638e1a2007-03-20 08:13:50 +000046 };
47
Chris Lattner35f27052006-05-01 21:16:03 +000048 enum ModRef { isRef = 1, isMod = 2, isModRef = 3 };
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000049 typedef std::multimap<MachineInstr*,
50 std::pair<unsigned, ModRef> > MI2VirtMapTy;
Alkis Evlogimenos5f375022004-03-01 20:05:10 +000051
Chris Lattner8c4d88d2004-09-30 01:54:45 +000052 private:
Evan Cheng90f95f82009-06-14 20:22:55 +000053 MachineRegisterInfo *MRI;
Owen Anderson49c8aa02009-03-13 05:55:11 +000054 const TargetInstrInfo *TII;
Mike Stumpfe095f32009-05-04 18:40:41 +000055 const TargetRegisterInfo *TRI;
Owen Anderson49c8aa02009-03-13 05:55:11 +000056 MachineFunction *MF;
Mike Stumpfe095f32009-05-04 18:40:41 +000057
58 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs;
59
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +000060 /// Virt2PhysMap - This is a virtual to physical register
61 /// mapping. Each virtual register is required to have an entry in
62 /// it; even spilled virtual registers (the register mapped to a
63 /// spilled register is the temporary used to load it from the
64 /// stack).
Chris Lattner94c002a2007-02-01 05:32:05 +000065 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysMap;
Evan Cheng81a03822007-11-17 00:40:40 +000066
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +000067 /// Virt2StackSlotMap - This is virtual register to stack slot
68 /// mapping. Each spilled virtual register has an entry in it
69 /// which corresponds to the stack slot this register is spilled
70 /// at.
Chris Lattner94c002a2007-02-01 05:32:05 +000071 IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
Evan Cheng81a03822007-11-17 00:40:40 +000072
Dan Gohman39e33ac2008-03-12 20:50:04 +000073 /// Virt2ReMatIdMap - This is virtual register to rematerialization id
Evan Cheng81a03822007-11-17 00:40:40 +000074 /// mapping. Each spilled virtual register that should be remat'd has an
75 /// entry in it which corresponds to the remat id.
Evan Cheng549f27d32007-08-13 23:45:17 +000076 IndexedMap<int, VirtReg2IndexFunctor> Virt2ReMatIdMap;
Evan Cheng81a03822007-11-17 00:40:40 +000077
78 /// Virt2SplitMap - This is virtual register to splitted virtual register
79 /// mapping.
80 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap;
81
Evan Chengadf85902007-12-05 09:51:10 +000082 /// Virt2SplitKillMap - This is splitted virtual register to its last use
Evan Chengd120ffd2007-12-05 10:24:35 +000083 /// (kill) index mapping.
Jakob Stoklund Olesen2cfa5b42011-01-09 18:58:33 +000084 IndexedMap<SlotIndex, VirtReg2IndexFunctor> Virt2SplitKillMap;
Evan Chengadf85902007-12-05 09:51:10 +000085
Evan Cheng81a03822007-11-17 00:40:40 +000086 /// ReMatMap - This is virtual register to re-materialized instruction
87 /// mapping. Each virtual register whose definition is going to be
88 /// re-materialized has an entry in it.
89 IndexedMap<MachineInstr*, VirtReg2IndexFunctor> ReMatMap;
90
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +000091 /// MI2VirtMap - This is MachineInstr to virtual register
92 /// mapping. In the case of memory spill code being folded into
93 /// instructions, we need to know which virtual register was
94 /// read/written by this instruction.
Chris Lattner7f690e62004-09-30 02:15:18 +000095 MI2VirtMapTy MI2VirtMap;
Misha Brukmanedf128a2005-04-21 22:36:52 +000096
Evan Cheng81a03822007-11-17 00:40:40 +000097 /// SpillPt2VirtMap - This records the virtual registers which should
98 /// be spilled right after the MachineInstr due to live interval
99 /// splitting.
Evan Chengb50bb8c2007-12-05 08:16:32 +0000100 std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >
101 SpillPt2VirtMap;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000102
Evan Cheng0cbb1162007-11-29 01:06:25 +0000103 /// RestorePt2VirtMap - This records the virtual registers which should
104 /// be restored right before the MachineInstr due to live interval
105 /// splitting.
106 std::map<MachineInstr*, std::vector<unsigned> > RestorePt2VirtMap;
107
Evan Cheng676dd7c2008-03-11 07:19:34 +0000108 /// EmergencySpillMap - This records the physical registers that should
109 /// be spilled / restored around the MachineInstr since the register
110 /// allocator has run out of registers.
111 std::map<MachineInstr*, std::vector<unsigned> > EmergencySpillMap;
112
113 /// EmergencySpillSlots - This records emergency spill slots used to
114 /// spill physical registers when the register allocator runs out of
115 /// registers. Ideally only one stack slot is used per function per
116 /// register class.
117 std::map<const TargetRegisterClass*, int> EmergencySpillSlots;
118
Evan Cheng2638e1a2007-03-20 08:13:50 +0000119 /// ReMatId - Instead of assigning a stack slot to a to be rematerialized
Evan Cheng91935142007-04-04 07:40:01 +0000120 /// virtual register, an unique id is being assigned. This keeps track of
Evan Cheng2638e1a2007-03-20 08:13:50 +0000121 /// the highest id used so far. Note, this starts at (1<<18) to avoid
122 /// conflicts with stack slot numbers.
123 int ReMatId;
124
Evan Chengd3653122008-02-27 03:04:06 +0000125 /// LowSpillSlot, HighSpillSlot - Lowest and highest spill slot indexes.
126 int LowSpillSlot, HighSpillSlot;
127
128 /// SpillSlotToUsesMap - Records uses for each register spill slot.
129 SmallVector<SmallPtrSet<MachineInstr*, 4>, 8> SpillSlotToUsesMap;
130
Evan Cheng4cce6b42008-04-11 17:53:36 +0000131 /// ImplicitDefed - One bit for each virtual register. If set it indicates
132 /// the register is implicitly defined.
133 BitVector ImplicitDefed;
134
Jakob Stoklund Olesenb55e91e2010-11-16 00:41:01 +0000135 /// createSpillSlot - Allocate a spill slot for RC from MFI.
136 unsigned createSpillSlot(const TargetRegisterClass *RC);
137
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000138 VirtRegMap(const VirtRegMap&); // DO NOT IMPLEMENT
139 void operator=(const VirtRegMap&); // DO NOT IMPLEMENT
Alkis Evlogimenos79742872004-02-23 23:47:10 +0000140
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000141 public:
Owen Anderson49c8aa02009-03-13 05:55:11 +0000142 static char ID;
Owen Anderson90c579d2010-08-06 18:33:48 +0000143 VirtRegMap() : MachineFunctionPass(ID), Virt2PhysMap(NO_PHYS_REG),
Owen Anderson49c8aa02009-03-13 05:55:11 +0000144 Virt2StackSlotMap(NO_STACK_SLOT),
145 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0),
Lang Hames233a60e2009-11-03 23:52:08 +0000146 Virt2SplitKillMap(SlotIndex()), ReMatMap(NULL),
Owen Anderson49c8aa02009-03-13 05:55:11 +0000147 ReMatId(MAX_STACK_SLOT+1),
148 LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { }
149 virtual bool runOnMachineFunction(MachineFunction &MF);
150
151 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
152 AU.setPreservesAll();
153 MachineFunctionPass::getAnalysisUsage(AU);
154 }
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000155
Jakob Stoklund Olesenf0179002010-07-26 23:44:11 +0000156 MachineFunction &getMachineFunction() const {
Jakob Stoklund Olesenc9672cb2010-12-10 18:36:02 +0000157 assert(MF && "getMachineFunction called before runOnMachineFunction");
Jakob Stoklund Olesenf0179002010-07-26 23:44:11 +0000158 return *MF;
159 }
160
Jakob Stoklund Olesenc9672cb2010-12-10 18:36:02 +0000161 MachineRegisterInfo &getRegInfo() const { return *MRI; }
162 const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
163
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000164 void grow();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000165
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000166 /// @brief returns true if the specified virtual register is
167 /// mapped to a physical register
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000168 bool hasPhys(unsigned virtReg) const {
169 return getPhys(virtReg) != NO_PHYS_REG;
170 }
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000171
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000172 /// @brief returns the physical register mapped to the specified
173 /// virtual register
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000174 unsigned getPhys(unsigned virtReg) const {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000175 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000176 return Virt2PhysMap[virtReg];
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000177 }
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000178
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000179 /// @brief creates a mapping for the specified virtual register to
180 /// the specified physical register
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000181 void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000182 assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
183 TargetRegisterInfo::isPhysicalRegister(physReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000184 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000185 "attempt to assign physical register to already mapped "
186 "virtual register");
Chris Lattner7f690e62004-09-30 02:15:18 +0000187 Virt2PhysMap[virtReg] = physReg;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000188 }
189
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000190 /// @brief clears the specified virtual register's, physical
191 /// register mapping
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000192 void clearVirt(unsigned virtReg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000193 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000194 assert(Virt2PhysMap[virtReg] != NO_PHYS_REG &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000195 "attempt to clear a not assigned virtual register");
Chris Lattner7f690e62004-09-30 02:15:18 +0000196 Virt2PhysMap[virtReg] = NO_PHYS_REG;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000197 }
198
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000199 /// @brief clears all virtual to physical register mappings
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000200 void clearAllVirt() {
Chris Lattner7f690e62004-09-30 02:15:18 +0000201 Virt2PhysMap.clear();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000202 grow();
203 }
204
Evan Cheng90f95f82009-06-14 20:22:55 +0000205 /// @brief returns the register allocation preference.
206 unsigned getRegAllocPref(unsigned virtReg);
207
Jakob Stoklund Olesen51458ed2011-07-08 20:46:18 +0000208 /// @brief returns true if VirtReg is assigned to its preferred physreg.
209 bool hasPreferredPhys(unsigned VirtReg) {
210 return getPhys(VirtReg) == getRegAllocPref(VirtReg);
211 }
212
Evan Cheng81a03822007-11-17 00:40:40 +0000213 /// @brief records virtReg is a split live interval from SReg.
214 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
215 Virt2SplitMap[virtReg] = SReg;
216 }
217
218 /// @brief returns the live interval virtReg is split from.
Jakob Stoklund Olesene324f6e2011-02-18 22:35:20 +0000219 unsigned getPreSplitReg(unsigned virtReg) const {
Evan Cheng81a03822007-11-17 00:40:40 +0000220 return Virt2SplitMap[virtReg];
221 }
222
Jakob Stoklund Olesenfd389172011-02-19 00:38:43 +0000223 /// getOriginal - Return the original virtual register that VirtReg descends
224 /// from through splitting.
225 /// A register that was not created by splitting is its own original.
226 /// This operation is idempotent.
227 unsigned getOriginal(unsigned VirtReg) const {
228 unsigned Orig = getPreSplitReg(VirtReg);
229 return Orig ? Orig : VirtReg;
230 }
231
Dan Gohman39e33ac2008-03-12 20:50:04 +0000232 /// @brief returns true if the specified virtual register is not
Evan Cheng549f27d32007-08-13 23:45:17 +0000233 /// mapped to a stack slot or rematerialized.
234 bool isAssignedReg(unsigned virtReg) const {
Evan Cheng81a03822007-11-17 00:40:40 +0000235 if (getStackSlot(virtReg) == NO_STACK_SLOT &&
236 getReMatId(virtReg) == NO_STACK_SLOT)
237 return true;
238 // Split register can be assigned a physical register as well as a
239 // stack slot or remat id.
240 return (Virt2SplitMap[virtReg] && Virt2PhysMap[virtReg] != NO_PHYS_REG);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000241 }
242
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000243 /// @brief returns the stack slot mapped to the specified virtual
244 /// register
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000245 int getStackSlot(unsigned virtReg) const {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000246 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000247 return Virt2StackSlotMap[virtReg];
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000248 }
249
Evan Cheng549f27d32007-08-13 23:45:17 +0000250 /// @brief returns the rematerialization id mapped to the specified virtual
251 /// register
252 int getReMatId(unsigned virtReg) const {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000253 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng549f27d32007-08-13 23:45:17 +0000254 return Virt2ReMatIdMap[virtReg];
255 }
256
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000257 /// @brief create a mapping for the specifed virtual register to
258 /// the next available stack slot
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000259 int assignVirt2StackSlot(unsigned virtReg);
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000260 /// @brief create a mapping for the specified virtual register to
261 /// the specified stack slot
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000262 void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
263
Evan Cheng2638e1a2007-03-20 08:13:50 +0000264 /// @brief assign an unique re-materialization id to the specified
265 /// virtual register.
266 int assignVirtReMatId(unsigned virtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000267 /// @brief assign an unique re-materialization id to the specified
268 /// virtual register.
269 void assignVirtReMatId(unsigned virtReg, int id);
Evan Cheng2638e1a2007-03-20 08:13:50 +0000270
271 /// @brief returns true if the specified virtual register is being
272 /// re-materialized.
273 bool isReMaterialized(unsigned virtReg) const {
Evan Cheng549f27d32007-08-13 23:45:17 +0000274 return ReMatMap[virtReg] != NULL;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000275 }
276
277 /// @brief returns the original machine instruction being re-issued
278 /// to re-materialize the specified virtual register.
Evan Cheng549f27d32007-08-13 23:45:17 +0000279 MachineInstr *getReMaterializedMI(unsigned virtReg) const {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000280 return ReMatMap[virtReg];
281 }
282
283 /// @brief records the specified virtual register will be
284 /// re-materialized and the original instruction which will be re-issed
Evan Cheng549f27d32007-08-13 23:45:17 +0000285 /// for this purpose. If parameter all is true, then all uses of the
286 /// registers are rematerialized and it's safe to delete the definition.
Evan Cheng2638e1a2007-03-20 08:13:50 +0000287 void setVirtIsReMaterialized(unsigned virtReg, MachineInstr *def) {
288 ReMatMap[virtReg] = def;
289 }
290
Evan Chengadf85902007-12-05 09:51:10 +0000291 /// @brief record the last use (kill) of a split virtual register.
Lang Hames233a60e2009-11-03 23:52:08 +0000292 void addKillPoint(unsigned virtReg, SlotIndex index) {
Evan Chengd120ffd2007-12-05 10:24:35 +0000293 Virt2SplitKillMap[virtReg] = index;
Evan Chengadf85902007-12-05 09:51:10 +0000294 }
295
Lang Hames233a60e2009-11-03 23:52:08 +0000296 SlotIndex getKillPoint(unsigned virtReg) const {
Evan Chengd120ffd2007-12-05 10:24:35 +0000297 return Virt2SplitKillMap[virtReg];
298 }
299
300 /// @brief remove the last use (kill) of a split virtual register.
Evan Chengadf85902007-12-05 09:51:10 +0000301 void removeKillPoint(unsigned virtReg) {
Lang Hames233a60e2009-11-03 23:52:08 +0000302 Virt2SplitKillMap[virtReg] = SlotIndex();
Evan Chengadf85902007-12-05 09:51:10 +0000303 }
304
Evan Chengcada2452007-11-28 01:28:46 +0000305 /// @brief returns true if the specified MachineInstr is a spill point.
306 bool isSpillPt(MachineInstr *Pt) const {
307 return SpillPt2VirtMap.find(Pt) != SpillPt2VirtMap.end();
308 }
309
Evan Cheng81a03822007-11-17 00:40:40 +0000310 /// @brief returns the virtual registers that should be spilled due to
311 /// splitting right after the specified MachineInstr.
Evan Chengb50bb8c2007-12-05 08:16:32 +0000312 std::vector<std::pair<unsigned,bool> > &getSpillPtSpills(MachineInstr *Pt) {
Evan Cheng81a03822007-11-17 00:40:40 +0000313 return SpillPt2VirtMap[Pt];
314 }
315
316 /// @brief records the specified MachineInstr as a spill point for virtReg.
Evan Chengb50bb8c2007-12-05 08:16:32 +0000317 void addSpillPoint(unsigned virtReg, bool isKill, MachineInstr *Pt) {
Evan Chengc781a242009-05-03 18:32:42 +0000318 std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >::iterator
319 I = SpillPt2VirtMap.find(Pt);
320 if (I != SpillPt2VirtMap.end())
321 I->second.push_back(std::make_pair(virtReg, isKill));
Evan Chengcada2452007-11-28 01:28:46 +0000322 else {
Evan Chengb50bb8c2007-12-05 08:16:32 +0000323 std::vector<std::pair<unsigned,bool> > Virts;
324 Virts.push_back(std::make_pair(virtReg, isKill));
Evan Chengcada2452007-11-28 01:28:46 +0000325 SpillPt2VirtMap.insert(std::make_pair(Pt, Virts));
326 }
Evan Cheng81a03822007-11-17 00:40:40 +0000327 }
328
Evan Chengc1f53c72008-03-11 21:34:46 +0000329 /// @brief - transfer spill point information from one instruction to
330 /// another.
Evan Cheng81a03822007-11-17 00:40:40 +0000331 void transferSpillPts(MachineInstr *Old, MachineInstr *New) {
Evan Chengc781a242009-05-03 18:32:42 +0000332 std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >::iterator
Evan Chengb50bb8c2007-12-05 08:16:32 +0000333 I = SpillPt2VirtMap.find(Old);
Evan Chengcada2452007-11-28 01:28:46 +0000334 if (I == SpillPt2VirtMap.end())
335 return;
336 while (!I->second.empty()) {
Evan Chengb50bb8c2007-12-05 08:16:32 +0000337 unsigned virtReg = I->second.back().first;
338 bool isKill = I->second.back().second;
Evan Chengcada2452007-11-28 01:28:46 +0000339 I->second.pop_back();
Evan Chengb50bb8c2007-12-05 08:16:32 +0000340 addSpillPoint(virtReg, isKill, New);
Evan Cheng81a03822007-11-17 00:40:40 +0000341 }
Evan Chengcada2452007-11-28 01:28:46 +0000342 SpillPt2VirtMap.erase(I);
Evan Cheng81a03822007-11-17 00:40:40 +0000343 }
344
Evan Cheng0cbb1162007-11-29 01:06:25 +0000345 /// @brief returns true if the specified MachineInstr is a restore point.
346 bool isRestorePt(MachineInstr *Pt) const {
347 return RestorePt2VirtMap.find(Pt) != RestorePt2VirtMap.end();
348 }
349
350 /// @brief returns the virtual registers that should be restoreed due to
351 /// splitting right after the specified MachineInstr.
352 std::vector<unsigned> &getRestorePtRestores(MachineInstr *Pt) {
353 return RestorePt2VirtMap[Pt];
354 }
355
356 /// @brief records the specified MachineInstr as a restore point for virtReg.
357 void addRestorePoint(unsigned virtReg, MachineInstr *Pt) {
Evan Chengc781a242009-05-03 18:32:42 +0000358 std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
359 RestorePt2VirtMap.find(Pt);
360 if (I != RestorePt2VirtMap.end())
361 I->second.push_back(virtReg);
Evan Cheng0cbb1162007-11-29 01:06:25 +0000362 else {
363 std::vector<unsigned> Virts;
364 Virts.push_back(virtReg);
365 RestorePt2VirtMap.insert(std::make_pair(Pt, Virts));
366 }
367 }
368
Evan Cheng676dd7c2008-03-11 07:19:34 +0000369 /// @brief - transfer restore point information from one instruction to
370 /// another.
Evan Cheng0cbb1162007-11-29 01:06:25 +0000371 void transferRestorePts(MachineInstr *Old, MachineInstr *New) {
Evan Chengc781a242009-05-03 18:32:42 +0000372 std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
Evan Cheng0cbb1162007-11-29 01:06:25 +0000373 RestorePt2VirtMap.find(Old);
374 if (I == RestorePt2VirtMap.end())
375 return;
376 while (!I->second.empty()) {
377 unsigned virtReg = I->second.back();
378 I->second.pop_back();
379 addRestorePoint(virtReg, New);
380 }
381 RestorePt2VirtMap.erase(I);
382 }
383
Evan Cheng676dd7c2008-03-11 07:19:34 +0000384 /// @brief records that the specified physical register must be spilled
385 /// around the specified machine instr.
386 void addEmergencySpill(unsigned PhysReg, MachineInstr *MI) {
387 if (EmergencySpillMap.find(MI) != EmergencySpillMap.end())
388 EmergencySpillMap[MI].push_back(PhysReg);
389 else {
390 std::vector<unsigned> PhysRegs;
391 PhysRegs.push_back(PhysReg);
392 EmergencySpillMap.insert(std::make_pair(MI, PhysRegs));
393 }
394 }
395
396 /// @brief returns true if one or more physical registers must be spilled
397 /// around the specified instruction.
398 bool hasEmergencySpills(MachineInstr *MI) const {
399 return EmergencySpillMap.find(MI) != EmergencySpillMap.end();
400 }
401
402 /// @brief returns the physical registers to be spilled and restored around
403 /// the instruction.
404 std::vector<unsigned> &getEmergencySpills(MachineInstr *MI) {
405 return EmergencySpillMap[MI];
406 }
407
Evan Chengc1f53c72008-03-11 21:34:46 +0000408 /// @brief - transfer emergency spill information from one instruction to
409 /// another.
410 void transferEmergencySpills(MachineInstr *Old, MachineInstr *New) {
411 std::map<MachineInstr*,std::vector<unsigned> >::iterator I =
412 EmergencySpillMap.find(Old);
413 if (I == EmergencySpillMap.end())
414 return;
415 while (!I->second.empty()) {
416 unsigned virtReg = I->second.back();
417 I->second.pop_back();
418 addEmergencySpill(virtReg, New);
419 }
420 EmergencySpillMap.erase(I);
421 }
422
Evan Cheng676dd7c2008-03-11 07:19:34 +0000423 /// @brief return or get a emergency spill slot for the register class.
424 int getEmergencySpillSlot(const TargetRegisterClass *RC);
425
Evan Chengd3653122008-02-27 03:04:06 +0000426 /// @brief Return lowest spill slot index.
427 int getLowSpillSlot() const {
428 return LowSpillSlot;
429 }
430
431 /// @brief Return highest spill slot index.
432 int getHighSpillSlot() const {
433 return HighSpillSlot;
434 }
435
436 /// @brief Records a spill slot use.
437 void addSpillSlotUse(int FrameIndex, MachineInstr *MI);
438
439 /// @brief Returns true if spill slot has been used.
440 bool isSpillSlotUsed(int FrameIndex) const {
441 assert(FrameIndex >= 0 && "Spill slot index should not be negative!");
442 return !SpillSlotToUsesMap[FrameIndex-LowSpillSlot].empty();
443 }
444
Evan Cheng4cce6b42008-04-11 17:53:36 +0000445 /// @brief Mark the specified register as being implicitly defined.
446 void setIsImplicitlyDefined(unsigned VirtReg) {
Jakob Stoklund Olesenc7d67f92011-01-08 23:11:07 +0000447 ImplicitDefed.set(TargetRegisterInfo::virtReg2Index(VirtReg));
Evan Cheng4cce6b42008-04-11 17:53:36 +0000448 }
449
450 /// @brief Returns true if the virtual register is implicitly defined.
451 bool isImplicitlyDefined(unsigned VirtReg) const {
Jakob Stoklund Olesenc7d67f92011-01-08 23:11:07 +0000452 return ImplicitDefed[TargetRegisterInfo::virtReg2Index(VirtReg)];
Evan Cheng4cce6b42008-04-11 17:53:36 +0000453 }
454
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000455 /// @brief Updates information about the specified virtual register's value
Evan Chengaee4af62007-12-02 08:30:39 +0000456 /// folded into newMI machine instruction.
457 void virtFolded(unsigned VirtReg, MachineInstr *OldMI, MachineInstr *NewMI,
458 ModRef MRInfo);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000459
Evan Cheng7f566252007-10-13 02:50:24 +0000460 /// @brief Updates information about the specified virtual register's value
461 /// folded into the specified machine instruction.
462 void virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo);
463
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000464 /// @brief returns the virtual registers' values folded in memory
465 /// operands of this instruction
Chris Lattner7f690e62004-09-30 02:15:18 +0000466 std::pair<MI2VirtMapTy::const_iterator, MI2VirtMapTy::const_iterator>
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000467 getFoldedVirts(MachineInstr* MI) const {
Chris Lattner7f690e62004-09-30 02:15:18 +0000468 return MI2VirtMap.equal_range(MI);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000469 }
Chris Lattner35f27052006-05-01 21:16:03 +0000470
Evan Chengcada2452007-11-28 01:28:46 +0000471 /// RemoveMachineInstrFromMaps - MI is being erased, remove it from the
472 /// the folded instruction map and spill point map.
Evan Chengd3653122008-02-27 03:04:06 +0000473 void RemoveMachineInstrFromMaps(MachineInstr *MI);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000474
Jakob Stoklund Olesenba05c012011-02-18 22:03:18 +0000475 /// rewrite - Rewrite all instructions in MF to use only physical registers
476 /// by mapping all virtual register operands to their assigned physical
477 /// registers.
478 ///
479 /// @param Indexes Optionally remove deleted instructions from indexes.
480 void rewrite(SlotIndexes *Indexes);
481
Daniel Dunbar1cd1d982009-07-24 10:36:58 +0000482 void print(raw_ostream &OS, const Module* M = 0) const;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000483 void dump() const;
484 };
485
Daniel Dunbar1cd1d982009-07-24 10:36:58 +0000486 inline raw_ostream &operator<<(raw_ostream &OS, const VirtRegMap &VRM) {
487 VRM.print(OS);
488 return OS;
489 }
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000490} // End llvm namespace
491
492#endif