Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 1 | //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines a simple peephole instruction selector for the V8 target |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "SparcV8.h" |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 15 | #include "SparcV8InstrInfo.h" |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 16 | #include "llvm/Instructions.h" |
| 17 | #include "llvm/IntrinsicLowering.h" |
| 18 | #include "llvm/Pass.h" |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 19 | #include "llvm/Constants.h" |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Brian Gaeke | 9df9282 | 2004-06-15 19:16:07 +0000 | [diff] [blame^] | 21 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/MachineFunction.h" |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/SSARegMap.h" |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 24 | #include "llvm/Target/TargetMachine.h" |
| 25 | #include "llvm/Support/GetElementPtrTypeIterator.h" |
| 26 | #include "llvm/Support/InstVisitor.h" |
| 27 | #include "llvm/Support/CFG.h" |
| 28 | using namespace llvm; |
| 29 | |
| 30 | namespace { |
| 31 | struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> { |
| 32 | TargetMachine &TM; |
| 33 | MachineFunction *F; // The function we are compiling into |
| 34 | MachineBasicBlock *BB; // The current MBB we are compiling |
| 35 | |
| 36 | std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs |
| 37 | |
| 38 | // MBBMap - Mapping between LLVM BB -> Machine BB |
| 39 | std::map<const BasicBlock*, MachineBasicBlock*> MBBMap; |
| 40 | |
| 41 | V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {} |
| 42 | |
| 43 | /// runOnFunction - Top level implementation of instruction selection for |
| 44 | /// the entire function. |
| 45 | /// |
| 46 | bool runOnFunction(Function &Fn); |
| 47 | |
| 48 | virtual const char *getPassName() const { |
| 49 | return "SparcV8 Simple Instruction Selection"; |
| 50 | } |
| 51 | |
Brian Gaeke | 532e60c | 2004-05-08 04:21:17 +0000 | [diff] [blame] | 52 | /// emitGEPOperation - Common code shared between visitGetElementPtrInst and |
| 53 | /// constant expression GEP support. |
| 54 | /// |
| 55 | void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP, |
| 56 | Value *Src, User::op_iterator IdxBegin, |
| 57 | User::op_iterator IdxEnd, unsigned TargetReg); |
| 58 | |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 59 | /// visitBasicBlock - This method is called when we are visiting a new basic |
| 60 | /// block. This simply creates a new MachineBasicBlock to emit code into |
| 61 | /// and adds it to the current MachineFunction. Subsequent visit* for |
| 62 | /// instructions will be invoked for all instructions in the basic block. |
| 63 | /// |
| 64 | void visitBasicBlock(BasicBlock &LLVM_BB) { |
| 65 | BB = MBBMap[&LLVM_BB]; |
| 66 | } |
| 67 | |
Chris Lattner | 4be7ca5 | 2004-04-07 04:27:16 +0000 | [diff] [blame] | 68 | void visitBinaryOperator(Instruction &I); |
| 69 | void visitShiftInstruction(Instruction &I) { visitBinaryOperator(I); } |
Chris Lattner | 4d0cda4 | 2004-04-07 05:04:51 +0000 | [diff] [blame] | 70 | void visitSetCondInst(Instruction &I); |
Chris Lattner | 4be7ca5 | 2004-04-07 04:27:16 +0000 | [diff] [blame] | 71 | void visitCallInst(CallInst &I); |
Brian Gaeke | f3334eb | 2004-04-07 17:29:37 +0000 | [diff] [blame] | 72 | void visitReturnInst(ReturnInst &I); |
Brian Gaeke | 532e60c | 2004-05-08 04:21:17 +0000 | [diff] [blame] | 73 | void visitBranchInst(BranchInst &I); |
Brian Gaeke | 3d11e8a | 2004-04-13 18:27:46 +0000 | [diff] [blame] | 74 | void visitCastInst(CastInst &I); |
Brian Gaeke | f3334eb | 2004-04-07 17:29:37 +0000 | [diff] [blame] | 75 | void visitLoadInst(LoadInst &I); |
| 76 | void visitStoreInst(StoreInst &I); |
Brian Gaeke | 532e60c | 2004-05-08 04:21:17 +0000 | [diff] [blame] | 77 | void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass |
| 78 | void visitGetElementPtrInst(GetElementPtrInst &I); |
| 79 | |
| 80 | |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 81 | |
| 82 | void visitInstruction(Instruction &I) { |
| 83 | std::cerr << "Unhandled instruction: " << I; |
| 84 | abort(); |
| 85 | } |
| 86 | |
| 87 | /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the |
| 88 | /// function, lowering any calls to unknown intrinsic functions into the |
| 89 | /// equivalent LLVM code. |
| 90 | void LowerUnknownIntrinsicFunctionCalls(Function &F); |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 91 | void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI); |
| 92 | |
Brian Gaeke | 562cb16 | 2004-04-07 17:04:09 +0000 | [diff] [blame] | 93 | void LoadArgumentsToVirtualRegs(Function *F); |
| 94 | |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 95 | /// copyConstantToRegister - Output the instructions required to put the |
| 96 | /// specified constant into the specified register. |
| 97 | /// |
| 98 | void copyConstantToRegister(MachineBasicBlock *MBB, |
| 99 | MachineBasicBlock::iterator IP, |
| 100 | Constant *C, unsigned R); |
| 101 | |
| 102 | /// makeAnotherReg - This method returns the next register number we haven't |
| 103 | /// yet used. |
| 104 | /// |
| 105 | /// Long values are handled somewhat specially. They are always allocated |
| 106 | /// as pairs of 32 bit integer values. The register number returned is the |
| 107 | /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits |
| 108 | /// of the long value. |
| 109 | /// |
| 110 | unsigned makeAnotherReg(const Type *Ty) { |
| 111 | assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) && |
| 112 | "Current target doesn't have SparcV8 reg info??"); |
| 113 | const SparcV8RegisterInfo *MRI = |
| 114 | static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()); |
| 115 | if (Ty == Type::LongTy || Ty == Type::ULongTy) { |
| 116 | const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy); |
| 117 | // Create the lower part |
| 118 | F->getSSARegMap()->createVirtualRegister(RC); |
| 119 | // Create the upper part. |
| 120 | return F->getSSARegMap()->createVirtualRegister(RC)-1; |
| 121 | } |
| 122 | |
| 123 | // Add the mapping of regnumber => reg class to MachineFunction |
| 124 | const TargetRegisterClass *RC = MRI->getRegClassForType(Ty); |
| 125 | return F->getSSARegMap()->createVirtualRegister(RC); |
| 126 | } |
| 127 | |
| 128 | unsigned getReg(Value &V) { return getReg (&V); } // allow refs. |
| 129 | unsigned getReg(Value *V) { |
| 130 | // Just append to the end of the current bb. |
| 131 | MachineBasicBlock::iterator It = BB->end(); |
| 132 | return getReg(V, BB, It); |
| 133 | } |
| 134 | unsigned getReg(Value *V, MachineBasicBlock *MBB, |
| 135 | MachineBasicBlock::iterator IPt) { |
| 136 | unsigned &Reg = RegMap[V]; |
| 137 | if (Reg == 0) { |
| 138 | Reg = makeAnotherReg(V->getType()); |
| 139 | RegMap[V] = Reg; |
| 140 | } |
| 141 | // If this operand is a constant, emit the code to copy the constant into |
| 142 | // the register here... |
| 143 | // |
| 144 | if (Constant *C = dyn_cast<Constant>(V)) { |
| 145 | copyConstantToRegister(MBB, IPt, C, Reg); |
| 146 | RegMap.erase(V); // Assign a new name to this constant if ref'd again |
| 147 | } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) { |
| 148 | // Move the address of the global into the register |
Brian Gaeke | cf47198 | 2004-03-09 04:49:13 +0000 | [diff] [blame] | 149 | unsigned TmpReg = makeAnotherReg(V->getType()); |
| 150 | BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV); |
| 151 | BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg) |
| 152 | .addGlobalAddress (GV); |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 153 | RegMap.erase(V); // Assign a new name to this address if ref'd again |
| 154 | } |
| 155 | |
| 156 | return Reg; |
| 157 | } |
| 158 | |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 159 | }; |
| 160 | } |
| 161 | |
| 162 | FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) { |
| 163 | return new V8ISel(TM); |
| 164 | } |
| 165 | |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 166 | enum TypeClass { |
Brian Gaeke | f57e364 | 2004-03-16 22:37:11 +0000 | [diff] [blame] | 167 | cByte, cShort, cInt, cLong, cFloat, cDouble |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 168 | }; |
| 169 | |
| 170 | static TypeClass getClass (const Type *T) { |
| 171 | switch (T->getPrimitiveID ()) { |
| 172 | case Type::UByteTyID: case Type::SByteTyID: return cByte; |
| 173 | case Type::UShortTyID: case Type::ShortTyID: return cShort; |
Brian Gaeke | 562cb16 | 2004-04-07 17:04:09 +0000 | [diff] [blame] | 174 | case Type::PointerTyID: |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 175 | case Type::UIntTyID: case Type::IntTyID: return cInt; |
Brian Gaeke | f57e364 | 2004-03-16 22:37:11 +0000 | [diff] [blame] | 176 | case Type::ULongTyID: case Type::LongTyID: return cLong; |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 177 | case Type::FloatTyID: return cFloat; |
| 178 | case Type::DoubleTyID: return cDouble; |
| 179 | default: |
| 180 | assert (0 && "Type of unknown class passed to getClass?"); |
| 181 | return cByte; |
| 182 | } |
| 183 | } |
Chris Lattner | 0d538bb | 2004-04-07 04:36:53 +0000 | [diff] [blame] | 184 | static TypeClass getClassB(const Type *T) { |
| 185 | if (T == Type::BoolTy) return cByte; |
| 186 | return getClass(T); |
| 187 | } |
| 188 | |
| 189 | |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 190 | |
| 191 | /// copyConstantToRegister - Output the instructions required to put the |
| 192 | /// specified constant into the specified register. |
| 193 | /// |
| 194 | void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB, |
| 195 | MachineBasicBlock::iterator IP, |
| 196 | Constant *C, unsigned R) { |
Brian Gaeke | 9df9282 | 2004-06-15 19:16:07 +0000 | [diff] [blame^] | 197 | if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { |
| 198 | switch (CE->getOpcode()) { |
| 199 | case Instruction::GetElementPtr: |
| 200 | emitGEPOperation(MBB, IP, CE->getOperand(0), |
| 201 | CE->op_begin()+1, CE->op_end(), R); |
| 202 | return; |
| 203 | default: |
| 204 | std::cerr << "Copying this constant expr not yet handled: " << *CE; |
| 205 | abort(); |
| 206 | } |
| 207 | } |
| 208 | |
Brian Gaeke | e302a7e | 2004-05-07 21:39:30 +0000 | [diff] [blame] | 209 | if (C->getType()->isIntegral ()) { |
| 210 | uint64_t Val; |
Brian Gaeke | 9df9282 | 2004-06-15 19:16:07 +0000 | [diff] [blame^] | 211 | unsigned Class = getClassB (C->getType ()); |
| 212 | if (Class == cLong) { |
| 213 | unsigned TmpReg = makeAnotherReg (Type::IntTy); |
| 214 | unsigned TmpReg2 = makeAnotherReg (Type::IntTy); |
| 215 | // Copy the value into the register pair. |
| 216 | // R = top(more-significant) half, R+1 = bottom(less-significant) half |
| 217 | uint64_t Val = cast<ConstantInt>(C)->getRawValue(); |
| 218 | unsigned topHalf = Val & 0xffffffffU; |
| 219 | unsigned bottomHalf = Val >> 32; |
| 220 | unsigned HH = topHalf >> 10; |
| 221 | unsigned HM = topHalf & 0x03ff; |
| 222 | unsigned LM = bottomHalf >> 10; |
| 223 | unsigned LO = bottomHalf & 0x03ff; |
| 224 | BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(HH); |
| 225 | BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) |
| 226 | .addImm (HM); |
| 227 | BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg2).addImm(LM); |
| 228 | BuildMI (*MBB, IP, V8::ORri, 2, R+1).addReg (TmpReg2) |
| 229 | .addImm (LO); |
| 230 | return; |
| 231 | } |
| 232 | |
| 233 | assert(Class <= cInt && "Type not handled yet!"); |
| 234 | |
Brian Gaeke | e302a7e | 2004-05-07 21:39:30 +0000 | [diff] [blame] | 235 | if (C->getType() == Type::BoolTy) { |
| 236 | Val = (C == ConstantBool::True); |
| 237 | } else { |
| 238 | ConstantInt *CI = dyn_cast<ConstantInt> (C); |
| 239 | Val = CI->getRawValue (); |
| 240 | } |
Brian Gaeke | 9df9282 | 2004-06-15 19:16:07 +0000 | [diff] [blame^] | 241 | switch (Class) { |
Brian Gaeke | e806173 | 2004-03-04 00:56:25 +0000 | [diff] [blame] | 242 | case cByte: |
Chris Lattner | 4be7ca5 | 2004-04-07 04:27:16 +0000 | [diff] [blame] | 243 | BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm((uint8_t)Val); |
Brian Gaeke | e806173 | 2004-03-04 00:56:25 +0000 | [diff] [blame] | 244 | return; |
| 245 | case cShort: { |
| 246 | unsigned TmpReg = makeAnotherReg (C->getType ()); |
Chris Lattner | 4be7ca5 | 2004-04-07 04:27:16 +0000 | [diff] [blame] | 247 | BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg) |
| 248 | .addImm (((uint16_t) Val) >> 10); |
| 249 | BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) |
| 250 | .addImm (((uint16_t) Val) & 0x03ff); |
Brian Gaeke | e806173 | 2004-03-04 00:56:25 +0000 | [diff] [blame] | 251 | return; |
| 252 | } |
| 253 | case cInt: { |
| 254 | unsigned TmpReg = makeAnotherReg (C->getType ()); |
Chris Lattner | 4be7ca5 | 2004-04-07 04:27:16 +0000 | [diff] [blame] | 255 | BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addImm(((uint32_t)Val) >> 10); |
| 256 | BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) |
| 257 | .addImm (((uint32_t) Val) & 0x03ff); |
Brian Gaeke | e806173 | 2004-03-04 00:56:25 +0000 | [diff] [blame] | 258 | return; |
| 259 | } |
| 260 | default: |
Brian Gaeke | 2d4fa8f | 2004-04-07 04:00:49 +0000 | [diff] [blame] | 261 | std::cerr << "Offending constant: " << *C << "\n"; |
Brian Gaeke | 775158d | 2004-03-04 04:37:45 +0000 | [diff] [blame] | 262 | assert (0 && "Can't copy this kind of constant into register yet"); |
Brian Gaeke | e806173 | 2004-03-04 00:56:25 +0000 | [diff] [blame] | 263 | return; |
| 264 | } |
Brian Gaeke | 9df9282 | 2004-06-15 19:16:07 +0000 | [diff] [blame^] | 265 | } else if (isa<ConstantPointerNull>(C)) { |
| 266 | // Copy zero (null pointer) to the register. |
| 267 | BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addImm (0); |
| 268 | } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) { |
| 269 | // Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize |
| 270 | // that SETHI %reg,global == SETHI %reg,%hi(global) and |
| 271 | // OR %reg,global,%reg == OR %reg,%lo(global),%reg. |
| 272 | unsigned TmpReg = makeAnotherReg (C->getType ()); |
| 273 | BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress (CPR->getValue()); |
| 274 | BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg) |
| 275 | .addGlobalAddress (CPR->getValue ()); |
| 276 | } else { |
| 277 | std::cerr << "Offending constant: " << *C << "\n"; |
| 278 | assert (0 && "Can't copy this kind of constant into register yet"); |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 279 | } |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 280 | } |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 281 | |
Brian Gaeke | 562cb16 | 2004-04-07 17:04:09 +0000 | [diff] [blame] | 282 | void V8ISel::LoadArgumentsToVirtualRegs (Function *F) { |
| 283 | unsigned ArgOffset = 0; |
| 284 | static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2, |
| 285 | V8::I3, V8::I4, V8::I5 }; |
| 286 | assert (F->asize () < 7 |
| 287 | && "Can't handle loading excess call args off the stack yet"); |
| 288 | |
| 289 | for (Function::aiterator I = F->abegin(), E = F->aend(); I != E; ++I) { |
| 290 | unsigned Reg = getReg(*I); |
| 291 | switch (getClassB(I->getType())) { |
| 292 | case cByte: |
| 293 | case cShort: |
| 294 | case cInt: |
| 295 | BuildMI(BB, V8::ORrr, 2, Reg).addReg (V8::G0) |
| 296 | .addReg (IncomingArgRegs[ArgOffset]); |
| 297 | break; |
| 298 | default: |
| 299 | assert (0 && "Only <=32-bit, integral arguments currently handled"); |
| 300 | return; |
| 301 | } |
| 302 | ++ArgOffset; |
| 303 | } |
| 304 | } |
| 305 | |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 306 | bool V8ISel::runOnFunction(Function &Fn) { |
| 307 | // First pass over the function, lower any unknown intrinsic functions |
| 308 | // with the IntrinsicLowering class. |
| 309 | LowerUnknownIntrinsicFunctionCalls(Fn); |
| 310 | |
| 311 | F = &MachineFunction::construct(&Fn, TM); |
| 312 | |
| 313 | // Create all of the machine basic blocks for the function... |
| 314 | for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) |
| 315 | F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I)); |
| 316 | |
| 317 | BB = &F->front(); |
| 318 | |
| 319 | // Set up a frame object for the return address. This is used by the |
| 320 | // llvm.returnaddress & llvm.frameaddress intrinisics. |
| 321 | //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4); |
| 322 | |
| 323 | // Copy incoming arguments off of the stack and out of fixed registers. |
Brian Gaeke | 562cb16 | 2004-04-07 17:04:09 +0000 | [diff] [blame] | 324 | LoadArgumentsToVirtualRegs(&Fn); |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 325 | |
| 326 | // Instruction select everything except PHI nodes |
| 327 | visit(Fn); |
| 328 | |
| 329 | // Select the PHI nodes |
| 330 | //SelectPHINodes(); |
| 331 | |
| 332 | RegMap.clear(); |
| 333 | MBBMap.clear(); |
| 334 | F = 0; |
| 335 | // We always build a machine code representation for the function |
| 336 | return true; |
| 337 | } |
| 338 | |
Brian Gaeke | 3d11e8a | 2004-04-13 18:27:46 +0000 | [diff] [blame] | 339 | void V8ISel::visitCastInst(CastInst &I) { |
| 340 | unsigned SrcReg = getReg (I.getOperand (0)); |
Brian Gaeke | e302a7e | 2004-05-07 21:39:30 +0000 | [diff] [blame] | 341 | unsigned DestReg = getReg (I); |
Brian Gaeke | 3d11e8a | 2004-04-13 18:27:46 +0000 | [diff] [blame] | 342 | const Type *oldTy = I.getOperand (0)->getType (); |
| 343 | const Type *newTy = I.getType (); |
Brian Gaeke | e302a7e | 2004-05-07 21:39:30 +0000 | [diff] [blame] | 344 | unsigned oldTyClass = getClassB (oldTy); |
| 345 | unsigned newTyClass = getClassB (newTy); |
Brian Gaeke | 3d11e8a | 2004-04-13 18:27:46 +0000 | [diff] [blame] | 346 | |
Brian Gaeke | 429022b | 2004-05-08 06:36:14 +0000 | [diff] [blame] | 347 | if (oldTyClass < cLong && newTyClass < cLong) { |
| 348 | if (oldTyClass >= newTyClass) { |
| 349 | // Emit a reg->reg copy to do a equal-size or narrowing cast, |
| 350 | // and do sign/zero extension (necessary if we change signedness). |
| 351 | unsigned TmpReg1 = makeAnotherReg (newTy); |
| 352 | unsigned TmpReg2 = makeAnotherReg (newTy); |
| 353 | BuildMI (BB, V8::ORrr, 2, TmpReg1).addReg (V8::G0).addReg (SrcReg); |
| 354 | unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy)); |
| 355 | BuildMI (BB, V8::SLLri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1); |
| 356 | if (newTy->isSigned ()) { // sign-extend with SRA |
| 357 | BuildMI(BB, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg2); |
| 358 | } else { // zero-extend with SRL |
| 359 | BuildMI(BB, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg2); |
| 360 | } |
| 361 | } else { |
| 362 | unsigned TmpReg1 = makeAnotherReg (oldTy); |
| 363 | unsigned TmpReg2 = makeAnotherReg (newTy); |
| 364 | unsigned TmpReg3 = makeAnotherReg (newTy); |
| 365 | // Widening integer cast. Make sure it's fully sign/zero-extended |
| 366 | // wrt the input type, then make sure it's fully sign/zero-extended wrt |
| 367 | // the output type. Kind of stupid, but simple... |
| 368 | unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (oldTy)); |
| 369 | BuildMI (BB, V8::SLLri, 2, TmpReg1).addZImm (shiftWidth).addReg(SrcReg); |
| 370 | if (oldTy->isSigned ()) { // sign-extend with SRA |
| 371 | BuildMI(BB, V8::SRAri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1); |
| 372 | } else { // zero-extend with SRL |
| 373 | BuildMI(BB, V8::SRLri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1); |
| 374 | } |
| 375 | shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy)); |
| 376 | BuildMI (BB, V8::SLLri, 2, TmpReg3).addZImm (shiftWidth).addReg(TmpReg2); |
| 377 | if (newTy->isSigned ()) { // sign-extend with SRA |
| 378 | BuildMI(BB, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg3); |
| 379 | } else { // zero-extend with SRL |
| 380 | BuildMI(BB, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg3); |
| 381 | } |
Brian Gaeke | e302a7e | 2004-05-07 21:39:30 +0000 | [diff] [blame] | 382 | } |
| 383 | } else { |
Brian Gaeke | 429022b | 2004-05-08 06:36:14 +0000 | [diff] [blame] | 384 | std::cerr << "Casts w/ long, fp, double still unsupported: " << I; |
Brian Gaeke | e302a7e | 2004-05-07 21:39:30 +0000 | [diff] [blame] | 385 | abort (); |
| 386 | } |
Brian Gaeke | 3d11e8a | 2004-04-13 18:27:46 +0000 | [diff] [blame] | 387 | } |
| 388 | |
Brian Gaeke | f3334eb | 2004-04-07 17:29:37 +0000 | [diff] [blame] | 389 | void V8ISel::visitLoadInst(LoadInst &I) { |
| 390 | unsigned DestReg = getReg (I); |
| 391 | unsigned PtrReg = getReg (I.getOperand (0)); |
Brian Gaeke | 532e60c | 2004-05-08 04:21:17 +0000 | [diff] [blame] | 392 | switch (getClassB (I.getType ())) { |
Brian Gaeke | f3334eb | 2004-04-07 17:29:37 +0000 | [diff] [blame] | 393 | case cByte: |
| 394 | if (I.getType ()->isSigned ()) |
| 395 | BuildMI (BB, V8::LDSBmr, 1, DestReg).addReg (PtrReg).addSImm(0); |
| 396 | else |
| 397 | BuildMI (BB, V8::LDUBmr, 1, DestReg).addReg (PtrReg).addSImm(0); |
| 398 | return; |
| 399 | case cShort: |
| 400 | if (I.getType ()->isSigned ()) |
| 401 | BuildMI (BB, V8::LDSHmr, 1, DestReg).addReg (PtrReg).addSImm(0); |
| 402 | else |
| 403 | BuildMI (BB, V8::LDUHmr, 1, DestReg).addReg (PtrReg).addSImm(0); |
| 404 | return; |
| 405 | case cInt: |
| 406 | BuildMI (BB, V8::LDmr, 1, DestReg).addReg (PtrReg).addSImm(0); |
| 407 | return; |
| 408 | case cLong: |
| 409 | BuildMI (BB, V8::LDDmr, 1, DestReg).addReg (PtrReg).addSImm(0); |
| 410 | return; |
| 411 | default: |
| 412 | std::cerr << "Load instruction not handled: " << I; |
| 413 | abort (); |
| 414 | return; |
| 415 | } |
| 416 | } |
| 417 | |
| 418 | void V8ISel::visitStoreInst(StoreInst &I) { |
Brian Gaeke | 532e60c | 2004-05-08 04:21:17 +0000 | [diff] [blame] | 419 | Value *SrcVal = I.getOperand (0); |
| 420 | unsigned SrcReg = getReg (SrcVal); |
Brian Gaeke | f3334eb | 2004-04-07 17:29:37 +0000 | [diff] [blame] | 421 | unsigned PtrReg = getReg (I.getOperand (1)); |
Brian Gaeke | 532e60c | 2004-05-08 04:21:17 +0000 | [diff] [blame] | 422 | switch (getClassB (SrcVal->getType ())) { |
| 423 | case cByte: |
| 424 | BuildMI (BB, V8::STBrm, 1, SrcReg).addReg (PtrReg).addSImm(0); |
| 425 | return; |
| 426 | case cShort: |
| 427 | BuildMI (BB, V8::STHrm, 1, SrcReg).addReg (PtrReg).addSImm(0); |
| 428 | return; |
| 429 | case cInt: |
| 430 | BuildMI (BB, V8::STrm, 1, SrcReg).addReg (PtrReg).addSImm(0); |
| 431 | return; |
| 432 | case cLong: |
| 433 | BuildMI (BB, V8::STDrm, 1, SrcReg).addReg (PtrReg).addSImm(0); |
| 434 | return; |
| 435 | default: |
| 436 | std::cerr << "Store instruction not handled: " << I; |
| 437 | abort (); |
| 438 | return; |
| 439 | } |
Brian Gaeke | f3334eb | 2004-04-07 17:29:37 +0000 | [diff] [blame] | 440 | } |
| 441 | |
Brian Gaeke | f7e44ef | 2004-04-02 20:53:33 +0000 | [diff] [blame] | 442 | void V8ISel::visitCallInst(CallInst &I) { |
Brian Gaeke | d54c38b | 2004-04-07 16:41:22 +0000 | [diff] [blame] | 443 | assert (I.getNumOperands () < 8 |
| 444 | && "Can't handle pushing excess call args on the stack yet"); |
Brian Gaeke | 562cb16 | 2004-04-07 17:04:09 +0000 | [diff] [blame] | 445 | static const unsigned OutgoingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3, |
Brian Gaeke | d54c38b | 2004-04-07 16:41:22 +0000 | [diff] [blame] | 446 | V8::O4, V8::O5 }; |
| 447 | for (unsigned i = 1; i < 7; ++i) |
| 448 | if (i < I.getNumOperands ()) { |
| 449 | unsigned ArgReg = getReg (I.getOperand (i)); |
| 450 | // Schlep it over into the incoming arg register |
Brian Gaeke | 562cb16 | 2004-04-07 17:04:09 +0000 | [diff] [blame] | 451 | BuildMI (BB, V8::ORrr, 2, OutgoingArgRegs[i - 1]).addReg (V8::G0) |
Brian Gaeke | d54c38b | 2004-04-07 16:41:22 +0000 | [diff] [blame] | 452 | .addReg (ArgReg); |
| 453 | } |
| 454 | |
Brian Gaeke | ea8494b | 2004-04-06 22:09:23 +0000 | [diff] [blame] | 455 | unsigned DestReg = getReg (I); |
Brian Gaeke | f7e44ef | 2004-04-02 20:53:33 +0000 | [diff] [blame] | 456 | BuildMI (BB, V8::CALL, 1).addPCDisp (I.getOperand (0)); |
Brian Gaeke | ea8494b | 2004-04-06 22:09:23 +0000 | [diff] [blame] | 457 | if (I.getType ()->getPrimitiveID () == Type::VoidTyID) |
| 458 | return; |
| 459 | // Deal w/ return value |
| 460 | switch (getClass (I.getType ())) { |
| 461 | case cByte: |
| 462 | case cShort: |
| 463 | case cInt: |
| 464 | // Schlep it over into the destination register |
| 465 | BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0); |
| 466 | break; |
| 467 | default: |
Brian Gaeke | 532e60c | 2004-05-08 04:21:17 +0000 | [diff] [blame] | 468 | std::cerr << "Return type of call instruction not handled: " << I; |
| 469 | abort (); |
Brian Gaeke | ea8494b | 2004-04-06 22:09:23 +0000 | [diff] [blame] | 470 | } |
Brian Gaeke | f7e44ef | 2004-04-02 20:53:33 +0000 | [diff] [blame] | 471 | } |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 472 | |
| 473 | void V8ISel::visitReturnInst(ReturnInst &I) { |
Brian Gaeke | 08f64c3 | 2004-03-06 05:32:28 +0000 | [diff] [blame] | 474 | if (I.getNumOperands () == 1) { |
| 475 | unsigned RetValReg = getReg (I.getOperand (0)); |
| 476 | switch (getClass (I.getOperand (0)->getType ())) { |
| 477 | case cByte: |
| 478 | case cShort: |
| 479 | case cInt: |
| 480 | // Schlep it over into i0 (where it will become o0 after restore). |
| 481 | BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg); |
| 482 | break; |
| 483 | default: |
Brian Gaeke | 532e60c | 2004-05-08 04:21:17 +0000 | [diff] [blame] | 484 | std::cerr << "Return instruction of this type not handled: " << I; |
| 485 | abort (); |
Brian Gaeke | 08f64c3 | 2004-03-06 05:32:28 +0000 | [diff] [blame] | 486 | } |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 487 | } |
Chris Lattner | 0d538bb | 2004-04-07 04:36:53 +0000 | [diff] [blame] | 488 | |
Brian Gaeke | 08f64c3 | 2004-03-06 05:32:28 +0000 | [diff] [blame] | 489 | // Just emit a 'retl' instruction to return. |
| 490 | BuildMI(BB, V8::RETL, 0); |
| 491 | return; |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 492 | } |
| 493 | |
Brian Gaeke | 532e60c | 2004-05-08 04:21:17 +0000 | [diff] [blame] | 494 | static inline BasicBlock *getBlockAfter(BasicBlock *BB) { |
| 495 | Function::iterator I = BB; ++I; // Get iterator to next block |
| 496 | return I != BB->getParent()->end() ? &*I : 0; |
| 497 | } |
| 498 | |
| 499 | /// visitBranchInst - Handles conditional and unconditional branches. |
| 500 | /// |
| 501 | void V8ISel::visitBranchInst(BranchInst &I) { |
| 502 | // Update machine-CFG edges |
| 503 | BB->addSuccessor (MBBMap[I.getSuccessor(0)]); |
| 504 | if (I.isConditional()) |
| 505 | BB->addSuccessor (MBBMap[I.getSuccessor(1)]); |
| 506 | |
| 507 | BasicBlock *NextBB = getBlockAfter(I.getParent()); // BB after current one |
| 508 | |
| 509 | BasicBlock *takenSucc = I.getSuccessor (0); |
| 510 | if (!I.isConditional()) { // Unconditional branch? |
| 511 | if (I.getSuccessor(0) != NextBB) |
| 512 | BuildMI (BB, V8::BA, 1).addPCDisp (takenSucc); |
| 513 | return; |
| 514 | } |
| 515 | |
| 516 | unsigned CondReg = getReg (I.getCondition ()); |
| 517 | BasicBlock *notTakenSucc = I.getSuccessor (1); |
| 518 | // Set Z condition code if CondReg was false |
| 519 | BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg); |
| 520 | if (notTakenSucc == NextBB) { |
| 521 | if (takenSucc != NextBB) |
| 522 | BuildMI (BB, V8::BNE, 1).addPCDisp (takenSucc); |
| 523 | } else { |
| 524 | BuildMI (BB, V8::BE, 1).addPCDisp (notTakenSucc); |
| 525 | if (takenSucc != NextBB) |
| 526 | BuildMI (BB, V8::BA, 1).addPCDisp (takenSucc); |
| 527 | } |
| 528 | } |
| 529 | |
| 530 | /// emitGEPOperation - Common code shared between visitGetElementPtrInst and |
| 531 | /// constant expression GEP support. |
| 532 | /// |
Brian Gaeke | 9f56482 | 2004-05-08 05:27:20 +0000 | [diff] [blame] | 533 | void V8ISel::emitGEPOperation (MachineBasicBlock *MBB, |
Brian Gaeke | 532e60c | 2004-05-08 04:21:17 +0000 | [diff] [blame] | 534 | MachineBasicBlock::iterator IP, |
| 535 | Value *Src, User::op_iterator IdxBegin, |
| 536 | User::op_iterator IdxEnd, unsigned TargetReg) { |
Brian Gaeke | 9f56482 | 2004-05-08 05:27:20 +0000 | [diff] [blame] | 537 | const TargetData &TD = TM.getTargetData (); |
| 538 | const Type *Ty = Src->getType (); |
| 539 | unsigned basePtrReg = getReg (Src); |
| 540 | |
| 541 | // GEPs have zero or more indices; we must perform a struct access |
| 542 | // or array access for each one. |
| 543 | for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe; |
| 544 | ++oi) { |
| 545 | Value *idx = *oi; |
| 546 | unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy); |
| 547 | if (const StructType *StTy = dyn_cast<StructType> (Ty)) { |
| 548 | // It's a struct access. idx is the index into the structure, |
| 549 | // which names the field. Use the TargetData structure to |
| 550 | // pick out what the layout of the structure is in memory. |
| 551 | // Use the (constant) structure index's value to find the |
| 552 | // right byte offset from the StructLayout class's list of |
| 553 | // structure member offsets. |
| 554 | unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue (); |
| 555 | unsigned memberOffset = |
| 556 | TD.getStructLayout (StTy)->MemberOffsets[fieldIndex]; |
| 557 | // Emit an ADD to add memberOffset to the basePtr. |
| 558 | BuildMI (*MBB, IP, V8::ADDri, 2, |
| 559 | nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset); |
| 560 | // The next type is the member of the structure selected by the |
| 561 | // index. |
| 562 | Ty = StTy->getElementType (fieldIndex); |
| 563 | } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) { |
| 564 | // It's an array or pointer access: [ArraySize x ElementType]. |
| 565 | // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we |
| 566 | // must find the size of the pointed-to type (Not coincidentally, the next |
| 567 | // type is the type of the elements in the array). |
| 568 | Ty = SqTy->getElementType (); |
| 569 | unsigned elementSize = TD.getTypeSize (Ty); |
| 570 | unsigned idxReg = getReg (idx, MBB, IP); |
| 571 | unsigned OffsetReg = makeAnotherReg (Type::IntTy); |
| 572 | unsigned elementSizeReg = makeAnotherReg (Type::UIntTy); |
| 573 | BuildMI (*MBB, IP, V8::ORri, 2, |
| 574 | elementSizeReg).addZImm (elementSize).addReg (V8::G0); |
| 575 | // Emit a SMUL to multiply the register holding the index by |
| 576 | // elementSize, putting the result in OffsetReg. |
| 577 | BuildMI (*MBB, IP, V8::SMULrr, 2, |
| 578 | OffsetReg).addReg (elementSizeReg).addReg (idxReg); |
| 579 | // Emit an ADD to add OffsetReg to the basePtr. |
| 580 | BuildMI (*MBB, IP, V8::ADDrr, 2, |
| 581 | nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg); |
| 582 | } |
| 583 | basePtrReg = nextBasePtrReg; |
| 584 | } |
| 585 | // After we have processed all the indices, the result is left in |
| 586 | // basePtrReg. Move it to the register where we were expected to |
| 587 | // put the answer. |
| 588 | BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg); |
Brian Gaeke | 532e60c | 2004-05-08 04:21:17 +0000 | [diff] [blame] | 589 | } |
| 590 | |
| 591 | void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) { |
| 592 | unsigned outputReg = getReg (I); |
| 593 | emitGEPOperation (BB, BB->end (), I.getOperand (0), |
| 594 | I.op_begin ()+1, I.op_end (), outputReg); |
| 595 | } |
| 596 | |
Chris Lattner | 4be7ca5 | 2004-04-07 04:27:16 +0000 | [diff] [blame] | 597 | void V8ISel::visitBinaryOperator (Instruction &I) { |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 598 | unsigned DestReg = getReg (I); |
| 599 | unsigned Op0Reg = getReg (I.getOperand (0)); |
| 600 | unsigned Op1Reg = getReg (I.getOperand (1)); |
| 601 | |
Chris Lattner | 0d538bb | 2004-04-07 04:36:53 +0000 | [diff] [blame] | 602 | unsigned ResultReg = DestReg; |
| 603 | if (getClassB(I.getType()) != cInt) |
| 604 | ResultReg = makeAnotherReg (I.getType ()); |
Chris Lattner | 22ede70 | 2004-04-07 04:06:46 +0000 | [diff] [blame] | 605 | unsigned OpCase = ~0; |
| 606 | |
Brian Gaeke | 2d4fa8f | 2004-04-07 04:00:49 +0000 | [diff] [blame] | 607 | // FIXME: support long, ulong, fp. |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 608 | switch (I.getOpcode ()) { |
Chris Lattner | 22ede70 | 2004-04-07 04:06:46 +0000 | [diff] [blame] | 609 | case Instruction::Add: OpCase = 0; break; |
| 610 | case Instruction::Sub: OpCase = 1; break; |
| 611 | case Instruction::Mul: OpCase = 2; break; |
| 612 | case Instruction::And: OpCase = 3; break; |
| 613 | case Instruction::Or: OpCase = 4; break; |
| 614 | case Instruction::Xor: OpCase = 5; break; |
Chris Lattner | 4be7ca5 | 2004-04-07 04:27:16 +0000 | [diff] [blame] | 615 | case Instruction::Shl: OpCase = 6; break; |
| 616 | case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break; |
Chris Lattner | 22ede70 | 2004-04-07 04:06:46 +0000 | [diff] [blame] | 617 | |
| 618 | case Instruction::Div: |
| 619 | case Instruction::Rem: { |
| 620 | unsigned Dest = ResultReg; |
| 621 | if (I.getOpcode() == Instruction::Rem) |
| 622 | Dest = makeAnotherReg(I.getType()); |
| 623 | |
| 624 | // FIXME: this is probably only right for 32 bit operands. |
| 625 | if (I.getType ()->isSigned()) { |
| 626 | unsigned Tmp = makeAnotherReg (I.getType ()); |
| 627 | // Sign extend into the Y register |
| 628 | BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31); |
| 629 | BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0); |
| 630 | BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg); |
| 631 | } else { |
| 632 | // Zero extend into the Y register, ie, just set it to zero |
| 633 | BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0); |
| 634 | BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg); |
Brian Gaeke | 2d4fa8f | 2004-04-07 04:00:49 +0000 | [diff] [blame] | 635 | } |
Chris Lattner | 22ede70 | 2004-04-07 04:06:46 +0000 | [diff] [blame] | 636 | |
| 637 | if (I.getOpcode() == Instruction::Rem) { |
| 638 | unsigned Tmp = makeAnotherReg (I.getType ()); |
| 639 | BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg); |
| 640 | BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp); |
Brian Gaeke | f57e364 | 2004-03-16 22:37:11 +0000 | [diff] [blame] | 641 | } |
Chris Lattner | 22ede70 | 2004-04-07 04:06:46 +0000 | [diff] [blame] | 642 | break; |
| 643 | } |
| 644 | default: |
| 645 | visitInstruction (I); |
| 646 | return; |
| 647 | } |
| 648 | |
| 649 | if (OpCase != ~0U) { |
| 650 | static const unsigned Opcodes[] = { |
Chris Lattner | 4be7ca5 | 2004-04-07 04:27:16 +0000 | [diff] [blame] | 651 | V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr, |
| 652 | V8::SLLrr, V8::SRLrr, V8::SRArr |
Chris Lattner | 22ede70 | 2004-04-07 04:06:46 +0000 | [diff] [blame] | 653 | }; |
| 654 | BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg); |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 655 | } |
| 656 | |
| 657 | switch (getClass (I.getType ())) { |
| 658 | case cByte: |
Brian Gaeke | 08f64c3 | 2004-03-06 05:32:28 +0000 | [diff] [blame] | 659 | if (I.getType ()->isSigned ()) { // add byte |
| 660 | BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff); |
| 661 | } else { // add ubyte |
| 662 | unsigned TmpReg = makeAnotherReg (I.getType ()); |
| 663 | BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24); |
| 664 | BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24); |
| 665 | } |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 666 | break; |
| 667 | case cShort: |
Brian Gaeke | 08f64c3 | 2004-03-06 05:32:28 +0000 | [diff] [blame] | 668 | if (I.getType ()->isSigned ()) { // add short |
| 669 | unsigned TmpReg = makeAnotherReg (I.getType ()); |
| 670 | BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16); |
| 671 | BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16); |
| 672 | } else { // add ushort |
| 673 | unsigned TmpReg = makeAnotherReg (I.getType ()); |
Brian Gaeke | 6d339f9 | 2004-03-16 22:45:42 +0000 | [diff] [blame] | 674 | BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16); |
| 675 | BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16); |
Brian Gaeke | 08f64c3 | 2004-03-06 05:32:28 +0000 | [diff] [blame] | 676 | } |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 677 | break; |
| 678 | case cInt: |
Chris Lattner | 0d538bb | 2004-04-07 04:36:53 +0000 | [diff] [blame] | 679 | // Nothing todo here. |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 680 | break; |
| 681 | default: |
Brian Gaeke | 08f64c3 | 2004-03-06 05:32:28 +0000 | [diff] [blame] | 682 | visitInstruction (I); |
Brian Gaeke | bc1d27a | 2004-03-03 23:03:14 +0000 | [diff] [blame] | 683 | return; |
| 684 | } |
| 685 | } |
| 686 | |
Chris Lattner | 4d0cda4 | 2004-04-07 05:04:51 +0000 | [diff] [blame] | 687 | void V8ISel::visitSetCondInst(Instruction &I) { |
| 688 | unsigned Op0Reg = getReg (I.getOperand (0)); |
| 689 | unsigned Op1Reg = getReg (I.getOperand (1)); |
| 690 | unsigned DestReg = getReg (I); |
Brian Gaeke | 429022b | 2004-05-08 06:36:14 +0000 | [diff] [blame] | 691 | const Type *Ty = I.getOperand (0)->getType (); |
Chris Lattner | 4d0cda4 | 2004-04-07 05:04:51 +0000 | [diff] [blame] | 692 | |
| 693 | // Compare the two values. |
| 694 | BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg); |
| 695 | |
Brian Gaeke | 429022b | 2004-05-08 06:36:14 +0000 | [diff] [blame] | 696 | unsigned BranchIdx; |
Chris Lattner | 4d0cda4 | 2004-04-07 05:04:51 +0000 | [diff] [blame] | 697 | switch (I.getOpcode()) { |
| 698 | default: assert(0 && "Unknown setcc instruction!"); |
Brian Gaeke | 429022b | 2004-05-08 06:36:14 +0000 | [diff] [blame] | 699 | case Instruction::SetEQ: BranchIdx = 0; break; |
| 700 | case Instruction::SetNE: BranchIdx = 1; break; |
| 701 | case Instruction::SetLT: BranchIdx = 2; break; |
| 702 | case Instruction::SetGT: BranchIdx = 3; break; |
| 703 | case Instruction::SetLE: BranchIdx = 4; break; |
| 704 | case Instruction::SetGE: BranchIdx = 5; break; |
Chris Lattner | 4d0cda4 | 2004-04-07 05:04:51 +0000 | [diff] [blame] | 705 | } |
Brian Gaeke | 429022b | 2004-05-08 06:36:14 +0000 | [diff] [blame] | 706 | static unsigned OpcodeTab[12] = { |
| 707 | // LLVM SparcV8 |
| 708 | // unsigned signed |
| 709 | V8::BE, V8::BE, // seteq = be be |
| 710 | V8::BNE, V8::BNE, // setne = bne bne |
| 711 | V8::BCS, V8::BL, // setlt = bcs bl |
| 712 | V8::BGU, V8::BG, // setgt = bgu bg |
| 713 | V8::BLEU, V8::BLE, // setle = bleu ble |
| 714 | V8::BCC, V8::BGE // setge = bcc bge |
| 715 | }; |
| 716 | unsigned Opcode = OpcodeTab[BranchIdx + (Ty->isSigned() ? 1 : 0)]; |
| 717 | MachineBasicBlock *Copy1MBB, *Copy0MBB, *CopyCondMBB; |
| 718 | MachineBasicBlock::iterator IP; |
| 719 | #if 0 |
| 720 | // Cond. Branch from BB --> either Copy1MBB or Copy0MBB --> CopyCondMBB |
| 721 | // Then once we're done with the SetCC, BB = CopyCondMBB. |
| 722 | BasicBlock *LLVM_BB = BB.getBasicBlock (); |
| 723 | unsigned Cond0Reg = makeAnotherReg (I.getType ()); |
| 724 | unsigned Cond1Reg = makeAnotherReg (I.getType ()); |
| 725 | F->getBasicBlockList ().push_back (Copy1MBB = new MachineBasicBlock (LLVM_BB)); |
| 726 | F->getBasicBlockList ().push_back (Copy0MBB = new MachineBasicBlock (LLVM_BB)); |
| 727 | F->getBasicBlockList ().push_back (CopyCondMBB = new MachineBasicBlock (LLVM_BB)); |
| 728 | BuildMI (BB, Opcode, 1).addMBB (Copy1MBB); |
| 729 | BuildMI (BB, V8::BA, 1).addMBB (Copy0MBB); |
| 730 | IP = Copy1MBB->begin (); |
| 731 | BuildMI (*Copy1MBB, IP, V8::ORri, 2, Cond1Reg).addZImm (1).addReg (V8::G0); |
| 732 | BuildMI (*Copy1MBB, IP, V8::BA, 1).addMBB (CopyCondMBB); |
| 733 | IP = Copy0MBB->begin (); |
| 734 | BuildMI (*Copy0MBB, IP, V8::ORri, 2, Cond0Reg).addZImm (0).addReg (V8::G0); |
| 735 | BuildMI (*Copy0MBB, IP, V8::BA, 1).addMBB (CopyCondMBB); |
| 736 | // What should go in CopyCondMBB: PHI, then OR to copy cond. reg to DestReg |
| 737 | #endif |
Chris Lattner | 4d0cda4 | 2004-04-07 05:04:51 +0000 | [diff] [blame] | 738 | visitInstruction(I); |
| 739 | } |
| 740 | |
| 741 | |
Chris Lattner | 1c809c5 | 2004-02-29 00:27:00 +0000 | [diff] [blame] | 742 | |
| 743 | /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the |
| 744 | /// function, lowering any calls to unknown intrinsic functions into the |
| 745 | /// equivalent LLVM code. |
| 746 | void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) { |
| 747 | for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) |
| 748 | for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ) |
| 749 | if (CallInst *CI = dyn_cast<CallInst>(I++)) |
| 750 | if (Function *F = CI->getCalledFunction()) |
| 751 | switch (F->getIntrinsicID()) { |
| 752 | case Intrinsic::not_intrinsic: break; |
| 753 | default: |
| 754 | // All other intrinsic calls we must lower. |
| 755 | Instruction *Before = CI->getPrev(); |
| 756 | TM.getIntrinsicLowering().LowerIntrinsicCall(CI); |
| 757 | if (Before) { // Move iterator to instruction after call |
| 758 | I = Before; ++I; |
| 759 | } else { |
| 760 | I = BB->begin(); |
| 761 | } |
| 762 | } |
| 763 | } |
| 764 | |
| 765 | |
| 766 | void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) { |
| 767 | unsigned TmpReg1, TmpReg2; |
| 768 | switch (ID) { |
| 769 | default: assert(0 && "Intrinsic not supported!"); |
| 770 | } |
| 771 | } |