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gerrit-public.fairphone.software / platform / external / llvm / 815c7aba99c80f463d4ffc3d7de30efd0c973965 / . / lib / Target / ARM / ARMInstrNEON.td
blob: 147490c78434633ed6a97c52f8698a2109c1ea3b [file] [log] [blame]
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]1//===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the ARM NEON instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// NEON-specific DAG Nodes.
16//===----------------------------------------------------------------------===//
17
18def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19
20def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
26
27// Types for vector shift by immediates. The "SHX" version is for long and
28// narrow operations where the source and destination vectors have different
29// types. The "SHINS" version is for shift and insert operations.
30def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
31 SDTCisVT<2, i32>]>;
32def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
33 SDTCisVT<2, i32>]>;
34def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
36
37def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
44
45def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
48
49def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
55
56def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
59
60def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
62
63def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
64 SDTCisVT<2, i32>]>;
65def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
67
68def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
70
Bob Wilsond2a2e002009-08-04 00:36:16 +0000[diff] [blame]71def SDTARMVLD : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
72def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD,
73 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
74def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD,
75 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
76def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD,
77 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
78
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]79//===----------------------------------------------------------------------===//
80// NEON operand definitions
81//===----------------------------------------------------------------------===//
82
83// addrmode_neonldstm := reg
84//
85/* TODO: Take advantage of vldm.
86def addrmode_neonldstm : Operand<i32>,
87 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
88 let PrintMethod = "printAddrNeonLdStMOperand";
89 let MIOperandInfo = (ops GPR, i32imm);
90}
91*/
92
93//===----------------------------------------------------------------------===//
94// NEON load / store instructions
95//===----------------------------------------------------------------------===//
96
97/* TODO: Take advantage of vldm.
98let mayLoad = 1 in {
99def VLDMD : NI<(outs),
100 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
101 "vldm${addr:submode} ${addr:base}, $dst1",
Evan Chengdabc6c02009-07-08 22:51:32 +0000[diff] [blame]102 []> {
103 let Inst{27-25} = 0b110;
104 let Inst{20} = 1;
105 let Inst{11-9} = 0b101;
106}
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]107
108def VLDMS : NI<(outs),
109 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
110 "vldm${addr:submode} ${addr:base}, $dst1",
Evan Chengdabc6c02009-07-08 22:51:32 +0000[diff] [blame]111 []> {
112 let Inst{27-25} = 0b110;
113 let Inst{20} = 1;
114 let Inst{11-9} = 0b101;
115}
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]116}
117*/
118
119// Use vldmia to load a Q register as a D register pair.
120def VLDRQ : NI<(outs QPR:$dst), (ins GPR:$addr),
121 "vldmia $addr, ${dst:dregpair}",
Evan Chengdabc6c02009-07-08 22:51:32 +0000[diff] [blame]122 [(set QPR:$dst, (v2f64 (load GPR:$addr)))]> {
123 let Inst{27-25} = 0b110;
124 let Inst{24} = 0; // P bit
125 let Inst{23} = 1; // U bit
126 let Inst{20} = 1;
127 let Inst{11-9} = 0b101;
128}
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]129
130// Use vstmia to store a Q register as a D register pair.
131def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr),
132 "vstmia $addr, ${src:dregpair}",
Evan Chengdabc6c02009-07-08 22:51:32 +0000[diff] [blame]133 [(store (v2f64 QPR:$src), GPR:$addr)]> {
134 let Inst{27-25} = 0b110;
135 let Inst{24} = 0; // P bit
136 let Inst{23} = 1; // U bit
137 let Inst{20} = 0;
138 let Inst{11-9} = 0b101;
139}
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]140
141
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]142// VLD1 : Vector Load (multiple single elements)
143class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
144 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
145 !strconcat(OpcodeStr, "\t${dst:dregsingle}, $addr"),
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]146 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]147class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
148 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
149 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]150 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]151
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]152def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1i>;
153def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1i>;
154def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1i>;
155def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1f>;
156def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1i>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]157
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]158def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1i>;
159def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1i>;
160def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1i>;
161def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1f>;
162def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]163
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]164// VST1 : Vector Store (multiple single elements)
165class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
166 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
167 !strconcat(OpcodeStr, "\t${src:dregsingle}, $addr"),
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]168 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]169class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
170 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
171 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]172 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]173
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]174def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1i>;
175def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1i>;
176def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1i>;
177def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1f>;
178def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1i>;
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]179
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]180def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1i>;
181def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1i>;
182def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>;
183def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>;
184def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>;
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]185
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]186
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]187//===----------------------------------------------------------------------===//
188// NEON pattern fragments
189//===----------------------------------------------------------------------===//
190
191// Extract D sub-registers of Q registers.
192// (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
193def SubReg_i8_reg : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
195}]>;
196def SubReg_i16_reg : SDNodeXForm<imm, [{
197 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
198}]>;
199def SubReg_i32_reg : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
201}]>;
202def SubReg_f64_reg : SDNodeXForm<imm, [{
203 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
204}]>;
205
206// Translate lane numbers from Q registers to D subregs.
207def SubReg_i8_lane : SDNodeXForm<imm, [{
208 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
209}]>;
210def SubReg_i16_lane : SDNodeXForm<imm, [{
211 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
212}]>;
213def SubReg_i32_lane : SDNodeXForm<imm, [{
214 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
215}]>;
216
217//===----------------------------------------------------------------------===//
218// Instruction Classes
219//===----------------------------------------------------------------------===//
220
221// Basic 2-register operations, both double- and quad-register.
222class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
223 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
224 ValueType ResTy, ValueType OpTy, SDNode OpNode>
225 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
226 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
227 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
228class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
229 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
230 ValueType ResTy, ValueType OpTy, SDNode OpNode>
231 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
232 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
233 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
234
235// Basic 2-register intrinsics, both double- and quad-register.
236class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
237 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
238 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
239 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
240 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
241 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
242class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
243 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
244 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
245 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
246 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
247 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
248
249// Narrow 2-register intrinsics.
250class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
251 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
252 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
253 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
254 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
255 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
256
257// Long 2-register intrinsics. (This is currently only used for VMOVL and is
258// derived from N2VImm instead of N2V because of the way the size is encoded.)
259class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
260 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
261 Intrinsic IntOp>
262 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
263 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
264 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
265
266// Basic 3-register operations, both double- and quad-register.
267class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
268 string OpcodeStr, ValueType ResTy, ValueType OpTy,
269 SDNode OpNode, bit Commutable>
270 : N3V<op24, op23, op21_20, op11_8, 0, op4,
271 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
272 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
273 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
274 let isCommutable = Commutable;
275}
276class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
277 string OpcodeStr, ValueType ResTy, ValueType OpTy,
278 SDNode OpNode, bit Commutable>
279 : N3V<op24, op23, op21_20, op11_8, 1, op4,
280 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
281 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
282 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
283 let isCommutable = Commutable;
284}
285
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]286// Basic 3-register operations, scalar single-precision
287class N3VDs<SDNode OpNode, NeonI Inst>
288 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
289 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
290 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
291 arm_ssubreg_0)>;
292
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]293// Basic 3-register intrinsics, both double- and quad-register.
294class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
295 string OpcodeStr, ValueType ResTy, ValueType OpTy,
296 Intrinsic IntOp, bit Commutable>
297 : N3V<op24, op23, op21_20, op11_8, 0, op4,
298 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
299 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
300 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
301 let isCommutable = Commutable;
302}
303class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
304 string OpcodeStr, ValueType ResTy, ValueType OpTy,
305 Intrinsic IntOp, bit Commutable>
306 : N3V<op24, op23, op21_20, op11_8, 1, op4,
307 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
308 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
309 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
310 let isCommutable = Commutable;
311}
312
313// Multiply-Add/Sub operations, both double- and quad-register.
314class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
315 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
316 : N3V<op24, op23, op21_20, op11_8, 0, op4,
317 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
318 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
319 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
320 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
321class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
322 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
323 : N3V<op24, op23, op21_20, op11_8, 1, op4,
324 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
325 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
326 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
327 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
328
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]329// Multiply-Add/Sub operations, scalar single-precision
330class N3VDMulOps<SDNode MulNode, SDNode OpNode, NeonI Inst>
331 : NEONFPPat<(f32 (OpNode SPR:$acc,
332 (f32 (MulNode SPR:$a, SPR:$b)))),
333 (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
334 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
335 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
336 arm_ssubreg_0)>;
337
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]338// Neon 3-argument intrinsics, both double- and quad-register.
339// The destination register is also used as the first source operand register.
340class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
341 string OpcodeStr, ValueType ResTy, ValueType OpTy,
342 Intrinsic IntOp>
343 : N3V<op24, op23, op21_20, op11_8, 0, op4,
344 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
345 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
346 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
347 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
348class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
349 string OpcodeStr, ValueType ResTy, ValueType OpTy,
350 Intrinsic IntOp>
351 : N3V<op24, op23, op21_20, op11_8, 1, op4,
352 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
353 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
354 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
355 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
356
357// Neon Long 3-argument intrinsic. The destination register is
358// a quad-register and is also used as the first source operand register.
359class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
360 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
361 : N3V<op24, op23, op21_20, op11_8, 0, op4,
362 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3),
363 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
364 [(set QPR:$dst,
365 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
366
367// Narrowing 3-register intrinsics.
368class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
369 string OpcodeStr, ValueType TyD, ValueType TyQ,
370 Intrinsic IntOp, bit Commutable>
371 : N3V<op24, op23, op21_20, op11_8, 0, op4,
372 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2),
373 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
374 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
375 let isCommutable = Commutable;
376}
377
378// Long 3-register intrinsics.
379class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
380 string OpcodeStr, ValueType TyQ, ValueType TyD,
381 Intrinsic IntOp, bit Commutable>
382 : N3V<op24, op23, op21_20, op11_8, 0, op4,
383 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2),
384 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
385 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
386 let isCommutable = Commutable;
387}
388
389// Wide 3-register intrinsics.
390class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
391 string OpcodeStr, ValueType TyQ, ValueType TyD,
392 Intrinsic IntOp, bit Commutable>
393 : N3V<op24, op23, op21_20, op11_8, 0, op4,
394 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2),
395 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
396 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
397 let isCommutable = Commutable;
398}
399
400// Pairwise long 2-register intrinsics, both double- and quad-register.
401class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
402 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
403 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
404 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
405 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
406 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
407class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
408 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
409 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
410 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
411 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
412 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
413
414// Pairwise long 2-register accumulate intrinsics,
415// both double- and quad-register.
416// The destination register is also used as the first source operand register.
417class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
418 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
419 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
420 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
421 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
422 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
423 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
424class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
425 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
426 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
427 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
428 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
429 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
430 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
431
432// Shift by immediate,
433// both double- and quad-register.
434class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
435 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
436 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
437 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM),
438 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
439 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
440class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
441 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
442 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
443 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM),
444 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
445 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
446
447// Long shift by immediate.
448class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
449 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
450 ValueType OpTy, SDNode OpNode>
451 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
452 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM),
453 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
454 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
455 (i32 imm:$SIMM))))]>;
456
457// Narrow shift by immediate.
458class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
459 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
460 ValueType OpTy, SDNode OpNode>
461 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
462 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM),
463 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
464 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
465 (i32 imm:$SIMM))))]>;
466
467// Shift right by immediate and accumulate,
468// both double- and quad-register.
469class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
470 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
471 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
472 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
473 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
474 [(set DPR:$dst, (Ty (add DPR:$src1,
475 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
476class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
477 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
478 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
479 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
480 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
481 [(set QPR:$dst, (Ty (add QPR:$src1,
482 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
483
484// Shift by immediate and insert,
485// both double- and quad-register.
486class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
487 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
488 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
489 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
490 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
491 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
492class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
493 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
494 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
495 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
496 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
497 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
498
499// Convert, with fractional bits immediate,
500// both double- and quad-register.
501class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
502 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
503 Intrinsic IntOp>
504 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
505 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM),
506 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
507 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
508class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
509 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
510 Intrinsic IntOp>
511 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
512 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM),
513 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
514 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
515
516//===----------------------------------------------------------------------===//
517// Multiclasses
518//===----------------------------------------------------------------------===//
519
520// Neon 3-register vector operations.
521
522// First with only element sizes of 8, 16 and 32 bits:
523multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
524 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
525 // 64-bit vector types.
526 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
527 v8i8, v8i8, OpNode, Commutable>;
528 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
529 v4i16, v4i16, OpNode, Commutable>;
530 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
531 v2i32, v2i32, OpNode, Commutable>;
532
533 // 128-bit vector types.
534 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
535 v16i8, v16i8, OpNode, Commutable>;
536 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
537 v8i16, v8i16, OpNode, Commutable>;
538 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
539 v4i32, v4i32, OpNode, Commutable>;
540}
541
542// ....then also with element size 64 bits:
543multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
544 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
545 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
546 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
547 v1i64, v1i64, OpNode, Commutable>;
548 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
549 v2i64, v2i64, OpNode, Commutable>;
550}
551
552
553// Neon Narrowing 2-register vector intrinsics,
554// source operand element sizes of 16, 32 and 64 bits:
555multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
556 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
557 Intrinsic IntOp> {
558 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
559 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
560 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
561 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
562 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
563 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
564}
565
566
567// Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
568// source operand element sizes of 16, 32 and 64 bits:
569multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
570 bit op4, string OpcodeStr, Intrinsic IntOp> {
571 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
572 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
573 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
574 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
575 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
576 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
577}
578
579
580// Neon 3-register vector intrinsics.
581
582// First with only element sizes of 16 and 32 bits:
583multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
584 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
585 // 64-bit vector types.
586 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
587 v4i16, v4i16, IntOp, Commutable>;
588 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
589 v2i32, v2i32, IntOp, Commutable>;
590
591 // 128-bit vector types.
592 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
593 v8i16, v8i16, IntOp, Commutable>;
594 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
595 v4i32, v4i32, IntOp, Commutable>;
596}
597
598// ....then also with element size of 8 bits:
599multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
600 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
601 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
602 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
603 v8i8, v8i8, IntOp, Commutable>;
604 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
605 v16i8, v16i8, IntOp, Commutable>;
606}
607
608// ....then also with element size of 64 bits:
609multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
610 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
611 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
612 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
613 v1i64, v1i64, IntOp, Commutable>;
614 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
615 v2i64, v2i64, IntOp, Commutable>;
616}
617
618
619// Neon Narrowing 3-register vector intrinsics,
620// source operand element sizes of 16, 32 and 64 bits:
621multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
622 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
623 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
624 v8i8, v8i16, IntOp, Commutable>;
625 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
626 v4i16, v4i32, IntOp, Commutable>;
627 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
628 v2i32, v2i64, IntOp, Commutable>;
629}
630
631
632// Neon Long 3-register vector intrinsics.
633
634// First with only element sizes of 16 and 32 bits:
635multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
636 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
637 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
638 v4i32, v4i16, IntOp, Commutable>;
639 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
640 v2i64, v2i32, IntOp, Commutable>;
641}
642
643// ....then also with element size of 8 bits:
644multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
645 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
646 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
647 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
648 v8i16, v8i8, IntOp, Commutable>;
649}
650
651
652// Neon Wide 3-register vector intrinsics,
653// source operand element sizes of 8, 16 and 32 bits:
654multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
655 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
656 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
657 v8i16, v8i8, IntOp, Commutable>;
658 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
659 v4i32, v4i16, IntOp, Commutable>;
660 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
661 v2i64, v2i32, IntOp, Commutable>;
662}
663
664
665// Neon Multiply-Op vector operations,
666// element sizes of 8, 16 and 32 bits:
667multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
668 string OpcodeStr, SDNode OpNode> {
669 // 64-bit vector types.
670 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
671 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
672 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
673 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
674 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
675 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
676
677 // 128-bit vector types.
678 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
679 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
680 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
681 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
682 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
683 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
684}
685
686
687// Neon 3-argument intrinsics,
688// element sizes of 8, 16 and 32 bits:
689multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
690 string OpcodeStr, Intrinsic IntOp> {
691 // 64-bit vector types.
692 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
693 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
694 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
695 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
696 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
697 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
698
699 // 128-bit vector types.
700 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
701 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
702 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
703 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
704 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
705 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
706}
707
708
709// Neon Long 3-argument intrinsics.
710
711// First with only element sizes of 16 and 32 bits:
712multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
713 string OpcodeStr, Intrinsic IntOp> {
714 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
715 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
716 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
717 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
718}
719
720// ....then also with element size of 8 bits:
721multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
722 string OpcodeStr, Intrinsic IntOp>
723 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
724 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
725 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
726}
727
728
729// Neon 2-register vector intrinsics,
730// element sizes of 8, 16 and 32 bits:
731multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
732 bits<5> op11_7, bit op4, string OpcodeStr,
733 Intrinsic IntOp> {
734 // 64-bit vector types.
735 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
736 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
737 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
738 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
739 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
740 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
741
742 // 128-bit vector types.
743 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
744 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
745 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
746 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
747 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
748 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
749}
750
751
752// Neon Pairwise long 2-register intrinsics,
753// element sizes of 8, 16 and 32 bits:
754multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
755 bits<5> op11_7, bit op4,
756 string OpcodeStr, Intrinsic IntOp> {
757 // 64-bit vector types.
758 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
759 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
760 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
761 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
762 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
763 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
764
765 // 128-bit vector types.
766 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
767 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
768 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
769 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
770 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
771 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
772}
773
774
775// Neon Pairwise long 2-register accumulate intrinsics,
776// element sizes of 8, 16 and 32 bits:
777multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
778 bits<5> op11_7, bit op4,
779 string OpcodeStr, Intrinsic IntOp> {
780 // 64-bit vector types.
781 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
782 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
783 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
784 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
785 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
786 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
787
788 // 128-bit vector types.
789 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
790 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
791 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
792 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
793 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
794 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
795}
796
797
798// Neon 2-register vector shift by immediate,
799// element sizes of 8, 16, 32 and 64 bits:
800multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
801 string OpcodeStr, SDNode OpNode> {
802 // 64-bit vector types.
803 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
804 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
805 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
806 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
807 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
808 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
809 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
810 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
811
812 // 128-bit vector types.
813 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
814 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
815 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
816 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
817 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
818 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
819 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
820 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
821}
822
823
824// Neon Shift-Accumulate vector operations,
825// element sizes of 8, 16, 32 and 64 bits:
826multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
827 string OpcodeStr, SDNode ShOp> {
828 // 64-bit vector types.
829 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
830 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
831 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
832 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
833 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
834 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
835 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
836 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
837
838 // 128-bit vector types.
839 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
840 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
841 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
842 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
843 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
844 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
845 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
846 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
847}
848
849
850// Neon Shift-Insert vector operations,
851// element sizes of 8, 16, 32 and 64 bits:
852multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
853 string OpcodeStr, SDNode ShOp> {
854 // 64-bit vector types.
855 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
856 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
857 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
858 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
859 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
860 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
861 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
862 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
863
864 // 128-bit vector types.
865 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
866 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
867 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
868 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
869 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
870 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
871 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
872 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
873}
874
875//===----------------------------------------------------------------------===//
876// Instruction Definitions.
877//===----------------------------------------------------------------------===//
878
879// Vector Add Operations.
880
881// VADD : Vector Add (integer and floating-point)
882defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
883def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
884def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
885// VADDL : Vector Add Long (Q = D + D)
886defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
887defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
888// VADDW : Vector Add Wide (Q = Q + D)
889defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
890defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
891// VHADD : Vector Halving Add
892defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
893defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
894// VRHADD : Vector Rounding Halving Add
895defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
896defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
897// VQADD : Vector Saturating Add
898defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
899defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
900// VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
901defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
902// VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
903defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
904
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]905// Vector Add Operations used for single-precision FP
906def : N3VDs<fadd, VADDfd>;
907
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]908// Vector Multiply Operations.
909
910// VMUL : Vector Multiply (integer, polynomial and floating-point)
911defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
912def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
913 int_arm_neon_vmulp, 1>;
914def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
915 int_arm_neon_vmulp, 1>;
916def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
917def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
918// VQDMULH : Vector Saturating Doubling Multiply Returning High Half
919defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
920// VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
921defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
922// VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
923defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
924defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
925def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
926 int_arm_neon_vmullp, 1>;
927// VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
928defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
929
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]930// Vector Multiply Operations used for single-precision FP
931def : N3VDs<fmul, VMULfd>;
932
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]933// Vector Multiply-Accumulate and Multiply-Subtract Operations.
934
935// VMLA : Vector Multiply Accumulate (integer and floating-point)
936defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
937def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
938def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
939// VMLAL : Vector Multiply Accumulate Long (Q += D * D)
940defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
941defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
942// VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
943defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
944// VMLS : Vector Multiply Subtract (integer and floating-point)
945defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
946def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
947def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
948// VMLSL : Vector Multiply Subtract Long (Q -= D * D)
949defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
950defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
951// VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
952defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
953
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]954// Vector Multiply-Accumulate/Subtract used for single-precision FP
955def : N3VDMulOps<fmul, fadd, VMLAfd>;
David Goodwinf31748c2009-08-04 18:44:29 +0000[diff] [blame]956def : N3VDMulOps<fmul, fsub, VMLSfd>;
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]957
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]958// Vector Subtract Operations.
959
960// VSUB : Vector Subtract (integer and floating-point)
961defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
962def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
963def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
964// VSUBL : Vector Subtract Long (Q = D - D)
965defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
966defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
967// VSUBW : Vector Subtract Wide (Q = Q - D)
968defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
969defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
970// VHSUB : Vector Halving Subtract
971defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
972defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
973// VQSUB : Vector Saturing Subtract
974defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
975defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
976// VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
977defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
978// VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
979defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
980
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]981// Vector Sub Operations used for single-precision FP
982def : N3VDs<fsub, VSUBfd>;
983
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]984// Vector Comparisons.
985
986// VCEQ : Vector Compare Equal
987defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
988def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
989def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
990// VCGE : Vector Compare Greater Than or Equal
991defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
992defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
993def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
994def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
995// VCGT : Vector Compare Greater Than
996defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
997defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
998def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
999def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1000// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1001def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1002 int_arm_neon_vacged, 0>;
1003def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1004 int_arm_neon_vacgeq, 0>;
1005// VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1006def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1007 int_arm_neon_vacgtd, 0>;
1008def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1009 int_arm_neon_vacgtq, 0>;
1010// VTST : Vector Test Bits
1011defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1012
1013// Vector Bitwise Operations.
1014
1015// VAND : Vector Bitwise AND
1016def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1017def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1018
1019// VEOR : Vector Bitwise Exclusive OR
1020def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1021def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1022
1023// VORR : Vector Bitwise OR
1024def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1025def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1026
1027// VBIC : Vector Bitwise Bit Clear (AND NOT)
1028def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1029 (ins DPR:$src1, DPR:$src2), "vbic\t$dst, $src1, $src2", "",
1030 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1031def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1032 (ins QPR:$src1, QPR:$src2), "vbic\t$dst, $src1, $src2", "",
1033 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1034
1035// VORN : Vector Bitwise OR NOT
1036def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1037 (ins DPR:$src1, DPR:$src2), "vorn\t$dst, $src1, $src2", "",
1038 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1039def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1040 (ins QPR:$src1, QPR:$src2), "vorn\t$dst, $src1, $src2", "",
1041 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1042
1043// VMVN : Vector Bitwise NOT
1044def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1045 (outs DPR:$dst), (ins DPR:$src), "vmvn\t$dst, $src", "",
1046 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1047def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1048 (outs QPR:$dst), (ins QPR:$src), "vmvn\t$dst, $src", "",
1049 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1050def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1051def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1052
1053// VBSL : Vector Bitwise Select
1054def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1055 (ins DPR:$src1, DPR:$src2, DPR:$src3),
1056 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1057 [(set DPR:$dst,
1058 (v2i32 (or (and DPR:$src2, DPR:$src1),
1059 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1060def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1061 (ins QPR:$src1, QPR:$src2, QPR:$src3),
1062 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1063 [(set QPR:$dst,
1064 (v4i32 (or (and QPR:$src2, QPR:$src1),
1065 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1066
1067// VBIF : Vector Bitwise Insert if False
1068// like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1069// VBIT : Vector Bitwise Insert if True
1070// like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1071// These are not yet implemented. The TwoAddress pass will not go looking
1072// for equivalent operations with different register constraints; it just
1073// inserts copies.
1074
1075// Vector Absolute Differences.
1076
1077// VABD : Vector Absolute Difference
1078defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1079defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1080def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1081 int_arm_neon_vabdf, 0>;
1082def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1083 int_arm_neon_vabdf, 0>;
1084
1085// VABDL : Vector Absolute Difference Long (Q = | D - D |)
1086defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1087defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1088
1089// VABA : Vector Absolute Difference and Accumulate
1090defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1091defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1092
1093// VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1094defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1095defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1096
1097// Vector Maximum and Minimum.
1098
1099// VMAX : Vector Maximum
1100defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1101defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1102def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1103 int_arm_neon_vmaxf, 1>;
1104def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1105 int_arm_neon_vmaxf, 1>;
1106
1107// VMIN : Vector Minimum
1108defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1109defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1110def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1111 int_arm_neon_vminf, 1>;
1112def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1113 int_arm_neon_vminf, 1>;
1114
1115// Vector Pairwise Operations.
1116
1117// VPADD : Vector Pairwise Add
1118def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1119 int_arm_neon_vpaddi, 0>;
1120def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1121 int_arm_neon_vpaddi, 0>;
1122def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1123 int_arm_neon_vpaddi, 0>;
1124def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1125 int_arm_neon_vpaddf, 0>;
1126
1127// VPADDL : Vector Pairwise Add Long
1128defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1129 int_arm_neon_vpaddls>;
1130defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1131 int_arm_neon_vpaddlu>;
1132
1133// VPADAL : Vector Pairwise Add and Accumulate Long
1134defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1135 int_arm_neon_vpadals>;
1136defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1137 int_arm_neon_vpadalu>;
1138
1139// VPMAX : Vector Pairwise Maximum
1140def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1141 int_arm_neon_vpmaxs, 0>;
1142def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1143 int_arm_neon_vpmaxs, 0>;
1144def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1145 int_arm_neon_vpmaxs, 0>;
1146def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1147 int_arm_neon_vpmaxu, 0>;
1148def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1149 int_arm_neon_vpmaxu, 0>;
1150def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1151 int_arm_neon_vpmaxu, 0>;
1152def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1153 int_arm_neon_vpmaxf, 0>;
1154
1155// VPMIN : Vector Pairwise Minimum
1156def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1157 int_arm_neon_vpmins, 0>;
1158def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1159 int_arm_neon_vpmins, 0>;
1160def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1161 int_arm_neon_vpmins, 0>;
1162def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1163 int_arm_neon_vpminu, 0>;
1164def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1165 int_arm_neon_vpminu, 0>;
1166def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1167 int_arm_neon_vpminu, 0>;
1168def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1169 int_arm_neon_vpminf, 0>;
1170
1171// Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1172
1173// VRECPE : Vector Reciprocal Estimate
1174def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1175 v2i32, v2i32, int_arm_neon_vrecpe>;
1176def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1177 v4i32, v4i32, int_arm_neon_vrecpe>;
1178def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1179 v2f32, v2f32, int_arm_neon_vrecpef>;
1180def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1181 v4f32, v4f32, int_arm_neon_vrecpef>;
1182
1183// VRECPS : Vector Reciprocal Step
1184def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1185 int_arm_neon_vrecps, 1>;
1186def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1187 int_arm_neon_vrecps, 1>;
1188
1189// VRSQRTE : Vector Reciprocal Square Root Estimate
1190def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1191 v2i32, v2i32, int_arm_neon_vrsqrte>;
1192def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1193 v4i32, v4i32, int_arm_neon_vrsqrte>;
1194def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1195 v2f32, v2f32, int_arm_neon_vrsqrtef>;
1196def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1197 v4f32, v4f32, int_arm_neon_vrsqrtef>;
1198
1199// VRSQRTS : Vector Reciprocal Square Root Step
1200def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1201 int_arm_neon_vrsqrts, 1>;
1202def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1203 int_arm_neon_vrsqrts, 1>;
1204
1205// Vector Shifts.
1206
1207// VSHL : Vector Shift
1208defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1209defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1210// VSHL : Vector Shift Left (Immediate)
1211defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1212// VSHR : Vector Shift Right (Immediate)
1213defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1214defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1215
1216// VSHLL : Vector Shift Left Long
1217def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1218 v8i16, v8i8, NEONvshlls>;
1219def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1220 v4i32, v4i16, NEONvshlls>;
1221def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1222 v2i64, v2i32, NEONvshlls>;
1223def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1224 v8i16, v8i8, NEONvshllu>;
1225def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1226 v4i32, v4i16, NEONvshllu>;
1227def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1228 v2i64, v2i32, NEONvshllu>;
1229
1230// VSHLL : Vector Shift Left Long (with maximum shift count)
1231def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1232 v8i16, v8i8, NEONvshlli>;
1233def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1234 v4i32, v4i16, NEONvshlli>;
1235def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1236 v2i64, v2i32, NEONvshlli>;
1237
1238// VSHRN : Vector Shift Right and Narrow
1239def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1240 v8i8, v8i16, NEONvshrn>;
1241def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1242 v4i16, v4i32, NEONvshrn>;
1243def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1244 v2i32, v2i64, NEONvshrn>;
1245
1246// VRSHL : Vector Rounding Shift
1247defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1248defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1249// VRSHR : Vector Rounding Shift Right
1250defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1251defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1252
1253// VRSHRN : Vector Rounding Shift Right and Narrow
1254def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1255 v8i8, v8i16, NEONvrshrn>;
1256def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1257 v4i16, v4i32, NEONvrshrn>;
1258def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1259 v2i32, v2i64, NEONvrshrn>;
1260
1261// VQSHL : Vector Saturating Shift
1262defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1263defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1264// VQSHL : Vector Saturating Shift Left (Immediate)
1265defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1266defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1267// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1268defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1269
1270// VQSHRN : Vector Saturating Shift Right and Narrow
1271def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1272 v8i8, v8i16, NEONvqshrns>;
1273def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1274 v4i16, v4i32, NEONvqshrns>;
1275def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1276 v2i32, v2i64, NEONvqshrns>;
1277def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1278 v8i8, v8i16, NEONvqshrnu>;
1279def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1280 v4i16, v4i32, NEONvqshrnu>;
1281def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1282 v2i32, v2i64, NEONvqshrnu>;
1283
1284// VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1285def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1286 v8i8, v8i16, NEONvqshrnsu>;
1287def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1288 v4i16, v4i32, NEONvqshrnsu>;
1289def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1290 v2i32, v2i64, NEONvqshrnsu>;
1291
1292// VQRSHL : Vector Saturating Rounding Shift
1293defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1294 int_arm_neon_vqrshifts, 0>;
1295defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1296 int_arm_neon_vqrshiftu, 0>;
1297
1298// VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1299def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1300 v8i8, v8i16, NEONvqrshrns>;
1301def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1302 v4i16, v4i32, NEONvqrshrns>;
1303def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1304 v2i32, v2i64, NEONvqrshrns>;
1305def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1306 v8i8, v8i16, NEONvqrshrnu>;
1307def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1308 v4i16, v4i32, NEONvqrshrnu>;
1309def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1310 v2i32, v2i64, NEONvqrshrnu>;
1311
1312// VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1313def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1314 v8i8, v8i16, NEONvqrshrnsu>;
1315def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1316 v4i16, v4i32, NEONvqrshrnsu>;
1317def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1318 v2i32, v2i64, NEONvqrshrnsu>;
1319
1320// VSRA : Vector Shift Right and Accumulate
1321defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1322defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1323// VRSRA : Vector Rounding Shift Right and Accumulate
1324defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1325defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1326
1327// VSLI : Vector Shift Left and Insert
1328defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1329// VSRI : Vector Shift Right and Insert
1330defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1331
1332// Vector Absolute and Saturating Absolute.
1333
1334// VABS : Vector Absolute Value
1335defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1336 int_arm_neon_vabs>;
1337def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1338 v2f32, v2f32, int_arm_neon_vabsf>;
1339def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1340 v4f32, v4f32, int_arm_neon_vabsf>;
1341
1342// VQABS : Vector Saturating Absolute Value
1343defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1344 int_arm_neon_vqabs>;
1345
1346// Vector Negate.
1347
1348def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1349def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1350
1351class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1352 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1353 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1354 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1355class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1356 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1357 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1358 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1359
1360// VNEG : Vector Negate
1361def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1362def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1363def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1364def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1365def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1366def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1367
1368// VNEG : Vector Negate (floating-point)
1369def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1370 (outs DPR:$dst), (ins DPR:$src), "vneg.f32\t$dst, $src", "",
1371 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1372def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1373 (outs QPR:$dst), (ins QPR:$src), "vneg.f32\t$dst, $src", "",
1374 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1375
1376def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1377def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1378def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1379def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1380def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1381def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1382
1383// VQNEG : Vector Saturating Negate
1384defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1385 int_arm_neon_vqneg>;
1386
1387// Vector Bit Counting Operations.
1388
1389// VCLS : Vector Count Leading Sign Bits
1390defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1391 int_arm_neon_vcls>;
1392// VCLZ : Vector Count Leading Zeros
1393defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1394 int_arm_neon_vclz>;
1395// VCNT : Vector Count One Bits
1396def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1397 v8i8, v8i8, int_arm_neon_vcnt>;
1398def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1399 v16i8, v16i8, int_arm_neon_vcnt>;
1400
1401// Vector Move Operations.
1402
1403// VMOV : Vector Move (Register)
1404
1405def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1406 "vmov\t$dst, $src", "", []>;
1407def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1408 "vmov\t$dst, $src", "", []>;
1409
1410// VMOV : Vector Move (Immediate)
1411
1412// VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1413def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1414 return ARM::getVMOVImm(N, 1, *CurDAG);
1415}]>;
1416def vmovImm8 : PatLeaf<(build_vector), [{
1417 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1418}], VMOV_get_imm8>;
1419
1420// VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1421def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1422 return ARM::getVMOVImm(N, 2, *CurDAG);
1423}]>;
1424def vmovImm16 : PatLeaf<(build_vector), [{
1425 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1426}], VMOV_get_imm16>;
1427
1428// VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1429def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1430 return ARM::getVMOVImm(N, 4, *CurDAG);
1431}]>;
1432def vmovImm32 : PatLeaf<(build_vector), [{
1433 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1434}], VMOV_get_imm32>;
1435
1436// VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1437def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1438 return ARM::getVMOVImm(N, 8, *CurDAG);
1439}]>;
1440def vmovImm64 : PatLeaf<(build_vector), [{
1441 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1442}], VMOV_get_imm64>;
1443
1444// Note: Some of the cmode bits in the following VMOV instructions need to
1445// be encoded based on the immed values.
1446
1447def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1448 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "",
1449 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1450def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1451 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "",
1452 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1453
1454def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1455 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "",
1456 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1457def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1458 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "",
1459 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1460
1461def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1462 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "",
1463 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1464def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1465 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "",
1466 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1467
1468def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1469 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "",
1470 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1471def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1472 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "",
1473 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1474
1475// VMOV : Vector Get Lane (move scalar to ARM core register)
1476
1477def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1478 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1479 "vmov", ".s8\t$dst, $src[$lane]",
1480 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1481 imm:$lane))]>;
1482def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1483 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1484 "vmov", ".s16\t$dst, $src[$lane]",
1485 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1486 imm:$lane))]>;
1487def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1488 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1489 "vmov", ".u8\t$dst, $src[$lane]",
1490 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1491 imm:$lane))]>;
1492def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1493 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1494 "vmov", ".u16\t$dst, $src[$lane]",
1495 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1496 imm:$lane))]>;
1497def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1498 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1499 "vmov", ".32\t$dst, $src[$lane]",
1500 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1501 imm:$lane))]>;
1502// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1503def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1504 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1505 (SubReg_i8_reg imm:$lane))),
1506 (SubReg_i8_lane imm:$lane))>;
1507def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1508 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1509 (SubReg_i16_reg imm:$lane))),
1510 (SubReg_i16_lane imm:$lane))>;
1511def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1512 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1513 (SubReg_i8_reg imm:$lane))),
1514 (SubReg_i8_lane imm:$lane))>;
1515def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1516 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1517 (SubReg_i16_reg imm:$lane))),
1518 (SubReg_i16_lane imm:$lane))>;
1519def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1520 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1521 (SubReg_i32_reg imm:$lane))),
1522 (SubReg_i32_lane imm:$lane))>;
1523//def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1524// (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1525def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1526 (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1527
1528
1529// VMOV : Vector Set Lane (move ARM core register to scalar)
1530
1531let Constraints = "$src1 = $dst" in {
1532def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1533 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1534 "vmov", ".8\t$dst[$lane], $src2",
1535 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1536 GPR:$src2, imm:$lane))]>;
1537def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1538 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1539 "vmov", ".16\t$dst[$lane], $src2",
1540 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1541 GPR:$src2, imm:$lane))]>;
1542def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1543 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1544 "vmov", ".32\t$dst[$lane], $src2",
1545 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1546 GPR:$src2, imm:$lane))]>;
1547}
1548def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1549 (v16i8 (INSERT_SUBREG QPR:$src1,
1550 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1551 (SubReg_i8_reg imm:$lane))),
1552 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1553 (SubReg_i8_reg imm:$lane)))>;
1554def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1555 (v8i16 (INSERT_SUBREG QPR:$src1,
1556 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1557 (SubReg_i16_reg imm:$lane))),
1558 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1559 (SubReg_i16_reg imm:$lane)))>;
1560def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1561 (v4i32 (INSERT_SUBREG QPR:$src1,
1562 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1563 (SubReg_i32_reg imm:$lane))),
1564 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1565 (SubReg_i32_reg imm:$lane)))>;
1566
1567//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1568// (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1569def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1570 (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1571
1572// VDUP : Vector Duplicate (from ARM core register to all elements)
1573
1574def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
1575 (vector_shuffle node:$lhs, node:$rhs), [{
1576 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1577 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
1578}]>;
1579
1580class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1581 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1582 "vdup", !strconcat(asmSize, "\t$dst, $src"),
1583 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1584class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1585 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1586 "vdup", !strconcat(asmSize, "\t$dst, $src"),
1587 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1588
1589def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1590def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1591def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1592def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1593def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1594def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1595
1596def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1597 "vdup", ".32\t$dst, $src",
1598 [(set DPR:$dst, (v2f32 (splat_lo
1599 (scalar_to_vector
1600 (f32 (bitconvert GPR:$src))),
1601 undef)))]>;
1602def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1603 "vdup", ".32\t$dst, $src",
1604 [(set QPR:$dst, (v4f32 (splat_lo
1605 (scalar_to_vector
1606 (f32 (bitconvert GPR:$src))),
1607 undef)))]>;
1608
1609// VDUP : Vector Duplicate Lane (from scalar to all elements)
1610
1611def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
1612 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1613 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
1614}]>;
1615
1616def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
1617 (vector_shuffle node:$lhs, node:$rhs), [{
1618 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1619 return SVOp->isSplat();
1620}], SHUFFLE_get_splat_lane>;
1621
1622class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1623 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1624 (outs DPR:$dst), (ins DPR:$src, i32imm:$lane),
1625 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1626 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
1627
1628// vector_shuffle requires that the source and destination types match, so
1629// VDUP to a 128-bit result uses a target-specific VDUPLANEQ node.
1630class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1631 ValueType ResTy, ValueType OpTy>
1632 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1633 (outs QPR:$dst), (ins DPR:$src, i32imm:$lane),
1634 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1635 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
1636
1637def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1638def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1639def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1640def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1641def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1642def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1643def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1644def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1645
1646// VMOVN : Vector Narrowing Move
1647defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1648 int_arm_neon_vmovn>;
1649// VQMOVN : Vector Saturating Narrowing Move
1650defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1651 int_arm_neon_vqmovns>;
1652defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1653 int_arm_neon_vqmovnu>;
1654defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1655 int_arm_neon_vqmovnsu>;
1656// VMOVL : Vector Lengthening Move
1657defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1658defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1659
1660// Vector Conversions.
1661
1662// VCVT : Vector Convert Between Floating-Point and Integers
1663def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1664 v2i32, v2f32, fp_to_sint>;
1665def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1666 v2i32, v2f32, fp_to_uint>;
1667def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1668 v2f32, v2i32, sint_to_fp>;
1669def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1670 v2f32, v2i32, uint_to_fp>;
1671
1672def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1673 v4i32, v4f32, fp_to_sint>;
1674def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1675 v4i32, v4f32, fp_to_uint>;
1676def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1677 v4f32, v4i32, sint_to_fp>;
1678def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1679 v4f32, v4i32, uint_to_fp>;
1680
1681// VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1682// Note: Some of the opcode bits in the following VCVT instructions need to
1683// be encoded based on the immed values.
1684def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1685 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1686def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1687 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1688def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1689 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1690def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1691 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1692
1693def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1694 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1695def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1696 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1697def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1698 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1699def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1700 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1701
Bob Wilsonc1cd72e2009-07-26 00:39:34 +0000[diff] [blame]1702// VREV : Vector Reverse
1703
1704def vrev64_shuffle : PatFrag<(ops node:$in),
1705 (vector_shuffle node:$in, undef), [{
1706 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1707 return ARM::isVREVMask(SVOp, 64);
1708}]>;
1709
1710def vrev32_shuffle : PatFrag<(ops node:$in),
1711 (vector_shuffle node:$in, undef), [{
1712 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1713 return ARM::isVREVMask(SVOp, 32);
1714}]>;
1715
1716def vrev16_shuffle : PatFrag<(ops node:$in),
1717 (vector_shuffle node:$in, undef), [{
1718 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1719 return ARM::isVREVMask(SVOp, 16);
1720}]>;
1721
1722// VREV64 : Vector Reverse elements within 64-bit doublewords
1723
1724class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1725 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1726 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1727 [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>;
1728class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1729 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1730 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1731 [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>;
1732
1733def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1734def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1735def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1736def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1737
1738def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1739def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1740def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1741def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1742
1743// VREV32 : Vector Reverse elements within 32-bit words
1744
1745class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1746 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1747 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1748 [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>;
1749class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1750 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1751 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1752 [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>;
1753
1754def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1755def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1756
1757def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1758def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1759
1760// VREV16 : Vector Reverse elements within 16-bit halfwords
1761
1762class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1763 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1764 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1765 [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>;
1766class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1767 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1768 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1769 [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>;
1770
1771def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1772def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1773
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]1774//===----------------------------------------------------------------------===//
1775// Non-Instruction Patterns
1776//===----------------------------------------------------------------------===//
1777
1778// bit_convert
1779def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
1780def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
1781def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
1782def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
1783def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
1784def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
1785def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
1786def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
1787def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
1788def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
1789def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
1790def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
1791def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
1792def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
1793def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
1794def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
1795def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
1796def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
1797def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
1798def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
1799def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
1800def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
1801def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
1802def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
1803def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
1804def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
1805def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
1806def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
1807def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
1808def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
1809
1810def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
1811def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
1812def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
1813def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
1814def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
1815def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
1816def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
1817def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
1818def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
1819def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
1820def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
1821def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
1822def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
1823def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
1824def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
1825def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
1826def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
1827def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
1828def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
1829def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
1830def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
1831def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
1832def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
1833def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
1834def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
1835def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
1836def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
1837def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
1838def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
1839def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;