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gerrit-public.fairphone.software / platform / external / llvm / d2a2e002bfb53b66ab5f5421e9bcf5ff319e09a6 / . / lib / Target / ARM / ARMInstrNEON.td
blob: 5e8a4b5994fa7d15dfbe9e8ff9115d1760cb150b [file] [log] [blame]
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]1//===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the ARM NEON instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// NEON-specific DAG Nodes.
16//===----------------------------------------------------------------------===//
17
18def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19
20def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
26
27// Types for vector shift by immediates. The "SHX" version is for long and
28// narrow operations where the source and destination vectors have different
29// types. The "SHINS" version is for shift and insert operations.
30def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
31 SDTCisVT<2, i32>]>;
32def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
33 SDTCisVT<2, i32>]>;
34def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
36
37def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
44
45def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
48
49def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
55
56def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
59
60def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
62
63def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
64 SDTCisVT<2, i32>]>;
65def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
67
68def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
70
Bob Wilsond2a2e002009-08-04 00:36:16 +0000[diff] [blame^]71def SDTARMVLD : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
72def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD,
73 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
74def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD,
75 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
76def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD,
77 [SDNPHasChain, SDNPOutFlag, SDNPMayLoad]>;
78
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]79//===----------------------------------------------------------------------===//
80// NEON operand definitions
81//===----------------------------------------------------------------------===//
82
83// addrmode_neonldstm := reg
84//
85/* TODO: Take advantage of vldm.
86def addrmode_neonldstm : Operand<i32>,
87 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
88 let PrintMethod = "printAddrNeonLdStMOperand";
89 let MIOperandInfo = (ops GPR, i32imm);
90}
91*/
92
93//===----------------------------------------------------------------------===//
94// NEON load / store instructions
95//===----------------------------------------------------------------------===//
96
97/* TODO: Take advantage of vldm.
98let mayLoad = 1 in {
99def VLDMD : NI<(outs),
100 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
101 "vldm${addr:submode} ${addr:base}, $dst1",
Evan Chengdabc6c02009-07-08 22:51:32 +0000[diff] [blame]102 []> {
103 let Inst{27-25} = 0b110;
104 let Inst{20} = 1;
105 let Inst{11-9} = 0b101;
106}
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]107
108def VLDMS : NI<(outs),
109 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
110 "vldm${addr:submode} ${addr:base}, $dst1",
Evan Chengdabc6c02009-07-08 22:51:32 +0000[diff] [blame]111 []> {
112 let Inst{27-25} = 0b110;
113 let Inst{20} = 1;
114 let Inst{11-9} = 0b101;
115}
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]116}
117*/
118
119// Use vldmia to load a Q register as a D register pair.
120def VLDRQ : NI<(outs QPR:$dst), (ins GPR:$addr),
121 "vldmia $addr, ${dst:dregpair}",
Evan Chengdabc6c02009-07-08 22:51:32 +0000[diff] [blame]122 [(set QPR:$dst, (v2f64 (load GPR:$addr)))]> {
123 let Inst{27-25} = 0b110;
124 let Inst{24} = 0; // P bit
125 let Inst{23} = 1; // U bit
126 let Inst{20} = 1;
127 let Inst{11-9} = 0b101;
128}
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]129
130// Use vstmia to store a Q register as a D register pair.
131def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr),
132 "vstmia $addr, ${src:dregpair}",
Evan Chengdabc6c02009-07-08 22:51:32 +0000[diff] [blame]133 [(store (v2f64 QPR:$src), GPR:$addr)]> {
134 let Inst{27-25} = 0b110;
135 let Inst{24} = 0; // P bit
136 let Inst{23} = 1; // U bit
137 let Inst{20} = 0;
138 let Inst{11-9} = 0b101;
139}
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]140
141
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]142// VLD1 : Vector Load (multiple single elements)
143class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
144 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
145 !strconcat(OpcodeStr, "\t${dst:dregsingle}, $addr"),
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]146 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]147class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
148 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
149 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]150 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]151
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]152def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1i>;
153def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1i>;
154def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1i>;
155def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1f>;
156def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1i>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]157
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]158def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1i>;
159def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1i>;
160def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1i>;
161def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1f>;
162def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]163
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]164// VST1 : Vector Store (multiple single elements)
165class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
166 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
167 !strconcat(OpcodeStr, "\t${src:dregsingle}, $addr"),
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]168 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]169class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
170 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
171 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]172 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]173
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]174def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1i>;
175def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1i>;
176def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1i>;
177def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1f>;
178def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1i>;
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]179
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]180def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1i>;
181def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1i>;
182def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>;
183def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>;
184def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>;
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]185
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]186
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]187//===----------------------------------------------------------------------===//
188// NEON pattern fragments
189//===----------------------------------------------------------------------===//
190
191// Extract D sub-registers of Q registers.
192// (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
193def SubReg_i8_reg : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
195}]>;
196def SubReg_i16_reg : SDNodeXForm<imm, [{
197 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
198}]>;
199def SubReg_i32_reg : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
201}]>;
202def SubReg_f64_reg : SDNodeXForm<imm, [{
203 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
204}]>;
205
206// Translate lane numbers from Q registers to D subregs.
207def SubReg_i8_lane : SDNodeXForm<imm, [{
208 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
209}]>;
210def SubReg_i16_lane : SDNodeXForm<imm, [{
211 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
212}]>;
213def SubReg_i32_lane : SDNodeXForm<imm, [{
214 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
215}]>;
216
217//===----------------------------------------------------------------------===//
218// Instruction Classes
219//===----------------------------------------------------------------------===//
220
221// Basic 2-register operations, both double- and quad-register.
222class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
223 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
224 ValueType ResTy, ValueType OpTy, SDNode OpNode>
225 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
226 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
227 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
228class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
229 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
230 ValueType ResTy, ValueType OpTy, SDNode OpNode>
231 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
232 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
233 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
234
235// Basic 2-register intrinsics, both double- and quad-register.
236class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
237 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
238 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
239 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
240 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
241 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
242class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
243 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
244 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
245 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
246 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
247 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
248
249// Narrow 2-register intrinsics.
250class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
251 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
252 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
253 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
254 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
255 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
256
257// Long 2-register intrinsics. (This is currently only used for VMOVL and is
258// derived from N2VImm instead of N2V because of the way the size is encoded.)
259class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
260 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
261 Intrinsic IntOp>
262 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
263 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
264 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
265
266// Basic 3-register operations, both double- and quad-register.
267class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
268 string OpcodeStr, ValueType ResTy, ValueType OpTy,
269 SDNode OpNode, bit Commutable>
270 : N3V<op24, op23, op21_20, op11_8, 0, op4,
271 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
272 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
273 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
274 let isCommutable = Commutable;
275}
276class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
277 string OpcodeStr, ValueType ResTy, ValueType OpTy,
278 SDNode OpNode, bit Commutable>
279 : N3V<op24, op23, op21_20, op11_8, 1, op4,
280 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
281 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
282 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
283 let isCommutable = Commutable;
284}
285
286// Basic 3-register intrinsics, both double- and quad-register.
287class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
288 string OpcodeStr, ValueType ResTy, ValueType OpTy,
289 Intrinsic IntOp, bit Commutable>
290 : N3V<op24, op23, op21_20, op11_8, 0, op4,
291 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
292 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
293 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
294 let isCommutable = Commutable;
295}
296class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
297 string OpcodeStr, ValueType ResTy, ValueType OpTy,
298 Intrinsic IntOp, bit Commutable>
299 : N3V<op24, op23, op21_20, op11_8, 1, op4,
300 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
301 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
302 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
303 let isCommutable = Commutable;
304}
305
306// Multiply-Add/Sub operations, both double- and quad-register.
307class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
308 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
309 : N3V<op24, op23, op21_20, op11_8, 0, op4,
310 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
311 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
312 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
313 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
314class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
315 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
316 : N3V<op24, op23, op21_20, op11_8, 1, op4,
317 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
318 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
319 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
320 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
321
322// Neon 3-argument intrinsics, both double- and quad-register.
323// The destination register is also used as the first source operand register.
324class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
325 string OpcodeStr, ValueType ResTy, ValueType OpTy,
326 Intrinsic IntOp>
327 : N3V<op24, op23, op21_20, op11_8, 0, op4,
328 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
329 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
330 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
331 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
332class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
333 string OpcodeStr, ValueType ResTy, ValueType OpTy,
334 Intrinsic IntOp>
335 : N3V<op24, op23, op21_20, op11_8, 1, op4,
336 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
337 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
338 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
339 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
340
341// Neon Long 3-argument intrinsic. The destination register is
342// a quad-register and is also used as the first source operand register.
343class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
344 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
345 : N3V<op24, op23, op21_20, op11_8, 0, op4,
346 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3),
347 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
348 [(set QPR:$dst,
349 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
350
351// Narrowing 3-register intrinsics.
352class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
353 string OpcodeStr, ValueType TyD, ValueType TyQ,
354 Intrinsic IntOp, bit Commutable>
355 : N3V<op24, op23, op21_20, op11_8, 0, op4,
356 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2),
357 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
358 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
359 let isCommutable = Commutable;
360}
361
362// Long 3-register intrinsics.
363class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
364 string OpcodeStr, ValueType TyQ, ValueType TyD,
365 Intrinsic IntOp, bit Commutable>
366 : N3V<op24, op23, op21_20, op11_8, 0, op4,
367 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2),
368 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
369 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
370 let isCommutable = Commutable;
371}
372
373// Wide 3-register intrinsics.
374class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
375 string OpcodeStr, ValueType TyQ, ValueType TyD,
376 Intrinsic IntOp, bit Commutable>
377 : N3V<op24, op23, op21_20, op11_8, 0, op4,
378 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2),
379 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
380 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
381 let isCommutable = Commutable;
382}
383
384// Pairwise long 2-register intrinsics, both double- and quad-register.
385class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
386 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
387 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
388 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
389 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
390 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
391class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
392 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
393 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
394 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
395 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
396 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
397
398// Pairwise long 2-register accumulate intrinsics,
399// both double- and quad-register.
400// The destination register is also used as the first source operand register.
401class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
402 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
403 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
404 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
405 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
406 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
407 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
408class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
409 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
410 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
411 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
412 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
413 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
414 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
415
416// Shift by immediate,
417// both double- and quad-register.
418class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
419 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
420 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
421 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM),
422 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
423 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
424class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
425 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
426 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
427 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM),
428 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
429 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
430
431// Long shift by immediate.
432class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
433 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
434 ValueType OpTy, SDNode OpNode>
435 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
436 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM),
437 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
438 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
439 (i32 imm:$SIMM))))]>;
440
441// Narrow shift by immediate.
442class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
443 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
444 ValueType OpTy, SDNode OpNode>
445 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
446 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM),
447 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
448 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
449 (i32 imm:$SIMM))))]>;
450
451// Shift right by immediate and accumulate,
452// both double- and quad-register.
453class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
454 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
455 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
456 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
457 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
458 [(set DPR:$dst, (Ty (add DPR:$src1,
459 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
460class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
461 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
462 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
463 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
464 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
465 [(set QPR:$dst, (Ty (add QPR:$src1,
466 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
467
468// Shift by immediate and insert,
469// both double- and quad-register.
470class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
471 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
472 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
473 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
474 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
475 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
476class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
477 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
478 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
479 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
480 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
481 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
482
483// Convert, with fractional bits immediate,
484// both double- and quad-register.
485class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
486 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
487 Intrinsic IntOp>
488 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
489 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM),
490 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
491 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
492class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
493 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
494 Intrinsic IntOp>
495 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
496 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM),
497 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
498 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
499
500//===----------------------------------------------------------------------===//
501// Multiclasses
502//===----------------------------------------------------------------------===//
503
504// Neon 3-register vector operations.
505
506// First with only element sizes of 8, 16 and 32 bits:
507multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
508 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
509 // 64-bit vector types.
510 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
511 v8i8, v8i8, OpNode, Commutable>;
512 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
513 v4i16, v4i16, OpNode, Commutable>;
514 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
515 v2i32, v2i32, OpNode, Commutable>;
516
517 // 128-bit vector types.
518 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
519 v16i8, v16i8, OpNode, Commutable>;
520 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
521 v8i16, v8i16, OpNode, Commutable>;
522 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
523 v4i32, v4i32, OpNode, Commutable>;
524}
525
526// ....then also with element size 64 bits:
527multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
528 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
529 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
530 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
531 v1i64, v1i64, OpNode, Commutable>;
532 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
533 v2i64, v2i64, OpNode, Commutable>;
534}
535
536
537// Neon Narrowing 2-register vector intrinsics,
538// source operand element sizes of 16, 32 and 64 bits:
539multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
540 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
541 Intrinsic IntOp> {
542 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
543 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
544 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
545 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
546 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
547 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
548}
549
550
551// Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
552// source operand element sizes of 16, 32 and 64 bits:
553multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
554 bit op4, string OpcodeStr, Intrinsic IntOp> {
555 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
556 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
557 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
558 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
559 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
560 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
561}
562
563
564// Neon 3-register vector intrinsics.
565
566// First with only element sizes of 16 and 32 bits:
567multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
568 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
569 // 64-bit vector types.
570 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
571 v4i16, v4i16, IntOp, Commutable>;
572 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
573 v2i32, v2i32, IntOp, Commutable>;
574
575 // 128-bit vector types.
576 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
577 v8i16, v8i16, IntOp, Commutable>;
578 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
579 v4i32, v4i32, IntOp, Commutable>;
580}
581
582// ....then also with element size of 8 bits:
583multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
584 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
585 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
586 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
587 v8i8, v8i8, IntOp, Commutable>;
588 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
589 v16i8, v16i8, IntOp, Commutable>;
590}
591
592// ....then also with element size of 64 bits:
593multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
594 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
595 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
596 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
597 v1i64, v1i64, IntOp, Commutable>;
598 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
599 v2i64, v2i64, IntOp, Commutable>;
600}
601
602
603// Neon Narrowing 3-register vector intrinsics,
604// source operand element sizes of 16, 32 and 64 bits:
605multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
606 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
607 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
608 v8i8, v8i16, IntOp, Commutable>;
609 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
610 v4i16, v4i32, IntOp, Commutable>;
611 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
612 v2i32, v2i64, IntOp, Commutable>;
613}
614
615
616// Neon Long 3-register vector intrinsics.
617
618// First with only element sizes of 16 and 32 bits:
619multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
620 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
621 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
622 v4i32, v4i16, IntOp, Commutable>;
623 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
624 v2i64, v2i32, IntOp, Commutable>;
625}
626
627// ....then also with element size of 8 bits:
628multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
629 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
630 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
631 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
632 v8i16, v8i8, IntOp, Commutable>;
633}
634
635
636// Neon Wide 3-register vector intrinsics,
637// source operand element sizes of 8, 16 and 32 bits:
638multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
639 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
640 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
641 v8i16, v8i8, IntOp, Commutable>;
642 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
643 v4i32, v4i16, IntOp, Commutable>;
644 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
645 v2i64, v2i32, IntOp, Commutable>;
646}
647
648
649// Neon Multiply-Op vector operations,
650// element sizes of 8, 16 and 32 bits:
651multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
652 string OpcodeStr, SDNode OpNode> {
653 // 64-bit vector types.
654 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
655 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
656 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
657 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
658 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
659 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
660
661 // 128-bit vector types.
662 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
663 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
664 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
665 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
666 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
667 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
668}
669
670
671// Neon 3-argument intrinsics,
672// element sizes of 8, 16 and 32 bits:
673multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
674 string OpcodeStr, Intrinsic IntOp> {
675 // 64-bit vector types.
676 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
677 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
678 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
679 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
680 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
681 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
682
683 // 128-bit vector types.
684 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
685 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
686 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
687 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
688 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
689 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
690}
691
692
693// Neon Long 3-argument intrinsics.
694
695// First with only element sizes of 16 and 32 bits:
696multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
697 string OpcodeStr, Intrinsic IntOp> {
698 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
699 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
700 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
701 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
702}
703
704// ....then also with element size of 8 bits:
705multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
706 string OpcodeStr, Intrinsic IntOp>
707 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
708 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
709 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
710}
711
712
713// Neon 2-register vector intrinsics,
714// element sizes of 8, 16 and 32 bits:
715multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
716 bits<5> op11_7, bit op4, string OpcodeStr,
717 Intrinsic IntOp> {
718 // 64-bit vector types.
719 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
720 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
721 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
722 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
723 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
724 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
725
726 // 128-bit vector types.
727 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
728 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
729 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
730 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
731 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
732 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
733}
734
735
736// Neon Pairwise long 2-register intrinsics,
737// element sizes of 8, 16 and 32 bits:
738multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
739 bits<5> op11_7, bit op4,
740 string OpcodeStr, Intrinsic IntOp> {
741 // 64-bit vector types.
742 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
743 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
744 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
745 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
746 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
747 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
748
749 // 128-bit vector types.
750 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
751 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
752 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
753 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
754 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
755 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
756}
757
758
759// Neon Pairwise long 2-register accumulate intrinsics,
760// element sizes of 8, 16 and 32 bits:
761multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
762 bits<5> op11_7, bit op4,
763 string OpcodeStr, Intrinsic IntOp> {
764 // 64-bit vector types.
765 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
766 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
767 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
768 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
769 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
770 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
771
772 // 128-bit vector types.
773 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
774 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
775 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
776 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
777 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
778 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
779}
780
781
782// Neon 2-register vector shift by immediate,
783// element sizes of 8, 16, 32 and 64 bits:
784multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
785 string OpcodeStr, SDNode OpNode> {
786 // 64-bit vector types.
787 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
788 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
789 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
790 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
791 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
792 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
793 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
794 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
795
796 // 128-bit vector types.
797 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
798 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
799 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
800 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
801 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
802 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
803 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
804 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
805}
806
807
808// Neon Shift-Accumulate vector operations,
809// element sizes of 8, 16, 32 and 64 bits:
810multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
811 string OpcodeStr, SDNode ShOp> {
812 // 64-bit vector types.
813 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
814 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
815 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
816 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
817 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
818 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
819 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
820 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
821
822 // 128-bit vector types.
823 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
824 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
825 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
826 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
827 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
828 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
829 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
830 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
831}
832
833
834// Neon Shift-Insert vector operations,
835// element sizes of 8, 16, 32 and 64 bits:
836multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
837 string OpcodeStr, SDNode ShOp> {
838 // 64-bit vector types.
839 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
840 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
841 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
842 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
843 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
844 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
845 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
846 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
847
848 // 128-bit vector types.
849 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
850 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
851 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
852 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
853 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
854 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
855 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
856 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
857}
858
859//===----------------------------------------------------------------------===//
860// Instruction Definitions.
861//===----------------------------------------------------------------------===//
862
863// Vector Add Operations.
864
865// VADD : Vector Add (integer and floating-point)
866defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
867def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
868def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
869// VADDL : Vector Add Long (Q = D + D)
870defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
871defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
872// VADDW : Vector Add Wide (Q = Q + D)
873defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
874defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
875// VHADD : Vector Halving Add
876defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
877defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
878// VRHADD : Vector Rounding Halving Add
879defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
880defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
881// VQADD : Vector Saturating Add
882defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
883defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
884// VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
885defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
886// VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
887defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
888
889// Vector Multiply Operations.
890
891// VMUL : Vector Multiply (integer, polynomial and floating-point)
892defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
893def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
894 int_arm_neon_vmulp, 1>;
895def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
896 int_arm_neon_vmulp, 1>;
897def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
898def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
899// VQDMULH : Vector Saturating Doubling Multiply Returning High Half
900defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
901// VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
902defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
903// VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
904defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
905defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
906def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
907 int_arm_neon_vmullp, 1>;
908// VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
909defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
910
911// Vector Multiply-Accumulate and Multiply-Subtract Operations.
912
913// VMLA : Vector Multiply Accumulate (integer and floating-point)
914defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
915def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
916def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
917// VMLAL : Vector Multiply Accumulate Long (Q += D * D)
918defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
919defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
920// VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
921defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
922// VMLS : Vector Multiply Subtract (integer and floating-point)
923defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
924def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
925def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
926// VMLSL : Vector Multiply Subtract Long (Q -= D * D)
927defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
928defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
929// VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
930defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
931
932// Vector Subtract Operations.
933
934// VSUB : Vector Subtract (integer and floating-point)
935defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
936def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
937def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
938// VSUBL : Vector Subtract Long (Q = D - D)
939defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
940defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
941// VSUBW : Vector Subtract Wide (Q = Q - D)
942defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
943defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
944// VHSUB : Vector Halving Subtract
945defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
946defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
947// VQSUB : Vector Saturing Subtract
948defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
949defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
950// VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
951defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
952// VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
953defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
954
955// Vector Comparisons.
956
957// VCEQ : Vector Compare Equal
958defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
959def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
960def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
961// VCGE : Vector Compare Greater Than or Equal
962defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
963defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
964def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
965def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
966// VCGT : Vector Compare Greater Than
967defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
968defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
969def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
970def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
971// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
972def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
973 int_arm_neon_vacged, 0>;
974def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
975 int_arm_neon_vacgeq, 0>;
976// VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
977def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
978 int_arm_neon_vacgtd, 0>;
979def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
980 int_arm_neon_vacgtq, 0>;
981// VTST : Vector Test Bits
982defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
983
984// Vector Bitwise Operations.
985
986// VAND : Vector Bitwise AND
987def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
988def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
989
990// VEOR : Vector Bitwise Exclusive OR
991def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
992def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
993
994// VORR : Vector Bitwise OR
995def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
996def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
997
998// VBIC : Vector Bitwise Bit Clear (AND NOT)
999def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1000 (ins DPR:$src1, DPR:$src2), "vbic\t$dst, $src1, $src2", "",
1001 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1002def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1003 (ins QPR:$src1, QPR:$src2), "vbic\t$dst, $src1, $src2", "",
1004 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1005
1006// VORN : Vector Bitwise OR NOT
1007def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1008 (ins DPR:$src1, DPR:$src2), "vorn\t$dst, $src1, $src2", "",
1009 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1010def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1011 (ins QPR:$src1, QPR:$src2), "vorn\t$dst, $src1, $src2", "",
1012 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1013
1014// VMVN : Vector Bitwise NOT
1015def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1016 (outs DPR:$dst), (ins DPR:$src), "vmvn\t$dst, $src", "",
1017 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1018def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1019 (outs QPR:$dst), (ins QPR:$src), "vmvn\t$dst, $src", "",
1020 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1021def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1022def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1023
1024// VBSL : Vector Bitwise Select
1025def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1026 (ins DPR:$src1, DPR:$src2, DPR:$src3),
1027 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1028 [(set DPR:$dst,
1029 (v2i32 (or (and DPR:$src2, DPR:$src1),
1030 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1031def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1032 (ins QPR:$src1, QPR:$src2, QPR:$src3),
1033 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1034 [(set QPR:$dst,
1035 (v4i32 (or (and QPR:$src2, QPR:$src1),
1036 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1037
1038// VBIF : Vector Bitwise Insert if False
1039// like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1040// VBIT : Vector Bitwise Insert if True
1041// like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1042// These are not yet implemented. The TwoAddress pass will not go looking
1043// for equivalent operations with different register constraints; it just
1044// inserts copies.
1045
1046// Vector Absolute Differences.
1047
1048// VABD : Vector Absolute Difference
1049defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1050defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1051def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1052 int_arm_neon_vabdf, 0>;
1053def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1054 int_arm_neon_vabdf, 0>;
1055
1056// VABDL : Vector Absolute Difference Long (Q = | D - D |)
1057defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1058defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1059
1060// VABA : Vector Absolute Difference and Accumulate
1061defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1062defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1063
1064// VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1065defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1066defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1067
1068// Vector Maximum and Minimum.
1069
1070// VMAX : Vector Maximum
1071defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1072defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1073def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1074 int_arm_neon_vmaxf, 1>;
1075def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1076 int_arm_neon_vmaxf, 1>;
1077
1078// VMIN : Vector Minimum
1079defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1080defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1081def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1082 int_arm_neon_vminf, 1>;
1083def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1084 int_arm_neon_vminf, 1>;
1085
1086// Vector Pairwise Operations.
1087
1088// VPADD : Vector Pairwise Add
1089def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1090 int_arm_neon_vpaddi, 0>;
1091def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1092 int_arm_neon_vpaddi, 0>;
1093def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1094 int_arm_neon_vpaddi, 0>;
1095def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1096 int_arm_neon_vpaddf, 0>;
1097
1098// VPADDL : Vector Pairwise Add Long
1099defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1100 int_arm_neon_vpaddls>;
1101defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1102 int_arm_neon_vpaddlu>;
1103
1104// VPADAL : Vector Pairwise Add and Accumulate Long
1105defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1106 int_arm_neon_vpadals>;
1107defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1108 int_arm_neon_vpadalu>;
1109
1110// VPMAX : Vector Pairwise Maximum
1111def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1112 int_arm_neon_vpmaxs, 0>;
1113def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1114 int_arm_neon_vpmaxs, 0>;
1115def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1116 int_arm_neon_vpmaxs, 0>;
1117def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1118 int_arm_neon_vpmaxu, 0>;
1119def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1120 int_arm_neon_vpmaxu, 0>;
1121def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1122 int_arm_neon_vpmaxu, 0>;
1123def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1124 int_arm_neon_vpmaxf, 0>;
1125
1126// VPMIN : Vector Pairwise Minimum
1127def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1128 int_arm_neon_vpmins, 0>;
1129def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1130 int_arm_neon_vpmins, 0>;
1131def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1132 int_arm_neon_vpmins, 0>;
1133def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1134 int_arm_neon_vpminu, 0>;
1135def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1136 int_arm_neon_vpminu, 0>;
1137def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1138 int_arm_neon_vpminu, 0>;
1139def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1140 int_arm_neon_vpminf, 0>;
1141
1142// Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1143
1144// VRECPE : Vector Reciprocal Estimate
1145def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1146 v2i32, v2i32, int_arm_neon_vrecpe>;
1147def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1148 v4i32, v4i32, int_arm_neon_vrecpe>;
1149def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1150 v2f32, v2f32, int_arm_neon_vrecpef>;
1151def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1152 v4f32, v4f32, int_arm_neon_vrecpef>;
1153
1154// VRECPS : Vector Reciprocal Step
1155def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1156 int_arm_neon_vrecps, 1>;
1157def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1158 int_arm_neon_vrecps, 1>;
1159
1160// VRSQRTE : Vector Reciprocal Square Root Estimate
1161def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1162 v2i32, v2i32, int_arm_neon_vrsqrte>;
1163def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1164 v4i32, v4i32, int_arm_neon_vrsqrte>;
1165def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1166 v2f32, v2f32, int_arm_neon_vrsqrtef>;
1167def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1168 v4f32, v4f32, int_arm_neon_vrsqrtef>;
1169
1170// VRSQRTS : Vector Reciprocal Square Root Step
1171def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1172 int_arm_neon_vrsqrts, 1>;
1173def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1174 int_arm_neon_vrsqrts, 1>;
1175
1176// Vector Shifts.
1177
1178// VSHL : Vector Shift
1179defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1180defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1181// VSHL : Vector Shift Left (Immediate)
1182defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1183// VSHR : Vector Shift Right (Immediate)
1184defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1185defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1186
1187// VSHLL : Vector Shift Left Long
1188def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1189 v8i16, v8i8, NEONvshlls>;
1190def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1191 v4i32, v4i16, NEONvshlls>;
1192def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1193 v2i64, v2i32, NEONvshlls>;
1194def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1195 v8i16, v8i8, NEONvshllu>;
1196def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1197 v4i32, v4i16, NEONvshllu>;
1198def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1199 v2i64, v2i32, NEONvshllu>;
1200
1201// VSHLL : Vector Shift Left Long (with maximum shift count)
1202def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1203 v8i16, v8i8, NEONvshlli>;
1204def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1205 v4i32, v4i16, NEONvshlli>;
1206def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1207 v2i64, v2i32, NEONvshlli>;
1208
1209// VSHRN : Vector Shift Right and Narrow
1210def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1211 v8i8, v8i16, NEONvshrn>;
1212def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1213 v4i16, v4i32, NEONvshrn>;
1214def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1215 v2i32, v2i64, NEONvshrn>;
1216
1217// VRSHL : Vector Rounding Shift
1218defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1219defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1220// VRSHR : Vector Rounding Shift Right
1221defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1222defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1223
1224// VRSHRN : Vector Rounding Shift Right and Narrow
1225def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1226 v8i8, v8i16, NEONvrshrn>;
1227def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1228 v4i16, v4i32, NEONvrshrn>;
1229def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1230 v2i32, v2i64, NEONvrshrn>;
1231
1232// VQSHL : Vector Saturating Shift
1233defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1234defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1235// VQSHL : Vector Saturating Shift Left (Immediate)
1236defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1237defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1238// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1239defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1240
1241// VQSHRN : Vector Saturating Shift Right and Narrow
1242def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1243 v8i8, v8i16, NEONvqshrns>;
1244def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1245 v4i16, v4i32, NEONvqshrns>;
1246def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1247 v2i32, v2i64, NEONvqshrns>;
1248def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1249 v8i8, v8i16, NEONvqshrnu>;
1250def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1251 v4i16, v4i32, NEONvqshrnu>;
1252def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1253 v2i32, v2i64, NEONvqshrnu>;
1254
1255// VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1256def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1257 v8i8, v8i16, NEONvqshrnsu>;
1258def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1259 v4i16, v4i32, NEONvqshrnsu>;
1260def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1261 v2i32, v2i64, NEONvqshrnsu>;
1262
1263// VQRSHL : Vector Saturating Rounding Shift
1264defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1265 int_arm_neon_vqrshifts, 0>;
1266defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1267 int_arm_neon_vqrshiftu, 0>;
1268
1269// VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1270def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1271 v8i8, v8i16, NEONvqrshrns>;
1272def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1273 v4i16, v4i32, NEONvqrshrns>;
1274def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1275 v2i32, v2i64, NEONvqrshrns>;
1276def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1277 v8i8, v8i16, NEONvqrshrnu>;
1278def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1279 v4i16, v4i32, NEONvqrshrnu>;
1280def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1281 v2i32, v2i64, NEONvqrshrnu>;
1282
1283// VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1284def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1285 v8i8, v8i16, NEONvqrshrnsu>;
1286def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1287 v4i16, v4i32, NEONvqrshrnsu>;
1288def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1289 v2i32, v2i64, NEONvqrshrnsu>;
1290
1291// VSRA : Vector Shift Right and Accumulate
1292defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1293defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1294// VRSRA : Vector Rounding Shift Right and Accumulate
1295defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1296defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1297
1298// VSLI : Vector Shift Left and Insert
1299defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1300// VSRI : Vector Shift Right and Insert
1301defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1302
1303// Vector Absolute and Saturating Absolute.
1304
1305// VABS : Vector Absolute Value
1306defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1307 int_arm_neon_vabs>;
1308def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1309 v2f32, v2f32, int_arm_neon_vabsf>;
1310def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1311 v4f32, v4f32, int_arm_neon_vabsf>;
1312
1313// VQABS : Vector Saturating Absolute Value
1314defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1315 int_arm_neon_vqabs>;
1316
1317// Vector Negate.
1318
1319def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1320def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1321
1322class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1323 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1324 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1325 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1326class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1327 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1328 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1329 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1330
1331// VNEG : Vector Negate
1332def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1333def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1334def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1335def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1336def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1337def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1338
1339// VNEG : Vector Negate (floating-point)
1340def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1341 (outs DPR:$dst), (ins DPR:$src), "vneg.f32\t$dst, $src", "",
1342 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1343def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1344 (outs QPR:$dst), (ins QPR:$src), "vneg.f32\t$dst, $src", "",
1345 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1346
1347def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1348def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1349def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1350def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1351def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1352def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1353
1354// VQNEG : Vector Saturating Negate
1355defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1356 int_arm_neon_vqneg>;
1357
1358// Vector Bit Counting Operations.
1359
1360// VCLS : Vector Count Leading Sign Bits
1361defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1362 int_arm_neon_vcls>;
1363// VCLZ : Vector Count Leading Zeros
1364defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1365 int_arm_neon_vclz>;
1366// VCNT : Vector Count One Bits
1367def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1368 v8i8, v8i8, int_arm_neon_vcnt>;
1369def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1370 v16i8, v16i8, int_arm_neon_vcnt>;
1371
1372// Vector Move Operations.
1373
1374// VMOV : Vector Move (Register)
1375
1376def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1377 "vmov\t$dst, $src", "", []>;
1378def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1379 "vmov\t$dst, $src", "", []>;
1380
1381// VMOV : Vector Move (Immediate)
1382
1383// VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1384def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1385 return ARM::getVMOVImm(N, 1, *CurDAG);
1386}]>;
1387def vmovImm8 : PatLeaf<(build_vector), [{
1388 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1389}], VMOV_get_imm8>;
1390
1391// VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1392def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1393 return ARM::getVMOVImm(N, 2, *CurDAG);
1394}]>;
1395def vmovImm16 : PatLeaf<(build_vector), [{
1396 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1397}], VMOV_get_imm16>;
1398
1399// VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1400def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1401 return ARM::getVMOVImm(N, 4, *CurDAG);
1402}]>;
1403def vmovImm32 : PatLeaf<(build_vector), [{
1404 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1405}], VMOV_get_imm32>;
1406
1407// VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1408def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1409 return ARM::getVMOVImm(N, 8, *CurDAG);
1410}]>;
1411def vmovImm64 : PatLeaf<(build_vector), [{
1412 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1413}], VMOV_get_imm64>;
1414
1415// Note: Some of the cmode bits in the following VMOV instructions need to
1416// be encoded based on the immed values.
1417
1418def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1419 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "",
1420 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1421def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1422 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "",
1423 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1424
1425def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1426 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "",
1427 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1428def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1429 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "",
1430 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1431
1432def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1433 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "",
1434 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1435def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1436 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "",
1437 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1438
1439def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1440 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "",
1441 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1442def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1443 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "",
1444 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1445
1446// VMOV : Vector Get Lane (move scalar to ARM core register)
1447
1448def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1449 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1450 "vmov", ".s8\t$dst, $src[$lane]",
1451 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1452 imm:$lane))]>;
1453def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1454 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1455 "vmov", ".s16\t$dst, $src[$lane]",
1456 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1457 imm:$lane))]>;
1458def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1459 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1460 "vmov", ".u8\t$dst, $src[$lane]",
1461 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1462 imm:$lane))]>;
1463def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1464 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1465 "vmov", ".u16\t$dst, $src[$lane]",
1466 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1467 imm:$lane))]>;
1468def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1469 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1470 "vmov", ".32\t$dst, $src[$lane]",
1471 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1472 imm:$lane))]>;
1473// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1474def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1475 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1476 (SubReg_i8_reg imm:$lane))),
1477 (SubReg_i8_lane imm:$lane))>;
1478def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1479 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1480 (SubReg_i16_reg imm:$lane))),
1481 (SubReg_i16_lane imm:$lane))>;
1482def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1483 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1484 (SubReg_i8_reg imm:$lane))),
1485 (SubReg_i8_lane imm:$lane))>;
1486def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1487 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1488 (SubReg_i16_reg imm:$lane))),
1489 (SubReg_i16_lane imm:$lane))>;
1490def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1491 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1492 (SubReg_i32_reg imm:$lane))),
1493 (SubReg_i32_lane imm:$lane))>;
1494//def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1495// (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1496def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1497 (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1498
1499
1500// VMOV : Vector Set Lane (move ARM core register to scalar)
1501
1502let Constraints = "$src1 = $dst" in {
1503def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1504 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1505 "vmov", ".8\t$dst[$lane], $src2",
1506 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1507 GPR:$src2, imm:$lane))]>;
1508def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1509 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1510 "vmov", ".16\t$dst[$lane], $src2",
1511 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1512 GPR:$src2, imm:$lane))]>;
1513def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1514 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1515 "vmov", ".32\t$dst[$lane], $src2",
1516 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1517 GPR:$src2, imm:$lane))]>;
1518}
1519def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1520 (v16i8 (INSERT_SUBREG QPR:$src1,
1521 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1522 (SubReg_i8_reg imm:$lane))),
1523 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1524 (SubReg_i8_reg imm:$lane)))>;
1525def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1526 (v8i16 (INSERT_SUBREG QPR:$src1,
1527 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1528 (SubReg_i16_reg imm:$lane))),
1529 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1530 (SubReg_i16_reg imm:$lane)))>;
1531def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1532 (v4i32 (INSERT_SUBREG QPR:$src1,
1533 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1534 (SubReg_i32_reg imm:$lane))),
1535 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1536 (SubReg_i32_reg imm:$lane)))>;
1537
1538//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1539// (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1540def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1541 (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1542
1543// VDUP : Vector Duplicate (from ARM core register to all elements)
1544
1545def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
1546 (vector_shuffle node:$lhs, node:$rhs), [{
1547 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1548 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
1549}]>;
1550
1551class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1552 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1553 "vdup", !strconcat(asmSize, "\t$dst, $src"),
1554 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1555class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1556 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1557 "vdup", !strconcat(asmSize, "\t$dst, $src"),
1558 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1559
1560def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1561def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1562def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1563def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1564def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1565def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1566
1567def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1568 "vdup", ".32\t$dst, $src",
1569 [(set DPR:$dst, (v2f32 (splat_lo
1570 (scalar_to_vector
1571 (f32 (bitconvert GPR:$src))),
1572 undef)))]>;
1573def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1574 "vdup", ".32\t$dst, $src",
1575 [(set QPR:$dst, (v4f32 (splat_lo
1576 (scalar_to_vector
1577 (f32 (bitconvert GPR:$src))),
1578 undef)))]>;
1579
1580// VDUP : Vector Duplicate Lane (from scalar to all elements)
1581
1582def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
1583 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1584 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
1585}]>;
1586
1587def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
1588 (vector_shuffle node:$lhs, node:$rhs), [{
1589 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1590 return SVOp->isSplat();
1591}], SHUFFLE_get_splat_lane>;
1592
1593class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1594 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1595 (outs DPR:$dst), (ins DPR:$src, i32imm:$lane),
1596 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1597 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
1598
1599// vector_shuffle requires that the source and destination types match, so
1600// VDUP to a 128-bit result uses a target-specific VDUPLANEQ node.
1601class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1602 ValueType ResTy, ValueType OpTy>
1603 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1604 (outs QPR:$dst), (ins DPR:$src, i32imm:$lane),
1605 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1606 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
1607
1608def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1609def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1610def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1611def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1612def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1613def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1614def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1615def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1616
1617// VMOVN : Vector Narrowing Move
1618defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1619 int_arm_neon_vmovn>;
1620// VQMOVN : Vector Saturating Narrowing Move
1621defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1622 int_arm_neon_vqmovns>;
1623defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1624 int_arm_neon_vqmovnu>;
1625defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1626 int_arm_neon_vqmovnsu>;
1627// VMOVL : Vector Lengthening Move
1628defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1629defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1630
1631// Vector Conversions.
1632
1633// VCVT : Vector Convert Between Floating-Point and Integers
1634def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1635 v2i32, v2f32, fp_to_sint>;
1636def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1637 v2i32, v2f32, fp_to_uint>;
1638def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1639 v2f32, v2i32, sint_to_fp>;
1640def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1641 v2f32, v2i32, uint_to_fp>;
1642
1643def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1644 v4i32, v4f32, fp_to_sint>;
1645def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1646 v4i32, v4f32, fp_to_uint>;
1647def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1648 v4f32, v4i32, sint_to_fp>;
1649def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1650 v4f32, v4i32, uint_to_fp>;
1651
1652// VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1653// Note: Some of the opcode bits in the following VCVT instructions need to
1654// be encoded based on the immed values.
1655def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1656 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1657def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1658 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1659def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1660 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1661def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1662 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1663
1664def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1665 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1666def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1667 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1668def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1669 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1670def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1671 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1672
Bob Wilsonc1cd72e2009-07-26 00:39:34 +0000[diff] [blame]1673// VREV : Vector Reverse
1674
1675def vrev64_shuffle : PatFrag<(ops node:$in),
1676 (vector_shuffle node:$in, undef), [{
1677 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1678 return ARM::isVREVMask(SVOp, 64);
1679}]>;
1680
1681def vrev32_shuffle : PatFrag<(ops node:$in),
1682 (vector_shuffle node:$in, undef), [{
1683 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1684 return ARM::isVREVMask(SVOp, 32);
1685}]>;
1686
1687def vrev16_shuffle : PatFrag<(ops node:$in),
1688 (vector_shuffle node:$in, undef), [{
1689 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1690 return ARM::isVREVMask(SVOp, 16);
1691}]>;
1692
1693// VREV64 : Vector Reverse elements within 64-bit doublewords
1694
1695class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1696 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1697 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1698 [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>;
1699class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1700 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1701 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1702 [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>;
1703
1704def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1705def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1706def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1707def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1708
1709def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1710def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1711def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1712def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1713
1714// VREV32 : Vector Reverse elements within 32-bit words
1715
1716class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1717 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1718 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1719 [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>;
1720class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1721 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1722 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1723 [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>;
1724
1725def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1726def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1727
1728def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1729def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1730
1731// VREV16 : Vector Reverse elements within 16-bit halfwords
1732
1733class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1734 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1735 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1736 [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>;
1737class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1738 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1739 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1740 [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>;
1741
1742def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1743def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1744
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]1745//===----------------------------------------------------------------------===//
1746// Non-Instruction Patterns
1747//===----------------------------------------------------------------------===//
1748
1749// bit_convert
1750def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
1751def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
1752def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
1753def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
1754def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
1755def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
1756def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
1757def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
1758def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
1759def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
1760def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
1761def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
1762def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
1763def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
1764def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
1765def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
1766def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
1767def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
1768def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
1769def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
1770def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
1771def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
1772def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
1773def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
1774def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
1775def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
1776def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
1777def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
1778def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
1779def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
1780
1781def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
1782def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
1783def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
1784def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
1785def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
1786def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
1787def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
1788def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
1789def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
1790def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
1791def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
1792def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
1793def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
1794def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
1795def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
1796def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
1797def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
1798def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
1799def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
1800def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
1801def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
1802def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
1803def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
1804def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
1805def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
1806def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
1807def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
1808def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
1809def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
1810def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;