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gerrit-public.fairphone.software / platform / external / llvm / c23b933d5f8be9b51a1d22e717c0311f65f87dcd / . / test / CodeGen / ARM / long_shift.ll
blob: a99a7ec86c1e12b8803bdcd410e0018a5201b654 [file] [log] [blame]
Jim Grosbach4a260922009-10-31 19:06:53 +0000[diff] [blame]1; RUN: llc < %s -march=arm | FileCheck %s
Evan Cheng02b985c2007-01-19 09:20:23 +0000[diff] [blame]2
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]3define i64 @f0(i64 %A, i64 %B) {
Jim Grosbach4a260922009-10-31 19:06:53 +0000[diff] [blame]4; CHECK: f0
Jim Grosbach7032f922010-10-14 22:57:13 +0000[diff] [blame]5; CHECK: lsrs r3, r3, #1
Jim Grosbach792e9792010-10-14 20:43:44 +0000[diff] [blame]6; CHECK-NEXT: rrx r2, r2
Jim Grosbach07d236b2009-10-31 21:52:58 +0000[diff] [blame]7; CHECK-NEXT: subs r0, r0, r2
8; CHECK-NEXT: sbc r1, r1, r3
Evan Cheng1091a972007-01-27 00:04:57 +0000[diff] [blame]9 %tmp = bitcast i64 %A to i64
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]10 %tmp2 = lshr i64 %B, 1
Evan Cheng1091a972007-01-27 00:04:57 +0000[diff] [blame]11 %tmp3 = sub i64 %tmp, %tmp2
12 ret i64 %tmp3
Evan Cheng02b985c2007-01-19 09:20:23 +0000[diff] [blame]13}
14
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]15define i32 @f1(i64 %x, i64 %y) {
Jim Grosbach4a260922009-10-31 19:06:53 +0000[diff] [blame]16; CHECK: f1
Jim Grosbach9ce75622010-09-17 21:58:46 +0000[diff] [blame]17; CHECK: lsl{{.*}}r2
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]18 %a = shl i64 %x, %y
Evan Cheng1091a972007-01-27 00:04:57 +0000[diff] [blame]19 %b = trunc i64 %a to i32
20 ret i32 %b
21}
22
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]23define i32 @f2(i64 %x, i64 %y) {
Jim Grosbach4a260922009-10-31 19:06:53 +0000[diff] [blame]24; CHECK: f2
Jim Grosbach9ce75622010-09-17 21:58:46 +0000[diff] [blame]25; CHECK: lsr{{.*}}r2
Dan Gohmanfe5e4da2010-06-24 22:23:02 +0000[diff] [blame]26; CHECK-NEXT: rsb r3, r2, #32
Evan Cheng2c339152011-03-23 22:52:04 +0000[diff] [blame]27; CHECK-NEXT: sub r2, r2, #32
Dan Gohmanfe5e4da2010-06-24 22:23:02 +0000[diff] [blame]28; CHECK-NEXT: orr r0, r0, r1, lsl r3
Evan Chengddfd1372011-12-14 02:11:42 +0000[diff] [blame]29; CHECK-NEXT: cmp r2, #0
Jim Grosbachd4a16ad2011-03-10 23:56:09 +0000[diff] [blame]30; CHECK-NEXT: asrge r0, r1, r2
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]31 %a = ashr i64 %x, %y
Evan Cheng1091a972007-01-27 00:04:57 +0000[diff] [blame]32 %b = trunc i64 %a to i32
33 ret i32 %b
34}
35
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]36define i32 @f3(i64 %x, i64 %y) {
Jim Grosbach4a260922009-10-31 19:06:53 +0000[diff] [blame]37; CHECK: f3
Jim Grosbach9ce75622010-09-17 21:58:46 +0000[diff] [blame]38; CHECK: lsr{{.*}}r2
Dan Gohmanfe5e4da2010-06-24 22:23:02 +0000[diff] [blame]39; CHECK-NEXT: rsb r3, r2, #32
Evan Cheng2c339152011-03-23 22:52:04 +0000[diff] [blame]40; CHECK-NEXT: sub r2, r2, #32
Dan Gohmanfe5e4da2010-06-24 22:23:02 +0000[diff] [blame]41; CHECK-NEXT: orr r0, r0, r1, lsl r3
Evan Chengddfd1372011-12-14 02:11:42 +0000[diff] [blame]42; CHECK-NEXT: cmp r2, #0
Jim Grosbachd4a16ad2011-03-10 23:56:09 +0000[diff] [blame]43; CHECK-NEXT: lsrge r0, r1, r2
Reid Spencer832254e2007-02-02 02:16:23 +0000[diff] [blame]44 %a = lshr i64 %x, %y
Evan Cheng1091a972007-01-27 00:04:57 +0000[diff] [blame]45 %b = trunc i64 %a to i32
46 ret i32 %b
47}