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gerrit-public.fairphone.software / platform / external / llvm / cba270d042862bca213b812656a2181b0de0578e / . / lib / Target / ARM / ARMISelLowering.h
blob: 81120c8d994bd4edd08a1ffb82f361ae3c4a1407 [file] [log] [blame]
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]18#include "ARMSubtarget.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]19#include "llvm/Target/TargetLowering.h"
20#include "llvm/CodeGen/SelectionDAG.h"
Bob Wilson1f595bb2009-04-17 19:07:39 +0000[diff] [blame]21#include "llvm/CodeGen/CallingConvLower.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]22#include <vector>
23
24namespace llvm {
25 class ARMConstantPoolValue;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]26
27 namespace ARMISD {
28 // ARM Specific DAG Nodes
29 enum NodeType {
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]30 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohman0ba2bcf2008-09-23 18:42:32 +0000[diff] [blame]31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]32
33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
34 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]36
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]37 CALL, // Function call.
Evan Cheng277f0742007-06-19 21:05:09 +0000[diff] [blame]38 CALL_PRED, // Function call that's predicable.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]39 CALL_NOLINK, // Function call with branch not branch-and-link.
40 tCALL, // Thumb function call.
41 BRCOND, // Conditional branch.
42 BR_JT, // Jumptable branch.
Evan Cheng5657c012009-07-29 02:18:14 +0000[diff] [blame]43 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]44 RET_FLAG, // Return with a flag operand.
45
46 PIC_ADD, // Add with a PC operand and a PIC label.
47
48 CMP, // ARM compare instructions.
David Goodwinc0309b42009-06-29 15:33:01 +0000[diff] [blame]49 CMPZ, // ARM compare that sets only Z flag.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]50 CMPFP, // ARM VFP compare instruction, sets FPSCR.
51 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
52 FMSTAT, // ARM fmstat instruction.
53 CMOV, // ARM conditional move instructions.
54 CNEG, // ARM conditional negate instructions.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]55
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]56 BCC_i64,
57
Jim Grosbach3482c802010-01-18 19:58:49 +0000[diff] [blame]58 RBIT, // ARM bitreverse instruction
59
Bob Wilson76a312b2010-03-19 22:51:32 +0000[diff] [blame]60 FTOSI, // FP to sint within a FP register.
61 FTOUI, // FP to uint within a FP register.
62 SITOF, // sint to FP within a FP register.
63 UITOF, // uint to FP within a FP register.
64
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]65 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
66 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
67 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]68
Jim Grosbache5165492009-11-09 00:11:35 +0000[diff] [blame]69 VMOVRRD, // double to two gprs.
70 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +0000[diff] [blame]71
Evan Cheng86198642009-08-07 00:34:42 +0000[diff] [blame]72 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
73 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
Jim Grosbach0e0da732009-05-12 23:59:14 +0000[diff] [blame]74
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]75 TC_RETURN, // Tail call return pseudo.
76
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]77 THREAD_POINTER,
78
Evan Cheng86198642009-08-07 00:34:42 +0000[diff] [blame]79 DYN_ALLOC, // Dynamic allocation on the stack.
80
Jim Grosbach3728e962009-12-10 00:11:09 +0000[diff] [blame]81 MEMBARRIER, // Memory barrier
82 SYNCBARRIER, // Memory sync barrier
83
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]84 VCEQ, // Vector compare equal.
85 VCGE, // Vector compare greater than or equal.
86 VCGEU, // Vector compare unsigned greater than or equal.
87 VCGT, // Vector compare greater than.
88 VCGTU, // Vector compare unsigned greater than.
89 VTST, // Vector test bits.
90
91 // Vector shift by immediate:
92 VSHL, // ...left
93 VSHRs, // ...right (signed)
94 VSHRu, // ...right (unsigned)
95 VSHLLs, // ...left long (signed)
96 VSHLLu, // ...left long (unsigned)
97 VSHLLi, // ...left long (with maximum shift count)
98 VSHRN, // ...right narrow
99
100 // Vector rounding shift by immediate:
101 VRSHRs, // ...right (signed)
102 VRSHRu, // ...right (unsigned)
103 VRSHRN, // ...right narrow
104
105 // Vector saturating shift by immediate:
106 VQSHLs, // ...left (signed)
107 VQSHLu, // ...left (unsigned)
108 VQSHLsu, // ...left (signed to unsigned)
109 VQSHRNs, // ...right narrow (signed)
110 VQSHRNu, // ...right narrow (unsigned)
111 VQSHRNsu, // ...right narrow (signed to unsigned)
112
113 // Vector saturating rounding shift by immediate:
114 VQRSHRNs, // ...right narrow (signed)
115 VQRSHRNu, // ...right narrow (unsigned)
116 VQRSHRNsu, // ...right narrow (signed to unsigned)
117
118 // Vector shift and insert:
119 VSLI, // ...left
120 VSRI, // ...right
121
122 // Vector get lane (VMOV scalar to ARM core register)
123 // (These are used for 8- and 16-bit element types only.)
124 VGETLANEu, // zero-extend vector extract element
125 VGETLANEs, // sign-extend vector extract element
126
Bob Wilsonc1d287b2009-08-14 05:13:08 +0000[diff] [blame]127 // Vector duplicate:
Bob Wilsoncba270d2010-07-13 21:16:48 +0000[diff] [blame^]128 VMOVIMM,
Bob Wilsonc1d287b2009-08-14 05:13:08 +0000[diff] [blame]129 VDUP,
Bob Wilson0ce37102009-08-14 05:08:32 +0000[diff] [blame]130 VDUPLANE,
Bob Wilsona599bff2009-08-04 00:36:16 +0000[diff] [blame]131
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]132 // Vector shuffles:
Bob Wilsonde95c1b82009-08-19 17:03:43 +0000[diff] [blame]133 VEXT, // extract
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]134 VREV64, // reverse elements within 64-bit doublewords
135 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +0000[diff] [blame]136 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsonc692cb72009-08-21 20:54:19 +0000[diff] [blame]137 VZIP, // zip (interleave)
138 VUZP, // unzip (deinterleave)
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]139 VTRN, // transpose
140
Bob Wilson40cbe7d2010-06-04 00:04:02 +0000[diff] [blame]141 // Operands of the standard BUILD_VECTOR node are not legalized, which
142 // is fine if BUILD_VECTORs are always lowered to shuffles or other
143 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
144 // operands need to be legalized. Define an ARM-specific version of
145 // BUILD_VECTOR for this purpose.
146 BUILD_VECTOR,
147
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]148 // Floating-point max and min:
149 FMAX,
150 FMIN
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]151 };
152 }
153
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]154 /// Define some predicates that are used for node matching.
155 namespace ARM {
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]156 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
157 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
158 /// instruction, returns its 8-bit integer representation. Otherwise,
159 /// returns -1.
160 int getVFPf32Imm(const APFloat &FPImm);
161 int getVFPf64Imm(const APFloat &FPImm);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]162 }
163
Bob Wilson261f2a22009-05-20 16:30:25 +0000[diff] [blame]164 //===--------------------------------------------------------------------===//
Dale Johannesen80dae192007-03-20 00:30:56 +0000[diff] [blame]165 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]166
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]167 class ARMTargetLowering : public TargetLowering {
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]168 public:
Dan Gohman61e729e2007-08-02 21:21:54 +0000[diff] [blame]169 explicit ARMTargetLowering(TargetMachine &TM);
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]170
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]171 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]172
173 /// ReplaceNodeResults - Replace the results of node with an illegal result
174 /// type with new values built out of custom code.
175 ///
176 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]177 SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]178
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]179 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]180
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]181 virtual const char *getTargetNodeName(unsigned Opcode) const;
182
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000[diff] [blame]183 virtual MachineBasicBlock *
184 EmitInstrWithCustomInserter(MachineInstr *MI,
185 MachineBasicBlock *MBB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]186
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]187 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
188 /// unaligned memory accesses. of the specified type.
189 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
190 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
191
Chris Lattnerc9addb72007-03-30 23:15:24 +0000[diff] [blame]192 /// isLegalAddressingMode - Return true if the addressing mode represented
193 /// by AM is legal for this target, for a load/store of the specified type.
194 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
Evan Chenge6c835f2009-08-14 20:09:37 +0000[diff] [blame]195 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]196
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]197 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]198 /// icmp immediate, that is the target has icmp instructions which can
199 /// compare a register against the immediate without having to materialize
200 /// the immediate into a register.
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]201 virtual bool isLegalICmpImmediate(int64_t Imm) const;
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]202
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]203 /// getPreIndexedAddressParts - returns true by value, base pointer and
204 /// offset pointer and addressing mode by reference if the node's address
205 /// can be legally represented as pre-indexed load / store address.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]206 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
207 SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]208 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]209 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]210
211 /// getPostIndexedAddressParts - returns true by value, base pointer and
212 /// offset pointer and addressing mode by reference if this node can be
213 /// combined with a load / store to form a post-indexed load / store.
214 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]215 SDValue &Base, SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]216 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]217 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]218
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]219 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]220 const APInt &Mask,
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]221 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]222 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]223 const SelectionDAG &DAG,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]224 unsigned Depth) const;
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]225
226
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]227 ConstraintType getConstraintType(const std::string &Constraint) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]228 std::pair<unsigned, const TargetRegisterClass*>
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]229 getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]230 EVT VT) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]231 std::vector<unsigned>
232 getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]233 EVT VT) const;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]234
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]235 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
236 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
237 /// true it means one of the asm constraint of the inline asm instruction
238 /// being processed is 'm'.
239 virtual void LowerAsmOperandForConstraint(SDValue Op,
240 char ConstraintLetter,
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]241 std::vector<SDValue> &Ops,
242 SelectionDAG &DAG) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]243
Dan Gohman419e4f92010-05-11 16:21:03 +0000[diff] [blame]244 const ARMSubtarget* getSubtarget() const {
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]245 return Subtarget;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]246 }
247
Evan Cheng06b666c2010-05-15 02:18:07 +0000[diff] [blame]248 /// getRegClassFor - Return the register class that should be used for the
249 /// specified value type.
250 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
251
Bill Wendlingb4202b82009-07-01 18:50:55 +0000[diff] [blame]252 /// getFunctionAlignment - Return the Log2 alignment of this function.
Bill Wendling20c568f2009-06-30 22:38:32 +0000[diff] [blame]253 virtual unsigned getFunctionAlignment(const Function *F) const;
254
Evan Cheng1cc39842010-05-20 23:26:43 +0000[diff] [blame]255 Sched::Preference getSchedulingPreference(SDNode *N) const;
256
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +0000[diff] [blame]257 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
Anton Korobeynikov48e19352009-09-23 19:04:09 +0000[diff] [blame]258 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]259
260 /// isFPImmLegal - Returns true if the target can instruction select the
261 /// specified FP immediate natively. If false, the legalizer will
262 /// materialize the FP immediate as a load from a constant pool.
263 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
264
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]265 private:
266 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
267 /// make the right decision when generating code for different targets.
268 const ARMSubtarget *Subtarget;
269
Bob Wilsond2559bf2009-07-13 18:11:36 +0000[diff] [blame]270 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]271 ///
272 unsigned ARMPCLabelIndex;
273
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]274 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
275 void addDRTypeForNEON(EVT VT);
276 void addQRTypeForNEON(EVT VT);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]277
278 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]279 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]280 SDValue Chain, SDValue &Arg,
281 RegsToPassVector &RegsToPass,
282 CCValAssign &VA, CCValAssign &NextVA,
283 SDValue &StackPtr,
284 SmallVector<SDValue, 8> &MemOpChains,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]285 ISD::ArgFlagsTy Flags) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]286 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]287 SDValue &Root, SelectionDAG &DAG,
288 DebugLoc dl) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]289
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]290 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
291 bool isVarArg) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]292 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
293 DebugLoc dl, SelectionDAG &DAG,
294 const CCValAssign &VA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]295 ISD::ArgFlagsTy Flags) const;
Jim Grosbach23ff7cf2010-05-26 20:22:18 +0000[diff] [blame]296 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5eb19512010-05-22 01:06:18 +0000[diff] [blame]297 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha87ded22010-02-08 23:22:00 +0000[diff] [blame]298 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]299 const ARMSubtarget *Subtarget) const;
300 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
301 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
302 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
303 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]304 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]305 SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]306 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]307 SelectionDAG &DAG) const;
308 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
309 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
310 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
311 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng515fe3a2010-07-08 02:08:50 +0000[diff] [blame]312 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng2457f2c2010-05-22 01:47:14 +0000[diff] [blame]313 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]314 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
315 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
316 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
317 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola7b73a5d2007-10-19 14:35:17 +0000[diff] [blame]318
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]319 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]320 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]321 const SmallVectorImpl<ISD::InputArg> &Ins,
322 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]323 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]324
325 virtual SDValue
326 LowerFormalArguments(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]327 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]328 const SmallVectorImpl<ISD::InputArg> &Ins,
329 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]330 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]331
332 virtual SDValue
Evan Cheng022d9e12010-02-02 23:55:14 +0000[diff] [blame]333 LowerCall(SDValue Chain, SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]334 CallingConv::ID CallConv, bool isVarArg,
Evan Cheng0c439eb2010-01-27 00:07:07 +0000[diff] [blame]335 bool &isTailCall,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]336 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]337 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]338 const SmallVectorImpl<ISD::InputArg> &Ins,
339 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]340 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]341
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]342 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
343 /// for tail call optimization. Targets which want to do tail call
344 /// optimization should implement this function.
345 bool IsEligibleForTailCallOptimization(SDValue Callee,
346 CallingConv::ID CalleeCC,
347 bool isVarArg,
348 bool isCalleeStructRet,
349 bool isCallerStructRet,
350 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]351 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]352 const SmallVectorImpl<ISD::InputArg> &Ins,
353 SelectionDAG& DAG) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]354 virtual SDValue
355 LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]356 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]357 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]358 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]359 DebugLoc dl, SelectionDAG &DAG) const;
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]360
361 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]362 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
363 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
364 SelectionDAG &DAG, DebugLoc dl) const;
365
366 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]367
Jim Grosbache801dc42009-12-12 01:40:06 +0000[diff] [blame]368 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
369 MachineBasicBlock *BB,
370 unsigned Size) const;
371 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
372 MachineBasicBlock *BB,
373 unsigned Size,
374 unsigned BinOpcode) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]375
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]376 };
377}
378
379#endif // ARMISELLOWERING_H