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gerrit-public.fairphone.software / platform / external / llvm / 36c2b91de7806ddb228865d810fab197ea675fd5 / . / lib / Target / ARM / ARMInstrNEON.td
blob: 45284b640f8c6ddcb89bccc91f71a83513df2c77 [file] [log] [blame]
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]1//===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the ARM NEON instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// NEON-specific DAG Nodes.
16//===----------------------------------------------------------------------===//
17
18def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19
20def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
26
27// Types for vector shift by immediates. The "SHX" version is for long and
28// narrow operations where the source and destination vectors have different
29// types. The "SHINS" version is for shift and insert operations.
30def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
31 SDTCisVT<2, i32>]>;
32def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
33 SDTCisVT<2, i32>]>;
34def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
36
37def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
44
45def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
48
49def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
55
56def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
59
60def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
62
63def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
64 SDTCisVT<2, i32>]>;
65def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
67
68def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
70
Bob Wilson055a90d2009-08-05 00:49:09 +0000[diff] [blame]71def SDTARMVLD2 : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
72def SDTARMVLD3 : SDTypeProfile<3, 1, [SDTCisSameAs<0, 1>,
73 SDTCisSameAs<0, 2>, SDTCisPtrTy<3>]>;
74def SDTARMVLD4 : SDTypeProfile<4, 1, [SDTCisSameAs<0, 1>,
75 SDTCisSameAs<0, 2>,
76 SDTCisSameAs<0, 3>, SDTCisPtrTy<4>]>;
77def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD2,
78 [SDNPHasChain, SDNPMayLoad]>;
79def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD3,
80 [SDNPHasChain, SDNPMayLoad]>;
81def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD4,
82 [SDNPHasChain, SDNPMayLoad]>;
Bob Wilsond2a2e002009-08-04 00:36:16 +0000[diff] [blame]83
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]84//===----------------------------------------------------------------------===//
85// NEON operand definitions
86//===----------------------------------------------------------------------===//
87
88// addrmode_neonldstm := reg
89//
90/* TODO: Take advantage of vldm.
91def addrmode_neonldstm : Operand<i32>,
92 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
93 let PrintMethod = "printAddrNeonLdStMOperand";
94 let MIOperandInfo = (ops GPR, i32imm);
95}
96*/
97
98//===----------------------------------------------------------------------===//
99// NEON load / store instructions
100//===----------------------------------------------------------------------===//
101
102/* TODO: Take advantage of vldm.
103let mayLoad = 1 in {
104def VLDMD : NI<(outs),
105 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
106 "vldm${addr:submode} ${addr:base}, $dst1",
Evan Chengdabc6c02009-07-08 22:51:32 +0000[diff] [blame]107 []> {
108 let Inst{27-25} = 0b110;
109 let Inst{20} = 1;
110 let Inst{11-9} = 0b101;
111}
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]112
113def VLDMS : NI<(outs),
114 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
115 "vldm${addr:submode} ${addr:base}, $dst1",
Evan Chengdabc6c02009-07-08 22:51:32 +0000[diff] [blame]116 []> {
117 let Inst{27-25} = 0b110;
118 let Inst{20} = 1;
119 let Inst{11-9} = 0b101;
120}
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]121}
122*/
123
124// Use vldmia to load a Q register as a D register pair.
125def VLDRQ : NI<(outs QPR:$dst), (ins GPR:$addr),
126 "vldmia $addr, ${dst:dregpair}",
Evan Chengdabc6c02009-07-08 22:51:32 +0000[diff] [blame]127 [(set QPR:$dst, (v2f64 (load GPR:$addr)))]> {
128 let Inst{27-25} = 0b110;
129 let Inst{24} = 0; // P bit
130 let Inst{23} = 1; // U bit
131 let Inst{20} = 1;
132 let Inst{11-9} = 0b101;
133}
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]134
135// Use vstmia to store a Q register as a D register pair.
136def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr),
137 "vstmia $addr, ${src:dregpair}",
Evan Chengdabc6c02009-07-08 22:51:32 +0000[diff] [blame]138 [(store (v2f64 QPR:$src), GPR:$addr)]> {
139 let Inst{27-25} = 0b110;
140 let Inst{24} = 0; // P bit
141 let Inst{23} = 1; // U bit
142 let Inst{20} = 0;
143 let Inst{11-9} = 0b101;
144}
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]145
146
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]147// VLD1 : Vector Load (multiple single elements)
148class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
149 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
Bob Wilson560d2d02009-08-04 21:39:33 +0000[diff] [blame]150 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"),
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]151 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]152class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
153 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
154 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]155 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]156
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]157def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1i>;
158def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1i>;
159def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1i>;
160def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1f>;
161def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1i>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]162
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]163def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1i>;
164def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1i>;
165def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1i>;
166def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1f>;
167def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>;
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]168
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]169// VST1 : Vector Store (multiple single elements)
170class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
171 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
Bob Wilson560d2d02009-08-04 21:39:33 +0000[diff] [blame]172 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]173 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]174class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
175 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
176 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]177 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]178
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]179def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1i>;
180def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1i>;
181def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1i>;
182def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1f>;
183def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1i>;
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]184
Bob Wilsond3902f72009-07-29 16:39:22 +0000[diff] [blame]185def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1i>;
186def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1i>;
187def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>;
188def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>;
189def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>;
Bob Wilsonf7e1ae32009-07-08 20:32:02 +0000[diff] [blame]190
Bob Wilson055a90d2009-08-05 00:49:09 +0000[diff] [blame]191// VLD2 : Vector Load (multiple 2-element structures)
192class VLD2D<string OpcodeStr>
193 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
194 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), []>;
195
196def VLD2d8 : VLD2D<"vld2.8">;
197def VLD2d16 : VLD2D<"vld2.16">;
198def VLD2d32 : VLD2D<"vld2.32">;
Bob Wilson055a90d2009-08-05 00:49:09 +0000[diff] [blame]199
200// VLD3 : Vector Load (multiple 3-element structures)
201class VLD3D<string OpcodeStr>
202 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
203 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), []>;
204
205def VLD3d8 : VLD3D<"vld3.8">;
206def VLD3d16 : VLD3D<"vld3.16">;
207def VLD3d32 : VLD3D<"vld3.32">;
Bob Wilson055a90d2009-08-05 00:49:09 +0000[diff] [blame]208
209// VLD4 : Vector Load (multiple 4-element structures)
210class VLD4D<string OpcodeStr>
211 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
212 (ins addrmode6:$addr),
213 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), []>;
214
215def VLD4d8 : VLD4D<"vld4.8">;
216def VLD4d16 : VLD4D<"vld4.16">;
217def VLD4d32 : VLD4D<"vld4.32">;
Bob Wilson055a90d2009-08-05 00:49:09 +0000[diff] [blame]218
Bob Wilsoned592c02009-07-08 18:11:30 +0000[diff] [blame]219
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]220//===----------------------------------------------------------------------===//
221// NEON pattern fragments
222//===----------------------------------------------------------------------===//
223
224// Extract D sub-registers of Q registers.
225// (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
226def SubReg_i8_reg : SDNodeXForm<imm, [{
227 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
228}]>;
229def SubReg_i16_reg : SDNodeXForm<imm, [{
230 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
231}]>;
232def SubReg_i32_reg : SDNodeXForm<imm, [{
233 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
234}]>;
235def SubReg_f64_reg : SDNodeXForm<imm, [{
236 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
237}]>;
238
239// Translate lane numbers from Q registers to D subregs.
240def SubReg_i8_lane : SDNodeXForm<imm, [{
241 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
242}]>;
243def SubReg_i16_lane : SDNodeXForm<imm, [{
244 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
245}]>;
246def SubReg_i32_lane : SDNodeXForm<imm, [{
247 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
248}]>;
249
250//===----------------------------------------------------------------------===//
251// Instruction Classes
252//===----------------------------------------------------------------------===//
253
254// Basic 2-register operations, both double- and quad-register.
255class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
256 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
257 ValueType ResTy, ValueType OpTy, SDNode OpNode>
258 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
259 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
260 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
261class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
262 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
263 ValueType ResTy, ValueType OpTy, SDNode OpNode>
264 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
265 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
266 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
267
268// Basic 2-register intrinsics, both double- and quad-register.
269class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
270 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
271 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
272 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
273 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
274 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
275class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
276 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
277 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
278 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
279 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
280 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
281
David Goodwinbc7c05e2009-08-04 20:39:05 +0000[diff] [blame]282// Basic 2-register operations, scalar single-precision
283class N2VDInts<SDNode OpNode, NeonI Inst>
284 : NEONFPPat<(f32 (OpNode SPR:$a)),
David Goodwin2105b902009-08-05 21:02:22 +0000[diff] [blame]285 (EXTRACT_SUBREG (COPY_TO_REGCLASS
286 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
287 SPR:$a, arm_ssubreg_0)),
288 DPR_VFP2),
289 arm_ssubreg_0)>;
David Goodwinbc7c05e2009-08-04 20:39:05 +0000[diff] [blame]290
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]291// Narrow 2-register intrinsics.
292class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
293 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
294 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
295 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
296 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
297 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
298
299// Long 2-register intrinsics. (This is currently only used for VMOVL and is
300// derived from N2VImm instead of N2V because of the way the size is encoded.)
301class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
302 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
303 Intrinsic IntOp>
304 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
305 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
306 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
307
308// Basic 3-register operations, both double- and quad-register.
309class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
310 string OpcodeStr, ValueType ResTy, ValueType OpTy,
311 SDNode OpNode, bit Commutable>
312 : N3V<op24, op23, op21_20, op11_8, 0, op4,
313 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
314 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
315 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
316 let isCommutable = Commutable;
317}
318class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
319 string OpcodeStr, ValueType ResTy, ValueType OpTy,
320 SDNode OpNode, bit Commutable>
321 : N3V<op24, op23, op21_20, op11_8, 1, op4,
322 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
323 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
324 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
325 let isCommutable = Commutable;
326}
327
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]328// Basic 3-register operations, scalar single-precision
329class N3VDs<SDNode OpNode, NeonI Inst>
330 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
David Goodwin2105b902009-08-05 21:02:22 +0000[diff] [blame]331 (EXTRACT_SUBREG (COPY_TO_REGCLASS
332 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
333 SPR:$a, arm_ssubreg_0),
334 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
335 SPR:$b, arm_ssubreg_0)),
336 DPR_VFP2),
337 arm_ssubreg_0)>;
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]338
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]339// Basic 3-register intrinsics, both double- and quad-register.
340class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
341 string OpcodeStr, ValueType ResTy, ValueType OpTy,
342 Intrinsic IntOp, bit Commutable>
343 : N3V<op24, op23, op21_20, op11_8, 0, op4,
344 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
345 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
346 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
347 let isCommutable = Commutable;
348}
349class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
350 string OpcodeStr, ValueType ResTy, ValueType OpTy,
351 Intrinsic IntOp, bit Commutable>
352 : N3V<op24, op23, op21_20, op11_8, 1, op4,
353 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
354 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
355 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
356 let isCommutable = Commutable;
357}
358
359// Multiply-Add/Sub operations, both double- and quad-register.
360class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
361 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
362 : N3V<op24, op23, op21_20, op11_8, 0, op4,
363 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
364 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
365 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
366 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
367class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
368 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
369 : N3V<op24, op23, op21_20, op11_8, 1, op4,
370 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
371 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
372 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
373 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
374
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]375// Multiply-Add/Sub operations, scalar single-precision
376class N3VDMulOps<SDNode MulNode, SDNode OpNode, NeonI Inst>
377 : NEONFPPat<(f32 (OpNode SPR:$acc,
378 (f32 (MulNode SPR:$a, SPR:$b)))),
David Goodwin2105b902009-08-05 21:02:22 +0000[diff] [blame]379 (EXTRACT_SUBREG (COPY_TO_REGCLASS
380 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
381 SPR:$acc, arm_ssubreg_0),
382 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
383 SPR:$a, arm_ssubreg_0),
384 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
385 SPR:$b, arm_ssubreg_0)),
386 DPR_VFP2),
Evan Cheng3f19e312009-08-05 06:41:25 +0000[diff] [blame]387 arm_ssubreg_0)>;
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]388
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]389// Neon 3-argument intrinsics, both double- and quad-register.
390// The destination register is also used as the first source operand register.
391class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
392 string OpcodeStr, ValueType ResTy, ValueType OpTy,
393 Intrinsic IntOp>
394 : N3V<op24, op23, op21_20, op11_8, 0, op4,
395 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
396 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
397 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
398 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
399class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
400 string OpcodeStr, ValueType ResTy, ValueType OpTy,
401 Intrinsic IntOp>
402 : N3V<op24, op23, op21_20, op11_8, 1, op4,
403 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
404 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
405 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
406 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
407
408// Neon Long 3-argument intrinsic. The destination register is
409// a quad-register and is also used as the first source operand register.
410class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
411 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
412 : N3V<op24, op23, op21_20, op11_8, 0, op4,
413 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3),
414 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
415 [(set QPR:$dst,
416 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
417
418// Narrowing 3-register intrinsics.
419class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
420 string OpcodeStr, ValueType TyD, ValueType TyQ,
421 Intrinsic IntOp, bit Commutable>
422 : N3V<op24, op23, op21_20, op11_8, 0, op4,
423 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2),
424 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
425 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
426 let isCommutable = Commutable;
427}
428
429// Long 3-register intrinsics.
430class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
431 string OpcodeStr, ValueType TyQ, ValueType TyD,
432 Intrinsic IntOp, bit Commutable>
433 : N3V<op24, op23, op21_20, op11_8, 0, op4,
434 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2),
435 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
436 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
437 let isCommutable = Commutable;
438}
439
440// Wide 3-register intrinsics.
441class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
442 string OpcodeStr, ValueType TyQ, ValueType TyD,
443 Intrinsic IntOp, bit Commutable>
444 : N3V<op24, op23, op21_20, op11_8, 0, op4,
445 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2),
446 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
447 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
448 let isCommutable = Commutable;
449}
450
451// Pairwise long 2-register intrinsics, both double- and quad-register.
452class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
453 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
454 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
455 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
456 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
457 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
458class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
459 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
460 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
461 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
462 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
463 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
464
465// Pairwise long 2-register accumulate intrinsics,
466// both double- and quad-register.
467// The destination register is also used as the first source operand register.
468class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
469 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
470 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
471 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
472 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2),
473 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
474 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
475class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
476 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
477 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
478 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
479 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2),
480 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
481 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
482
483// Shift by immediate,
484// both double- and quad-register.
485class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
486 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
487 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
488 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM),
489 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
490 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
491class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
492 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
493 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
494 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM),
495 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
496 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
497
498// Long shift by immediate.
499class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
500 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
501 ValueType OpTy, SDNode OpNode>
502 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
503 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM),
504 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
505 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
506 (i32 imm:$SIMM))))]>;
507
508// Narrow shift by immediate.
509class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
510 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
511 ValueType OpTy, SDNode OpNode>
512 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
513 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM),
514 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
515 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
516 (i32 imm:$SIMM))))]>;
517
518// Shift right by immediate and accumulate,
519// both double- and quad-register.
520class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
521 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
522 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
523 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
524 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
525 [(set DPR:$dst, (Ty (add DPR:$src1,
526 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
527class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
528 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
529 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
530 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
531 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
532 [(set QPR:$dst, (Ty (add QPR:$src1,
533 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
534
535// Shift by immediate and insert,
536// both double- and quad-register.
537class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
538 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
539 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
540 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
541 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
542 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
543class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
544 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
545 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
546 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
547 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
548 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
549
550// Convert, with fractional bits immediate,
551// both double- and quad-register.
552class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
553 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
554 Intrinsic IntOp>
555 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
556 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM),
557 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
558 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
559class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
560 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
561 Intrinsic IntOp>
562 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
563 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM),
564 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
565 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
566
567//===----------------------------------------------------------------------===//
568// Multiclasses
569//===----------------------------------------------------------------------===//
570
571// Neon 3-register vector operations.
572
573// First with only element sizes of 8, 16 and 32 bits:
574multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
575 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
576 // 64-bit vector types.
577 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
578 v8i8, v8i8, OpNode, Commutable>;
579 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
580 v4i16, v4i16, OpNode, Commutable>;
581 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
582 v2i32, v2i32, OpNode, Commutable>;
583
584 // 128-bit vector types.
585 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
586 v16i8, v16i8, OpNode, Commutable>;
587 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
588 v8i16, v8i16, OpNode, Commutable>;
589 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
590 v4i32, v4i32, OpNode, Commutable>;
591}
592
593// ....then also with element size 64 bits:
594multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
595 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
596 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
597 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
598 v1i64, v1i64, OpNode, Commutable>;
599 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
600 v2i64, v2i64, OpNode, Commutable>;
601}
602
603
604// Neon Narrowing 2-register vector intrinsics,
605// source operand element sizes of 16, 32 and 64 bits:
606multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
607 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
608 Intrinsic IntOp> {
609 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
610 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
611 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
612 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
613 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
614 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
615}
616
617
618// Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
619// source operand element sizes of 16, 32 and 64 bits:
620multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
621 bit op4, string OpcodeStr, Intrinsic IntOp> {
622 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
623 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
624 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
625 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
626 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
627 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
628}
629
630
631// Neon 3-register vector intrinsics.
632
633// First with only element sizes of 16 and 32 bits:
634multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
635 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
636 // 64-bit vector types.
637 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
638 v4i16, v4i16, IntOp, Commutable>;
639 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
640 v2i32, v2i32, IntOp, Commutable>;
641
642 // 128-bit vector types.
643 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
644 v8i16, v8i16, IntOp, Commutable>;
645 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
646 v4i32, v4i32, IntOp, Commutable>;
647}
648
649// ....then also with element size of 8 bits:
650multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
651 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
652 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
653 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
654 v8i8, v8i8, IntOp, Commutable>;
655 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
656 v16i8, v16i8, IntOp, Commutable>;
657}
658
659// ....then also with element size of 64 bits:
660multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
661 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
662 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
663 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
664 v1i64, v1i64, IntOp, Commutable>;
665 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
666 v2i64, v2i64, IntOp, Commutable>;
667}
668
669
670// Neon Narrowing 3-register vector intrinsics,
671// source operand element sizes of 16, 32 and 64 bits:
672multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
673 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
674 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
675 v8i8, v8i16, IntOp, Commutable>;
676 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
677 v4i16, v4i32, IntOp, Commutable>;
678 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
679 v2i32, v2i64, IntOp, Commutable>;
680}
681
682
683// Neon Long 3-register vector intrinsics.
684
685// First with only element sizes of 16 and 32 bits:
686multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
687 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
688 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
689 v4i32, v4i16, IntOp, Commutable>;
690 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
691 v2i64, v2i32, IntOp, Commutable>;
692}
693
694// ....then also with element size of 8 bits:
695multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
696 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
697 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
698 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
699 v8i16, v8i8, IntOp, Commutable>;
700}
701
702
703// Neon Wide 3-register vector intrinsics,
704// source operand element sizes of 8, 16 and 32 bits:
705multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
706 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
707 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
708 v8i16, v8i8, IntOp, Commutable>;
709 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
710 v4i32, v4i16, IntOp, Commutable>;
711 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
712 v2i64, v2i32, IntOp, Commutable>;
713}
714
715
716// Neon Multiply-Op vector operations,
717// element sizes of 8, 16 and 32 bits:
718multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
719 string OpcodeStr, SDNode OpNode> {
720 // 64-bit vector types.
721 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
722 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
723 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
724 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
725 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
726 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
727
728 // 128-bit vector types.
729 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
730 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
731 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
732 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
733 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
734 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
735}
736
737
738// Neon 3-argument intrinsics,
739// element sizes of 8, 16 and 32 bits:
740multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
741 string OpcodeStr, Intrinsic IntOp> {
742 // 64-bit vector types.
743 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
744 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
745 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
746 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
747 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
748 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
749
750 // 128-bit vector types.
751 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
752 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
753 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
754 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
755 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
756 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
757}
758
759
760// Neon Long 3-argument intrinsics.
761
762// First with only element sizes of 16 and 32 bits:
763multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
764 string OpcodeStr, Intrinsic IntOp> {
765 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
766 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
767 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
768 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
769}
770
771// ....then also with element size of 8 bits:
772multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
773 string OpcodeStr, Intrinsic IntOp>
774 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
775 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
776 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
777}
778
779
780// Neon 2-register vector intrinsics,
781// element sizes of 8, 16 and 32 bits:
782multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
783 bits<5> op11_7, bit op4, string OpcodeStr,
784 Intrinsic IntOp> {
785 // 64-bit vector types.
786 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
787 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
788 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
789 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
790 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
791 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
792
793 // 128-bit vector types.
794 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
795 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
796 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
797 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
798 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
799 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
800}
801
802
803// Neon Pairwise long 2-register intrinsics,
804// element sizes of 8, 16 and 32 bits:
805multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
806 bits<5> op11_7, bit op4,
807 string OpcodeStr, Intrinsic IntOp> {
808 // 64-bit vector types.
809 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
810 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
811 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
812 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
813 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
814 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
815
816 // 128-bit vector types.
817 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
818 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
819 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
820 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
821 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
822 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
823}
824
825
826// Neon Pairwise long 2-register accumulate intrinsics,
827// element sizes of 8, 16 and 32 bits:
828multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
829 bits<5> op11_7, bit op4,
830 string OpcodeStr, Intrinsic IntOp> {
831 // 64-bit vector types.
832 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
833 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
834 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
835 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
836 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
837 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
838
839 // 128-bit vector types.
840 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
841 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
842 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
843 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
844 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
845 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
846}
847
848
849// Neon 2-register vector shift by immediate,
850// element sizes of 8, 16, 32 and 64 bits:
851multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
852 string OpcodeStr, SDNode OpNode> {
853 // 64-bit vector types.
854 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
855 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
856 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
857 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
858 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
859 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
860 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
861 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
862
863 // 128-bit vector types.
864 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
865 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
866 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
867 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
868 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
869 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
870 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
871 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
872}
873
874
875// Neon Shift-Accumulate vector operations,
876// element sizes of 8, 16, 32 and 64 bits:
877multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
878 string OpcodeStr, SDNode ShOp> {
879 // 64-bit vector types.
880 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
881 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
882 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
883 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
884 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
885 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
886 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
887 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
888
889 // 128-bit vector types.
890 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
891 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
892 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
893 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
894 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
895 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
896 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
897 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
898}
899
900
901// Neon Shift-Insert vector operations,
902// element sizes of 8, 16, 32 and 64 bits:
903multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
904 string OpcodeStr, SDNode ShOp> {
905 // 64-bit vector types.
906 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
907 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
908 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
909 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
910 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
911 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
912 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
913 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
914
915 // 128-bit vector types.
916 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
917 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
918 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
919 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
920 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
921 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
922 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
923 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
924}
925
926//===----------------------------------------------------------------------===//
927// Instruction Definitions.
928//===----------------------------------------------------------------------===//
929
930// Vector Add Operations.
931
932// VADD : Vector Add (integer and floating-point)
933defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
934def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
935def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
936// VADDL : Vector Add Long (Q = D + D)
937defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
938defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
939// VADDW : Vector Add Wide (Q = Q + D)
940defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
941defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
942// VHADD : Vector Halving Add
943defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
944defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
945// VRHADD : Vector Rounding Halving Add
946defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
947defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
948// VQADD : Vector Saturating Add
949defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
950defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
951// VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
952defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
953// VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
954defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
955
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]956// Vector Add Operations used for single-precision FP
957def : N3VDs<fadd, VADDfd>;
958
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]959// Vector Multiply Operations.
960
961// VMUL : Vector Multiply (integer, polynomial and floating-point)
962defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
963def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
964 int_arm_neon_vmulp, 1>;
965def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
966 int_arm_neon_vmulp, 1>;
967def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
968def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
969// VQDMULH : Vector Saturating Doubling Multiply Returning High Half
970defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
971// VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
972defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
973// VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
974defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
975defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
976def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
977 int_arm_neon_vmullp, 1>;
978// VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
979defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
980
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]981// Vector Multiply Operations used for single-precision FP
982def : N3VDs<fmul, VMULfd>;
983
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]984// Vector Multiply-Accumulate and Multiply-Subtract Operations.
985
986// VMLA : Vector Multiply Accumulate (integer and floating-point)
987defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
988def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
989def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
990// VMLAL : Vector Multiply Accumulate Long (Q += D * D)
991defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
992defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
993// VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
994defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
995// VMLS : Vector Multiply Subtract (integer and floating-point)
996defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
997def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
998def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
999// VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1000defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1001defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1002// VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1003defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1004
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]1005// Vector Multiply-Accumulate/Subtract used for single-precision FP
1006def : N3VDMulOps<fmul, fadd, VMLAfd>;
David Goodwinf31748c2009-08-04 18:44:29 +0000[diff] [blame]1007def : N3VDMulOps<fmul, fsub, VMLSfd>;
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]1008
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]1009// Vector Subtract Operations.
1010
1011// VSUB : Vector Subtract (integer and floating-point)
1012defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
1013def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
1014def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
1015// VSUBL : Vector Subtract Long (Q = D - D)
1016defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
1017defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
1018// VSUBW : Vector Subtract Wide (Q = Q - D)
1019defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1020defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1021// VHSUB : Vector Halving Subtract
1022defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
1023defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
1024// VQSUB : Vector Saturing Subtract
1025defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
1026defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
1027// VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1028defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1029// VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1030defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1031
David Goodwindd19ce42009-08-04 17:53:06 +0000[diff] [blame]1032// Vector Sub Operations used for single-precision FP
1033def : N3VDs<fsub, VSUBfd>;
1034
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]1035// Vector Comparisons.
1036
1037// VCEQ : Vector Compare Equal
1038defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
1039def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1040def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1041// VCGE : Vector Compare Greater Than or Equal
1042defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
1043defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
1044def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1045def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1046// VCGT : Vector Compare Greater Than
1047defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
1048defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
1049def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1050def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1051// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1052def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1053 int_arm_neon_vacged, 0>;
1054def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1055 int_arm_neon_vacgeq, 0>;
1056// VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1057def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1058 int_arm_neon_vacgtd, 0>;
1059def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1060 int_arm_neon_vacgtq, 0>;
1061// VTST : Vector Test Bits
1062defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1063
1064// Vector Bitwise Operations.
1065
1066// VAND : Vector Bitwise AND
1067def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1068def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1069
1070// VEOR : Vector Bitwise Exclusive OR
1071def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1072def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1073
1074// VORR : Vector Bitwise OR
1075def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1076def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1077
1078// VBIC : Vector Bitwise Bit Clear (AND NOT)
1079def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1080 (ins DPR:$src1, DPR:$src2), "vbic\t$dst, $src1, $src2", "",
1081 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1082def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1083 (ins QPR:$src1, QPR:$src2), "vbic\t$dst, $src1, $src2", "",
1084 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1085
1086// VORN : Vector Bitwise OR NOT
1087def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1088 (ins DPR:$src1, DPR:$src2), "vorn\t$dst, $src1, $src2", "",
1089 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1090def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1091 (ins QPR:$src1, QPR:$src2), "vorn\t$dst, $src1, $src2", "",
1092 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1093
1094// VMVN : Vector Bitwise NOT
1095def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1096 (outs DPR:$dst), (ins DPR:$src), "vmvn\t$dst, $src", "",
1097 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1098def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1099 (outs QPR:$dst), (ins QPR:$src), "vmvn\t$dst, $src", "",
1100 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1101def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1102def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1103
1104// VBSL : Vector Bitwise Select
1105def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1106 (ins DPR:$src1, DPR:$src2, DPR:$src3),
1107 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1108 [(set DPR:$dst,
1109 (v2i32 (or (and DPR:$src2, DPR:$src1),
1110 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1111def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1112 (ins QPR:$src1, QPR:$src2, QPR:$src3),
1113 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1114 [(set QPR:$dst,
1115 (v4i32 (or (and QPR:$src2, QPR:$src1),
1116 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1117
1118// VBIF : Vector Bitwise Insert if False
1119// like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1120// VBIT : Vector Bitwise Insert if True
1121// like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1122// These are not yet implemented. The TwoAddress pass will not go looking
1123// for equivalent operations with different register constraints; it just
1124// inserts copies.
1125
1126// Vector Absolute Differences.
1127
1128// VABD : Vector Absolute Difference
1129defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1130defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1131def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1132 int_arm_neon_vabdf, 0>;
1133def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1134 int_arm_neon_vabdf, 0>;
1135
1136// VABDL : Vector Absolute Difference Long (Q = | D - D |)
1137defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1138defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1139
1140// VABA : Vector Absolute Difference and Accumulate
1141defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1142defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1143
1144// VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1145defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1146defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1147
1148// Vector Maximum and Minimum.
1149
1150// VMAX : Vector Maximum
1151defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1152defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1153def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1154 int_arm_neon_vmaxf, 1>;
1155def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1156 int_arm_neon_vmaxf, 1>;
1157
1158// VMIN : Vector Minimum
1159defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1160defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1161def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1162 int_arm_neon_vminf, 1>;
1163def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1164 int_arm_neon_vminf, 1>;
1165
1166// Vector Pairwise Operations.
1167
1168// VPADD : Vector Pairwise Add
1169def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1170 int_arm_neon_vpaddi, 0>;
1171def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1172 int_arm_neon_vpaddi, 0>;
1173def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1174 int_arm_neon_vpaddi, 0>;
1175def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1176 int_arm_neon_vpaddf, 0>;
1177
1178// VPADDL : Vector Pairwise Add Long
1179defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1180 int_arm_neon_vpaddls>;
1181defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1182 int_arm_neon_vpaddlu>;
1183
1184// VPADAL : Vector Pairwise Add and Accumulate Long
1185defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1186 int_arm_neon_vpadals>;
1187defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1188 int_arm_neon_vpadalu>;
1189
1190// VPMAX : Vector Pairwise Maximum
1191def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1192 int_arm_neon_vpmaxs, 0>;
1193def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1194 int_arm_neon_vpmaxs, 0>;
1195def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1196 int_arm_neon_vpmaxs, 0>;
1197def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1198 int_arm_neon_vpmaxu, 0>;
1199def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1200 int_arm_neon_vpmaxu, 0>;
1201def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1202 int_arm_neon_vpmaxu, 0>;
1203def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1204 int_arm_neon_vpmaxf, 0>;
1205
1206// VPMIN : Vector Pairwise Minimum
1207def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1208 int_arm_neon_vpmins, 0>;
1209def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1210 int_arm_neon_vpmins, 0>;
1211def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1212 int_arm_neon_vpmins, 0>;
1213def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1214 int_arm_neon_vpminu, 0>;
1215def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1216 int_arm_neon_vpminu, 0>;
1217def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1218 int_arm_neon_vpminu, 0>;
1219def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1220 int_arm_neon_vpminf, 0>;
1221
1222// Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1223
1224// VRECPE : Vector Reciprocal Estimate
1225def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1226 v2i32, v2i32, int_arm_neon_vrecpe>;
1227def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1228 v4i32, v4i32, int_arm_neon_vrecpe>;
1229def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1230 v2f32, v2f32, int_arm_neon_vrecpef>;
1231def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1232 v4f32, v4f32, int_arm_neon_vrecpef>;
1233
1234// VRECPS : Vector Reciprocal Step
1235def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1236 int_arm_neon_vrecps, 1>;
1237def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1238 int_arm_neon_vrecps, 1>;
1239
1240// VRSQRTE : Vector Reciprocal Square Root Estimate
1241def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1242 v2i32, v2i32, int_arm_neon_vrsqrte>;
1243def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1244 v4i32, v4i32, int_arm_neon_vrsqrte>;
1245def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1246 v2f32, v2f32, int_arm_neon_vrsqrtef>;
1247def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1248 v4f32, v4f32, int_arm_neon_vrsqrtef>;
1249
1250// VRSQRTS : Vector Reciprocal Square Root Step
1251def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1252 int_arm_neon_vrsqrts, 1>;
1253def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1254 int_arm_neon_vrsqrts, 1>;
1255
1256// Vector Shifts.
1257
1258// VSHL : Vector Shift
1259defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1260defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1261// VSHL : Vector Shift Left (Immediate)
1262defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1263// VSHR : Vector Shift Right (Immediate)
1264defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1265defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1266
1267// VSHLL : Vector Shift Left Long
1268def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1269 v8i16, v8i8, NEONvshlls>;
1270def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1271 v4i32, v4i16, NEONvshlls>;
1272def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1273 v2i64, v2i32, NEONvshlls>;
1274def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1275 v8i16, v8i8, NEONvshllu>;
1276def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1277 v4i32, v4i16, NEONvshllu>;
1278def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1279 v2i64, v2i32, NEONvshllu>;
1280
1281// VSHLL : Vector Shift Left Long (with maximum shift count)
1282def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1283 v8i16, v8i8, NEONvshlli>;
1284def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1285 v4i32, v4i16, NEONvshlli>;
1286def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1287 v2i64, v2i32, NEONvshlli>;
1288
1289// VSHRN : Vector Shift Right and Narrow
1290def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1291 v8i8, v8i16, NEONvshrn>;
1292def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1293 v4i16, v4i32, NEONvshrn>;
1294def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1295 v2i32, v2i64, NEONvshrn>;
1296
1297// VRSHL : Vector Rounding Shift
1298defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1299defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1300// VRSHR : Vector Rounding Shift Right
1301defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1302defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1303
1304// VRSHRN : Vector Rounding Shift Right and Narrow
1305def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1306 v8i8, v8i16, NEONvrshrn>;
1307def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1308 v4i16, v4i32, NEONvrshrn>;
1309def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1310 v2i32, v2i64, NEONvrshrn>;
1311
1312// VQSHL : Vector Saturating Shift
1313defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1314defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1315// VQSHL : Vector Saturating Shift Left (Immediate)
1316defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1317defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1318// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1319defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1320
1321// VQSHRN : Vector Saturating Shift Right and Narrow
1322def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1323 v8i8, v8i16, NEONvqshrns>;
1324def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1325 v4i16, v4i32, NEONvqshrns>;
1326def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1327 v2i32, v2i64, NEONvqshrns>;
1328def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1329 v8i8, v8i16, NEONvqshrnu>;
1330def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1331 v4i16, v4i32, NEONvqshrnu>;
1332def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1333 v2i32, v2i64, NEONvqshrnu>;
1334
1335// VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1336def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1337 v8i8, v8i16, NEONvqshrnsu>;
1338def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1339 v4i16, v4i32, NEONvqshrnsu>;
1340def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1341 v2i32, v2i64, NEONvqshrnsu>;
1342
1343// VQRSHL : Vector Saturating Rounding Shift
1344defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1345 int_arm_neon_vqrshifts, 0>;
1346defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1347 int_arm_neon_vqrshiftu, 0>;
1348
1349// VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1350def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1351 v8i8, v8i16, NEONvqrshrns>;
1352def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1353 v4i16, v4i32, NEONvqrshrns>;
1354def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1355 v2i32, v2i64, NEONvqrshrns>;
1356def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1357 v8i8, v8i16, NEONvqrshrnu>;
1358def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1359 v4i16, v4i32, NEONvqrshrnu>;
1360def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1361 v2i32, v2i64, NEONvqrshrnu>;
1362
1363// VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1364def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1365 v8i8, v8i16, NEONvqrshrnsu>;
1366def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1367 v4i16, v4i32, NEONvqrshrnsu>;
1368def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1369 v2i32, v2i64, NEONvqrshrnsu>;
1370
1371// VSRA : Vector Shift Right and Accumulate
1372defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1373defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1374// VRSRA : Vector Rounding Shift Right and Accumulate
1375defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1376defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1377
1378// VSLI : Vector Shift Left and Insert
1379defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1380// VSRI : Vector Shift Right and Insert
1381defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1382
1383// Vector Absolute and Saturating Absolute.
1384
1385// VABS : Vector Absolute Value
1386defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1387 int_arm_neon_vabs>;
1388def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1389 v2f32, v2f32, int_arm_neon_vabsf>;
1390def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1391 v4f32, v4f32, int_arm_neon_vabsf>;
David Goodwinbc7c05e2009-08-04 20:39:05 +0000[diff] [blame]1392def : N2VDInts<fabs, VABSfd>;
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]1393
1394// VQABS : Vector Saturating Absolute Value
1395defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1396 int_arm_neon_vqabs>;
1397
1398// Vector Negate.
1399
1400def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1401def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1402
1403class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1404 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1405 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1406 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1407class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1408 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1409 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1410 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1411
1412// VNEG : Vector Negate
1413def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1414def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1415def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1416def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1417def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1418def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1419
1420// VNEG : Vector Negate (floating-point)
1421def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1422 (outs DPR:$dst), (ins DPR:$src), "vneg.f32\t$dst, $src", "",
1423 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1424def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1425 (outs QPR:$dst), (ins QPR:$src), "vneg.f32\t$dst, $src", "",
1426 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
David Goodwinbc7c05e2009-08-04 20:39:05 +0000[diff] [blame]1427def : N2VDInts<fneg, VNEGf32d>;
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]1428
1429def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1430def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1431def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1432def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1433def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1434def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1435
1436// VQNEG : Vector Saturating Negate
1437defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1438 int_arm_neon_vqneg>;
1439
1440// Vector Bit Counting Operations.
1441
1442// VCLS : Vector Count Leading Sign Bits
1443defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1444 int_arm_neon_vcls>;
1445// VCLZ : Vector Count Leading Zeros
1446defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1447 int_arm_neon_vclz>;
1448// VCNT : Vector Count One Bits
1449def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1450 v8i8, v8i8, int_arm_neon_vcnt>;
1451def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1452 v16i8, v16i8, int_arm_neon_vcnt>;
1453
1454// Vector Move Operations.
1455
1456// VMOV : Vector Move (Register)
1457
1458def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1459 "vmov\t$dst, $src", "", []>;
1460def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1461 "vmov\t$dst, $src", "", []>;
1462
1463// VMOV : Vector Move (Immediate)
1464
1465// VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1466def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1467 return ARM::getVMOVImm(N, 1, *CurDAG);
1468}]>;
1469def vmovImm8 : PatLeaf<(build_vector), [{
1470 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1471}], VMOV_get_imm8>;
1472
1473// VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1474def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1475 return ARM::getVMOVImm(N, 2, *CurDAG);
1476}]>;
1477def vmovImm16 : PatLeaf<(build_vector), [{
1478 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1479}], VMOV_get_imm16>;
1480
1481// VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1482def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1483 return ARM::getVMOVImm(N, 4, *CurDAG);
1484}]>;
1485def vmovImm32 : PatLeaf<(build_vector), [{
1486 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1487}], VMOV_get_imm32>;
1488
1489// VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1490def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1491 return ARM::getVMOVImm(N, 8, *CurDAG);
1492}]>;
1493def vmovImm64 : PatLeaf<(build_vector), [{
1494 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1495}], VMOV_get_imm64>;
1496
1497// Note: Some of the cmode bits in the following VMOV instructions need to
1498// be encoded based on the immed values.
1499
1500def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1501 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "",
1502 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1503def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1504 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "",
1505 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1506
1507def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1508 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "",
1509 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1510def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1511 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "",
1512 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1513
1514def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1515 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "",
1516 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1517def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1518 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "",
1519 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1520
1521def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1522 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "",
1523 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1524def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1525 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "",
1526 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1527
1528// VMOV : Vector Get Lane (move scalar to ARM core register)
1529
1530def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1531 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1532 "vmov", ".s8\t$dst, $src[$lane]",
1533 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1534 imm:$lane))]>;
1535def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1536 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1537 "vmov", ".s16\t$dst, $src[$lane]",
1538 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1539 imm:$lane))]>;
1540def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1541 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1542 "vmov", ".u8\t$dst, $src[$lane]",
1543 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1544 imm:$lane))]>;
1545def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1546 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1547 "vmov", ".u16\t$dst, $src[$lane]",
1548 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1549 imm:$lane))]>;
1550def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1551 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1552 "vmov", ".32\t$dst, $src[$lane]",
1553 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1554 imm:$lane))]>;
1555// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1556def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1557 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1558 (SubReg_i8_reg imm:$lane))),
1559 (SubReg_i8_lane imm:$lane))>;
1560def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1561 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1562 (SubReg_i16_reg imm:$lane))),
1563 (SubReg_i16_lane imm:$lane))>;
1564def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1565 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1566 (SubReg_i8_reg imm:$lane))),
1567 (SubReg_i8_lane imm:$lane))>;
1568def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1569 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1570 (SubReg_i16_reg imm:$lane))),
1571 (SubReg_i16_lane imm:$lane))>;
1572def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1573 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1574 (SubReg_i32_reg imm:$lane))),
1575 (SubReg_i32_lane imm:$lane))>;
1576//def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1577// (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1578def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1579 (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1580
1581
1582// VMOV : Vector Set Lane (move ARM core register to scalar)
1583
1584let Constraints = "$src1 = $dst" in {
1585def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1586 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1587 "vmov", ".8\t$dst[$lane], $src2",
1588 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1589 GPR:$src2, imm:$lane))]>;
1590def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1591 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1592 "vmov", ".16\t$dst[$lane], $src2",
1593 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1594 GPR:$src2, imm:$lane))]>;
1595def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1596 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1597 "vmov", ".32\t$dst[$lane], $src2",
1598 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1599 GPR:$src2, imm:$lane))]>;
1600}
1601def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1602 (v16i8 (INSERT_SUBREG QPR:$src1,
1603 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1604 (SubReg_i8_reg imm:$lane))),
1605 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1606 (SubReg_i8_reg imm:$lane)))>;
1607def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1608 (v8i16 (INSERT_SUBREG QPR:$src1,
1609 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1610 (SubReg_i16_reg imm:$lane))),
1611 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1612 (SubReg_i16_reg imm:$lane)))>;
1613def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1614 (v4i32 (INSERT_SUBREG QPR:$src1,
1615 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1616 (SubReg_i32_reg imm:$lane))),
1617 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1618 (SubReg_i32_reg imm:$lane)))>;
1619
1620//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1621// (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1622def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1623 (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1624
1625// VDUP : Vector Duplicate (from ARM core register to all elements)
1626
1627def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
1628 (vector_shuffle node:$lhs, node:$rhs), [{
1629 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1630 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
1631}]>;
1632
1633class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1634 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1635 "vdup", !strconcat(asmSize, "\t$dst, $src"),
1636 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1637class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1638 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1639 "vdup", !strconcat(asmSize, "\t$dst, $src"),
1640 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1641
1642def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1643def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1644def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1645def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1646def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1647def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1648
1649def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1650 "vdup", ".32\t$dst, $src",
1651 [(set DPR:$dst, (v2f32 (splat_lo
1652 (scalar_to_vector
1653 (f32 (bitconvert GPR:$src))),
1654 undef)))]>;
1655def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1656 "vdup", ".32\t$dst, $src",
1657 [(set QPR:$dst, (v4f32 (splat_lo
1658 (scalar_to_vector
1659 (f32 (bitconvert GPR:$src))),
1660 undef)))]>;
1661
1662// VDUP : Vector Duplicate Lane (from scalar to all elements)
1663
1664def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
1665 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1666 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
1667}]>;
1668
1669def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
1670 (vector_shuffle node:$lhs, node:$rhs), [{
1671 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1672 return SVOp->isSplat();
1673}], SHUFFLE_get_splat_lane>;
1674
1675class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1676 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1677 (outs DPR:$dst), (ins DPR:$src, i32imm:$lane),
1678 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1679 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
1680
1681// vector_shuffle requires that the source and destination types match, so
1682// VDUP to a 128-bit result uses a target-specific VDUPLANEQ node.
1683class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1684 ValueType ResTy, ValueType OpTy>
1685 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1686 (outs QPR:$dst), (ins DPR:$src, i32imm:$lane),
1687 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1688 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
1689
1690def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1691def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1692def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1693def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1694def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1695def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1696def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1697def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1698
1699// VMOVN : Vector Narrowing Move
1700defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1701 int_arm_neon_vmovn>;
1702// VQMOVN : Vector Saturating Narrowing Move
1703defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1704 int_arm_neon_vqmovns>;
1705defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1706 int_arm_neon_vqmovnu>;
1707defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1708 int_arm_neon_vqmovnsu>;
1709// VMOVL : Vector Lengthening Move
1710defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1711defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1712
1713// Vector Conversions.
1714
1715// VCVT : Vector Convert Between Floating-Point and Integers
1716def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1717 v2i32, v2f32, fp_to_sint>;
1718def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1719 v2i32, v2f32, fp_to_uint>;
1720def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1721 v2f32, v2i32, sint_to_fp>;
1722def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1723 v2f32, v2i32, uint_to_fp>;
1724
1725def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1726 v4i32, v4f32, fp_to_sint>;
1727def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1728 v4i32, v4f32, fp_to_uint>;
1729def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1730 v4f32, v4i32, sint_to_fp>;
1731def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1732 v4f32, v4i32, uint_to_fp>;
1733
1734// VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1735// Note: Some of the opcode bits in the following VCVT instructions need to
1736// be encoded based on the immed values.
1737def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1738 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1739def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1740 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1741def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1742 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1743def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1744 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1745
1746def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1747 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1748def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1749 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1750def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1751 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1752def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1753 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1754
Bob Wilsonc1cd72e2009-07-26 00:39:34 +0000[diff] [blame]1755// VREV : Vector Reverse
1756
1757def vrev64_shuffle : PatFrag<(ops node:$in),
1758 (vector_shuffle node:$in, undef), [{
1759 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1760 return ARM::isVREVMask(SVOp, 64);
1761}]>;
1762
1763def vrev32_shuffle : PatFrag<(ops node:$in),
1764 (vector_shuffle node:$in, undef), [{
1765 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1766 return ARM::isVREVMask(SVOp, 32);
1767}]>;
1768
1769def vrev16_shuffle : PatFrag<(ops node:$in),
1770 (vector_shuffle node:$in, undef), [{
1771 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1772 return ARM::isVREVMask(SVOp, 16);
1773}]>;
1774
1775// VREV64 : Vector Reverse elements within 64-bit doublewords
1776
1777class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1778 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1779 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1780 [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>;
1781class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1782 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1783 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1784 [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>;
1785
1786def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1787def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1788def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1789def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1790
1791def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1792def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1793def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1794def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1795
1796// VREV32 : Vector Reverse elements within 32-bit words
1797
1798class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1799 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1800 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1801 [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>;
1802class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1803 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1804 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1805 [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>;
1806
1807def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1808def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1809
1810def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1811def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1812
1813// VREV16 : Vector Reverse elements within 16-bit halfwords
1814
1815class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1816 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1817 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1818 [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>;
1819class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1820 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1821 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "",
1822 [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>;
1823
1824def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1825def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1826
Bob Wilsone60fee02009-06-22 23:27:02 +0000[diff] [blame]1827//===----------------------------------------------------------------------===//
1828// Non-Instruction Patterns
1829//===----------------------------------------------------------------------===//
1830
1831// bit_convert
1832def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
1833def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
1834def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
1835def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
1836def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
1837def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
1838def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
1839def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
1840def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
1841def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
1842def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
1843def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
1844def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
1845def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
1846def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
1847def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
1848def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
1849def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
1850def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
1851def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
1852def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
1853def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
1854def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
1855def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
1856def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
1857def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
1858def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
1859def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
1860def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
1861def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
1862
1863def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
1864def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
1865def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
1866def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
1867def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
1868def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
1869def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
1870def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
1871def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
1872def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
1873def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
1874def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
1875def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
1876def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
1877def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
1878def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
1879def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
1880def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
1881def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
1882def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
1883def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
1884def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
1885def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
1886def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
1887def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
1888def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
1889def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
1890def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
1891def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
1892def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;