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Dan Gohmanf17a25c2007-07-18 16:29:46 +00001=pod
2
3=head1 NAME
4
5llc - LLVM static compiler
6
7=head1 SYNOPSIS
8
9B<llc> [I<options>] [I<filename>]
10
11=head1 DESCRIPTION
12
13The B<llc> command compiles LLVM bitcode into assembly language for a
14specified architecture. The assembly language output can then be passed through
15a native assembler and linker to generate a native executable.
16
17The choice of architecture for the output assembly code is automatically
18determined from the input bitcode file, unless the B<-march> option is used to
19override the default.
20
21=head1 OPTIONS
22
23If I<filename> is - or omitted, B<llc> reads LLVM bitcode from standard input.
24Otherwise, it will read LLVM bitcode from I<filename>.
25
26If the B<-o> option is omitted, then B<llc> will send its output to standard
27output if the input is from standard input. If the B<-o> option specifies -,
28then the output will also be sent to standard output.
29
30If no B<-o> option is specified and an input file other than - is specified,
31then B<llc> creates the output filename by taking the input filename,
32removing any existing F<.bc> extension, and adding a F<.s> suffix.
33
34Other B<llc> options are as follows:
35
36=head2 End-user Options
37
38=over
39
40=item B<--help>
41
42Print a summary of command line options.
43
44=item B<-f>
45
46Overwrite output files. By default, B<llc> will refuse to overwrite
47an output file which already exists.
48
49=item B<-mtriple>=I<target triple>
50
51Override the target triple specified in the input bitcode file with the
52specified string.
53
54=item B<-march>=I<arch>
55
56Specify the architecture for which to generate assembly, overriding the target
57encoded in the bitcode file. See the output of B<llc --help> for a list of
58valid architectures. By default this is inferred from the target triple or
59autodetected to the current architecture.
60
61=item B<-mcpu>=I<cpuname>
62
63Specify a specific chip in the current architecture to generate code for.
64By default this is inferred from the target triple and autodetected to
65the current architecture. For a list of available CPUs, use:
66B<llvm-as E<lt> /dev/null | llc -march=xyz -mcpu=help>
67
68=item B<-mattr>=I<a1,+a2,-a3,...>
69
70Override or control specific attributes of the target, such as whether SIMD
71operations are enabled or not. The default set of attributes is set by the
72current CPU. For a list of available attributes, use:
73B<llvm-as E<lt> /dev/null | llc -march=xyz -mattr=help>
74
75=item B<--disable-fp-elim>
76
77Disable frame pointer elimination optimization.
78
79=item B<--disable-excess-fp-precision>
80
81Disable optimizations that may produce excess precision for floating point.
82Note that this option can dramatically slow down code on some systems
83(e.g. X86).
84
85=item B<--enable-unsafe-fp-math>
86
87Enable optimizations that make unsafe assumptions about IEEE math (e.g. that
88addition is associative) or may not work for all input ranges. These
89optimizations allow the code generator to make use of some instructions which
90would otherwise not be usable (such as fsin on X86).
91
92=item B<--enable-correct-eh-support>
93
94Instruct the B<lowerinvoke> pass to insert code for correct exception handling
95support. This is expensive and is by default omitted for efficiency.
96
97=item B<--stats>
98
99Print statistics recorded by code-generation passes.
100
101=item B<--time-passes>
102
103Record the amount of time needed for each pass and print a report to standard
104error.
105
106=item B<--load>=F<dso_path>
107
108Dynamically load F<dso_path> (a path to a dynamically shared object) that
109implements an LLVM target. This will permit the target name to be used with the
110B<-march> option so that code can be generated for that target.
111
112=back
113
114=head2 Tuning/Configuration Options
115
116=over
117
118=item B<--print-machineinstrs>
119
120Print generated machine code between compilation phases (useful for debugging).
121
122=item B<--regalloc>=I<allocator>
123
124Specify the register allocator to use. The default I<allocator> is I<local>.
125Valid register allocators are:
126
127=over
128
129=item I<simple>
130
131Very simple "always spill" register allocator
132
133=item I<local>
134
135Local register allocator
136
137=item I<linearscan>
138
139Linear scan global register allocator
140
141=item I<iterativescan>
142
143Iterative scan global register allocator
144
145=back
146
147=item B<--spiller>=I<spiller>
148
149Specify the spiller to use for register allocators that support it. Currently
150this option is used only by the linear scan register allocator. The default
151I<spiller> is I<local>. Valid spillers are:
152
153=over
154
155=item I<simple>
156
157Simple spiller
158
159=item I<local>
160
161Local spiller
162
163=back
164
165=back
166
167=head2 Intel IA-32-specific Options
168
169=over
170
171=item B<--x86-asm-syntax=att|intel>
172
173Specify whether to emit assembly code in AT&T syntax (the default) or intel
174syntax.
175
176=back
177
178=head1 EXIT STATUS
179
180If B<llc> succeeds, it will exit with 0. Otherwise, if an error occurs,
181it will exit with a non-zero value.
182
183=head1 SEE ALSO
184
185L<lli|lli>
186
187=head1 AUTHORS
188
189Maintained by the LLVM Team (L<http://llvm.org>).
190
191=cut