| Andrew Trick | 5469976 | 2011-04-07 19:54:57 +0000 | [diff] [blame] | 1 | ; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s |
| 2 | ; Tests preRAsched support for VRegCycle interference. |
| 3 | |
| 4 | target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" |
| 5 | target triple = "thumbv7-apple-darwin10" |
| 6 | |
| 7 | define void @t(i32 %src_width, float* nocapture %src_copy_start, float* nocapture %dst_copy_start, i32 %src_copy_start_index) nounwind optsize { |
| 8 | entry: |
| 9 | %src_copy_start6 = bitcast float* %src_copy_start to i8* |
| 10 | %0 = icmp eq i32 %src_width, 0 |
| 11 | br i1 %0, label %return, label %bb |
| 12 | |
| 13 | ; Make sure the scheduler schedules all uses of the preincrement |
| 14 | ; induction variable before defining the postincrement value. |
| 15 | ; CHECK: t: |
| Jakob Stoklund Olesen | feaf347 | 2011-05-03 22:31:21 +0000 | [diff] [blame^] | 16 | ; CHECK: %bb |
| Andrew Trick | 5469976 | 2011-04-07 19:54:57 +0000 | [diff] [blame] | 17 | ; CHECK-NOT: mov |
| 18 | bb: ; preds = %entry, %bb |
| 19 | %j.05 = phi i32 [ %2, %bb ], [ 0, %entry ] |
| 20 | %tmp = mul i32 %j.05, %src_copy_start_index |
| 21 | %uglygep = getelementptr i8* %src_copy_start6, i32 %tmp |
| 22 | %src_copy_start_addr.04 = bitcast i8* %uglygep to float* |
| 23 | %dst_copy_start_addr.03 = getelementptr float* %dst_copy_start, i32 %j.05 |
| 24 | %1 = load float* %src_copy_start_addr.04, align 4 |
| 25 | store float %1, float* %dst_copy_start_addr.03, align 4 |
| 26 | %2 = add i32 %j.05, 1 |
| 27 | %exitcond = icmp eq i32 %2, %src_width |
| 28 | br i1 %exitcond, label %return, label %bb |
| 29 | |
| 30 | return: ; preds = %bb, %entry |
| 31 | ret void |
| 32 | } |