r600g: move streamout state to drivers/radeon
This streamout state code will be used by radeonsi.
There are new structures r600_common_context and r600_common_screen.
What is inherited by what is shown here:
pipe_context -> r600_common_context -> r600_context
pipe_screen -> r600_common_screen -> r600_screen
The common structures reside in drivers/radeon. Currently they only contain
enough functionality to be able to handle streamout. Eventually I'd like
the whole pipe_screen implementation to be shared and some of the context
stuff too.
This is quite big, but most changes are because of the new structures and
the fact r600_write_value is replaced by radeon_emit.
Thanks to Tom Stellard for fixing the build for r600g/compute.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Tested-by: Tom Stellard <thomas.stellard@amd.com>
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index ea5a4e7..31d08a8 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -58,24 +58,23 @@
assert(id < R600_NUM_ATOMS);
assert(rctx->atoms[id] == NULL);
rctx->atoms[id] = atom;
- atom->id = id;
- atom->emit = emit;
+ atom->emit = (void*)emit;
atom->num_dw = num_dw;
atom->dirty = false;
}
void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
{
- r600_emit_command_buffer(rctx->rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
+ r600_emit_command_buffer(rctx->b.rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
}
void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
unsigned alpha_ref = a->sx_alpha_ref;
- if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) {
+ if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
alpha_ref &= ~0x1FFF;
}
@@ -89,7 +88,7 @@
{
struct r600_context *rctx = (struct r600_context *)ctx;
- rctx->flags |= R600_CONTEXT_INV_TEX_CACHE |
+ rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
R600_CONTEXT_FLUSH_AND_INV_CB |
R600_CONTEXT_FLUSH_AND_INV |
R600_CONTEXT_WAIT_3D_IDLE;
@@ -142,7 +141,7 @@
rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
update_cb = true;
}
- if (rctx->chip_class <= R700 &&
+ if (rctx->b.chip_class <= R700 &&
rctx->cb_misc_state.cb_color_control != color_control) {
rctx->cb_misc_state.cb_color_control = color_control;
update_cb = true;
@@ -178,25 +177,25 @@
void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct pipe_blend_color *state = &rctx->blend_color.state;
r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
- r600_write_value(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
- r600_write_value(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
- r600_write_value(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
- r600_write_value(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
+ radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
+ radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
+ radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
+ radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
}
void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
- r600_write_value(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
- r600_write_value(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
+ radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
+ radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
}
static void r600_set_clip_state(struct pipe_context *ctx,
@@ -227,15 +226,15 @@
void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
- r600_write_value(cs, /* R_028430_DB_STENCILREFMASK */
+ radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
S_028430_STENCILREF(a->state.ref_value[0]) |
S_028430_STENCILMASK(a->state.valuemask[0]) |
S_028430_STENCILWRITEMASK(a->state.writemask[0]));
- r600_write_value(cs, /* R_028434_DB_STENCILREFMASK_BF */
+ radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
S_028434_STENCILREF_BF(a->state.ref_value[1]) |
S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
@@ -282,7 +281,7 @@
ref.writemask[1] = dsa->writemask[1];
if (rctx->zwritemask != dsa->zwritemask) {
rctx->zwritemask = dsa->zwritemask;
- if (rctx->chip_class >= EVERGREEN) {
+ if (rctx->b.chip_class >= EVERGREEN) {
/* work around some issue when not writting to zbuffer
* we are having lockup on evergreen so do not enable
* hyperz when not writting zbuffer
@@ -299,7 +298,7 @@
rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
rctx->alphatest_state.atom.dirty = true;
- if (rctx->chip_class >= EVERGREEN) {
+ if (rctx->b.chip_class >= EVERGREEN) {
evergreen_update_db_shader_control(rctx);
} else {
r600_update_db_shader_control(rctx);
@@ -336,7 +335,7 @@
}
/* Workaround for a missing scissor enable on r600. */
- if (rctx->chip_class == R600 &&
+ if (rctx->b.chip_class == R600 &&
rs->scissor_enable != rctx->scissor.enable) {
rctx->scissor.enable = rs->scissor_enable;
rctx->scissor.atom.dirty = true;
@@ -368,7 +367,7 @@
{
if (state->dirty_mask) {
if (state->dirty_mask & state->has_bordercolor_mask) {
- rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
+ rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
}
state->atom.num_dw =
util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
@@ -427,11 +426,11 @@
r600_sampler_states_dirty(rctx, &dst->states);
/* Seamless cubemap state. */
- if (rctx->chip_class <= R700 &&
+ if (rctx->b.chip_class <= R700 &&
seamless_cube_map != -1 &&
seamless_cube_map != rctx->seamless_cube_map.enabled) {
/* change in TA_CNTL_AUX need a pipeline flush */
- rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
+ rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
rctx->seamless_cube_map.enabled = seamless_cube_map;
rctx->seamless_cube_map.atom.dirty = true;
}
@@ -500,8 +499,8 @@
void r600_vertex_buffers_dirty(struct r600_context *rctx)
{
if (rctx->vertex_buffer_state.dirty_mask) {
- rctx->flags |= R600_CONTEXT_INV_VERTEX_CACHE;
- rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
+ rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
+ rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
util_bitcount(rctx->vertex_buffer_state.dirty_mask);
rctx->vertex_buffer_state.atom.dirty = true;
}
@@ -557,8 +556,8 @@
struct r600_samplerview_state *state)
{
if (state->dirty_mask) {
- rctx->flags |= R600_CONTEXT_INV_TEX_CACHE;
- state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
+ rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
+ state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
util_bitcount(state->dirty_mask);
state->atom.dirty = true;
}
@@ -617,7 +616,7 @@
}
/* Changing from array to non-arrays textures and vice versa requires
* updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
- if (rctx->chip_class <= R700 &&
+ if (rctx->b.chip_class <= R700 &&
(dst->states.enabled_mask & (1 << i)) &&
(rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
@@ -674,16 +673,16 @@
void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct pipe_viewport_state *state = &rctx->viewport.state;
r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
- r600_write_value(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
- r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
- r600_write_value(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
- r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
- r600_write_value(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
- r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
+ radeon_emit(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
+ radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
+ radeon_emit(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
+ radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
+ radeon_emit(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
+ radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
}
/* Compute the key for the hw shader variant */
@@ -827,7 +826,7 @@
r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo);
- if (rctx->chip_class <= R700) {
+ if (rctx->b.chip_class <= R700) {
bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
if (rctx->cb_misc_state.multiwrite != multiwrite) {
@@ -841,7 +840,7 @@
rctx->cb_misc_state.atom.dirty = true;
}
- if (rctx->chip_class >= EVERGREEN) {
+ if (rctx->b.chip_class >= EVERGREEN) {
evergreen_update_db_shader_control(rctx);
} else {
r600_update_db_shader_control(rctx);
@@ -857,6 +856,7 @@
rctx->vertex_shader.shader = rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
rctx->vertex_shader.atom.dirty = true;
+ rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo);
@@ -912,8 +912,8 @@
void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
{
if (state->dirty_mask) {
- rctx->flags |= R600_CONTEXT_INV_CONST_CACHE;
- state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
+ rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
+ state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
: util_bitcount(state->dirty_mask)*19;
state->atom.dirty = true;
}
@@ -963,7 +963,7 @@
u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
}
/* account it in gtt */
- rctx->gtt += input->buffer_size;
+ rctx->b.gtt += input->buffer_size;
} else {
/* Setup the hw buffer. */
cb->buffer_offset = input->buffer_offset;
@@ -976,105 +976,6 @@
r600_constant_buffers_dirty(rctx, state);
}
-static struct pipe_stream_output_target *
-r600_create_so_target(struct pipe_context *ctx,
- struct pipe_resource *buffer,
- unsigned buffer_offset,
- unsigned buffer_size)
-{
- struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_so_target *t;
- struct r600_resource *rbuffer = (struct r600_resource*)buffer;
-
- t = CALLOC_STRUCT(r600_so_target);
- if (!t) {
- return NULL;
- }
-
- u_suballocator_alloc(rctx->allocator_so_filled_size, 4,
- &t->buf_filled_size_offset,
- (struct pipe_resource**)&t->buf_filled_size);
- if (!t->buf_filled_size) {
- FREE(t);
- return NULL;
- }
-
- t->b.reference.count = 1;
- t->b.context = ctx;
- pipe_resource_reference(&t->b.buffer, buffer);
- t->b.buffer_offset = buffer_offset;
- t->b.buffer_size = buffer_size;
-
- util_range_add(&rbuffer->valid_buffer_range, buffer_offset,
- buffer_offset + buffer_size);
- return &t->b;
-}
-
-static void r600_so_target_destroy(struct pipe_context *ctx,
- struct pipe_stream_output_target *target)
-{
- struct r600_so_target *t = (struct r600_so_target*)target;
- pipe_resource_reference(&t->b.buffer, NULL);
- pipe_resource_reference((struct pipe_resource**)&t->buf_filled_size, NULL);
- FREE(t);
-}
-
-void r600_streamout_buffers_dirty(struct r600_context *rctx)
-{
- rctx->streamout.num_dw_for_end =
- 12 + /* flush_vgt_streamout */
- util_bitcount(rctx->streamout.enabled_mask) * 8 + /* STRMOUT_BUFFER_UPDATE */
- 3 /* set_streamout_enable(0) */;
-
- rctx->streamout.begin_atom.num_dw =
- 12 + /* flush_vgt_streamout */
- 6 + /* set_streamout_enable */
- util_bitcount(rctx->streamout.enabled_mask) * 7 + /* SET_CONTEXT_REG */
- (rctx->family >= CHIP_RS780 &&
- rctx->family <= CHIP_RV740 ? util_bitcount(rctx->streamout.enabled_mask) * 5 : 0) + /* STRMOUT_BASE_UPDATE */
- util_bitcount(rctx->streamout.enabled_mask & rctx->streamout.append_bitmask) * 8 + /* STRMOUT_BUFFER_UPDATE */
- util_bitcount(rctx->streamout.enabled_mask & ~rctx->streamout.append_bitmask) * 6 + /* STRMOUT_BUFFER_UPDATE */
- (rctx->family > CHIP_R600 && rctx->family < CHIP_RS780 ? 2 : 0) + /* SURFACE_BASE_UPDATE */
- rctx->streamout.num_dw_for_end;
-
- rctx->streamout.begin_atom.dirty = true;
-}
-
-static void r600_set_streamout_targets(struct pipe_context *ctx,
- unsigned num_targets,
- struct pipe_stream_output_target **targets,
- unsigned append_bitmask)
-{
- struct r600_context *rctx = (struct r600_context *)ctx;
- unsigned i;
-
- /* Stop streamout. */
- if (rctx->streamout.num_targets && rctx->streamout.begin_emitted) {
- r600_emit_streamout_end(rctx);
- }
-
- /* Set the new targets. */
- for (i = 0; i < num_targets; i++) {
- pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], targets[i]);
- r600_context_add_resource_size(ctx, targets[i]->buffer);
- }
- for (; i < rctx->streamout.num_targets; i++) {
- pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], NULL);
- }
-
- rctx->streamout.enabled_mask = (num_targets >= 1 && targets[0] ? 1 : 0) |
- (num_targets >= 2 && targets[1] ? 2 : 0) |
- (num_targets >= 3 && targets[2] ? 4 : 0) |
- (num_targets >= 4 && targets[3] ? 8 : 0);
-
- rctx->streamout.num_targets = num_targets;
- rctx->streamout.append_bitmask = append_bitmask;
-
- if (num_targets) {
- r600_streamout_buffers_dirty(rctx);
- }
-}
-
static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
{
struct r600_context *rctx = (struct r600_context*)pipe;
@@ -1138,7 +1039,7 @@
cb.user_buffer = samplers->buffer_constants;
cb.buffer_offset = 0;
cb.buffer_size = array_size;
- rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
+ rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
pipe_resource_reference(&cb.buffer, NULL);
}
@@ -1168,7 +1069,7 @@
cb.user_buffer = samplers->buffer_constants;
cb.buffer_offset = 0;
cb.buffer_size = array_size;
- rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
+ rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
pipe_resource_reference(&cb.buffer, NULL);
}
@@ -1197,7 +1098,7 @@
cb.user_buffer = samplers->txq_constants;
cb.buffer_offset = 0;
cb.buffer_size = array_size;
- rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_TXQ_CONST_BUFFER, &cb);
+ rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_TXQ_CONST_BUFFER, &cb);
pipe_resource_reference(&cb.buffer, NULL);
}
@@ -1228,7 +1129,7 @@
((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
(rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
- if (rctx->chip_class >= EVERGREEN)
+ if (rctx->b.chip_class >= EVERGREEN)
evergreen_update_ps_state(ctx, rctx->ps_shader->current);
else
r600_update_ps_state(ctx, rctx->ps_shader->current);
@@ -1243,7 +1144,7 @@
/* on R600 we stuff masks + txq info into one constant buffer */
/* on evergreen we only need a txq info one */
- if (rctx->chip_class < EVERGREEN) {
+ if (rctx->b.chip_class < EVERGREEN) {
if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
@@ -1261,7 +1162,7 @@
if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
- if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
+ if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
if (!r600_adjust_gprs(rctx)) {
/* discard rendering */
return false;
@@ -1306,7 +1207,7 @@
void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_clip_misc_state *state = &rctx->clip_misc_state;
r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
@@ -1323,7 +1224,7 @@
struct pipe_draw_info info = *dinfo;
struct pipe_index_buffer ib = {};
unsigned i;
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
if (!info.count && (info.indexed || !info.count_from_stream_output)) {
assert(0);
@@ -1336,8 +1237,8 @@
}
/* make sure that the gfx ring is only one active */
- if (rctx->rings.dma.cs) {
- rctx->rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
+ if (rctx->b.rings.dma.cs) {
+ rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
}
if (!r600_update_derived_state(rctx)) {
@@ -1364,7 +1265,7 @@
&out_offset, &out_buffer, &ptr);
util_shorten_ubyte_elts_to_userptr(
- &rctx->context, &ib, 0, ib.offset, info.count, ptr);
+ &rctx->b.b, &ib, 0, ib.offset, info.count, ptr);
pipe_resource_reference(&ib.buffer, NULL);
ib.user_buffer = NULL;
@@ -1398,8 +1299,8 @@
}
/* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
- if (rctx->chip_class == R600) {
- rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
+ if (rctx->b.chip_class == R600) {
+ rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
rctx->cb_misc_state.atom.dirty = true;
}
@@ -1466,12 +1367,12 @@
cs->buf[cs->cdw++] = info.count;
cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
- cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, &rctx->rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
+ cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
}
} else {
if (info.count_from_stream_output) {
struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
- uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
+ uint64_t va = r600_resource_va(&rctx->screen->b.b, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
@@ -1483,7 +1384,7 @@
cs->buf[cs->cdw++] = 0; /* unused */
cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
- cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, &rctx->rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
+ cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
}
cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
@@ -1550,7 +1451,7 @@
viewport.translate[1] = 0.0f;
viewport.translate[2] = 0.0f;
viewport.translate[3] = 0.0f;
- rctx->context.set_viewport_states(&rctx->context, 0, 1, &viewport);
+ rctx->b.b.set_viewport_states(&rctx->b.b, 0, 1, &viewport);
/* Upload vertices. The hw rectangle has only 3 vertices,
* I guess the 4th one is derived from the first 3.
@@ -1578,7 +1479,7 @@
}
/* draw */
- util_draw_vertex_buffer(&rctx->context, NULL, buf, rctx->blitter->vb_slot, offset,
+ util_draw_vertex_buffer(&rctx->b.b, NULL, buf, rctx->blitter->vb_slot, offset,
R600_PRIM_RECTANGLE_LIST, 3, 2);
pipe_resource_reference(&buf, NULL);
}
@@ -1718,68 +1619,66 @@
void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
{
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader->current;
r600_emit_command_buffer(cs, &shader->command_buffer);
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
- r600_write_value(cs, r600_context_bo_reloc(rctx, &rctx->rings.gfx, shader->bo, RADEON_USAGE_READ));
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+ radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo, RADEON_USAGE_READ));
}
/* keep this at the end of this file, please */
void r600_init_common_state_functions(struct r600_context *rctx)
{
- rctx->context.create_fs_state = r600_create_ps_state;
- rctx->context.create_vs_state = r600_create_vs_state;
- rctx->context.create_vertex_elements_state = r600_create_vertex_fetch_shader;
- rctx->context.bind_blend_state = r600_bind_blend_state;
- rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
- rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
- rctx->context.bind_fs_state = r600_bind_ps_state;
- rctx->context.bind_rasterizer_state = r600_bind_rs_state;
- rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
- rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
- rctx->context.bind_vs_state = r600_bind_vs_state;
- rctx->context.delete_blend_state = r600_delete_blend_state;
- rctx->context.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
- rctx->context.delete_fs_state = r600_delete_ps_state;
- rctx->context.delete_rasterizer_state = r600_delete_rs_state;
- rctx->context.delete_sampler_state = r600_delete_sampler_state;
- rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements;
- rctx->context.delete_vs_state = r600_delete_vs_state;
- rctx->context.set_blend_color = r600_set_blend_color;
- rctx->context.set_clip_state = r600_set_clip_state;
- rctx->context.set_constant_buffer = r600_set_constant_buffer;
- rctx->context.set_sample_mask = r600_set_sample_mask;
- rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
- rctx->context.set_viewport_states = r600_set_viewport_states;
- rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
- rctx->context.set_index_buffer = r600_set_index_buffer;
- rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
- rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
- rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
- rctx->context.texture_barrier = r600_texture_barrier;
- rctx->context.create_stream_output_target = r600_create_so_target;
- rctx->context.stream_output_target_destroy = r600_so_target_destroy;
- rctx->context.set_stream_output_targets = r600_set_streamout_targets;
- rctx->context.draw_vbo = r600_draw_vbo;
+ rctx->b.b.create_fs_state = r600_create_ps_state;
+ rctx->b.b.create_vs_state = r600_create_vs_state;
+ rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
+ rctx->b.b.bind_blend_state = r600_bind_blend_state;
+ rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
+ rctx->b.b.bind_fragment_sampler_states = r600_bind_ps_sampler_states;
+ rctx->b.b.bind_fs_state = r600_bind_ps_state;
+ rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
+ rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
+ rctx->b.b.bind_vertex_sampler_states = r600_bind_vs_sampler_states;
+ rctx->b.b.bind_vs_state = r600_bind_vs_state;
+ rctx->b.b.delete_blend_state = r600_delete_blend_state;
+ rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
+ rctx->b.b.delete_fs_state = r600_delete_ps_state;
+ rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
+ rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
+ rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
+ rctx->b.b.delete_vs_state = r600_delete_vs_state;
+ rctx->b.b.set_blend_color = r600_set_blend_color;
+ rctx->b.b.set_clip_state = r600_set_clip_state;
+ rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
+ rctx->b.b.set_sample_mask = r600_set_sample_mask;
+ rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
+ rctx->b.b.set_viewport_states = r600_set_viewport_states;
+ rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
+ rctx->b.b.set_index_buffer = r600_set_index_buffer;
+ rctx->b.b.set_fragment_sampler_views = r600_set_ps_sampler_views;
+ rctx->b.b.set_vertex_sampler_views = r600_set_vs_sampler_views;
+ rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
+ rctx->b.b.texture_barrier = r600_texture_barrier;
+ rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
+ rctx->b.b.draw_vbo = r600_draw_vbo;
}
void r600_trace_emit(struct r600_context *rctx)
{
struct r600_screen *rscreen = rctx->screen;
- struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+ struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
uint64_t va;
uint32_t reloc;
- va = r600_resource_va(&rscreen->screen, (void*)rscreen->trace_bo);
- reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
- r600_write_value(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
- r600_write_value(cs, va & 0xFFFFFFFFUL);
- r600_write_value(cs, (va >> 32UL) & 0xFFUL);
- r600_write_value(cs, cs->cdw);
- r600_write_value(cs, rscreen->cs_count);
- r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
- r600_write_value(cs, reloc);
+ va = r600_resource_va(&rscreen->b.b, (void*)rscreen->trace_bo);
+ reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
+ radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
+ radeon_emit(cs, va & 0xFFFFFFFFUL);
+ radeon_emit(cs, (va >> 32UL) & 0xFFUL);
+ radeon_emit(cs, cs->cdw);
+ radeon_emit(cs, rscreen->cs_count);
+ radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
+ radeon_emit(cs, reloc);
}